EL2095 Digital System Boolean Algebra (CH2)...Sekolah Teknik Elektro dan Informatika Institut...
Transcript of EL2095 Digital System Boolean Algebra (CH2)...Sekolah Teknik Elektro dan Informatika Institut...
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EL2095 Digital SystemBoolean Algebra (CH2)
Sekolah Teknik Elektro dan InformatikaInstitut Teknologi Bandung
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Introduction
Let’s learn to design digital circuits We’ll start with a simple form of circuit: Combinational circuit
A digital circuit whose outputs depend solely on the present combination of the circuit inputs’ values
Combinational
digital circuit
1a
b
1F0
1a
b
?F0
Digital circuit
Sequential
digital circuit
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Switches Electronic switches are the basis of binary digital circuits Electrical terminology
Voltage: Difference in electric potential between two points Analogous to water pressure
Current: Flow of charged particles Analogous to water flow
Resistance: Tendency of wire to resist current flow Analogous to water pipe diameter
V = I * R (Ohm’s Law)
4.5 A4.5 A
4.5 A
2 ohms
9V
0V 9V
+–
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Switches A switch has three parts
Source input, and output Current wants to flow from source input to output
Control input Voltage that controls whether that current can flow
The amazing shrinking switch 1930s: Relays 1940s: Vacuum tubes 1950s: Discrete transistor 1960s: Integrated circuits (ICs)
Initially just a few transistors on IC Then tens, hundreds, thousands...
“off”
“on”
outputsourceinput
outputsourceinput
controlinput
controlinput
(b)
relay vacuum tube
discrete transistor
IC
quarter(to see the relative size)
a
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Moore’s Law IC capacity doubling about every 18 months for several decades Known as “Moore’s Law” after Gordon Moore,
co‐founder of Intel Predicted in 1965 predicted that components per IC would double roughly every year or so
Book cover depicts related phenomena For a particular number of transistors, the IC shrinks by half every 18 months Notice how much shrinking occurs in just about 10
years Enables incredibly powerful computation in incredibly
tiny devices
Today’s ICs hold billions of transistors The first Pentium processor (early 1990s) needed only 3 million
An Intel Pentium processor IChaving millions of transistors
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The CMOS Transistor CMOS (Complementary Metal‐Oxide Semiconductor) transistor Basic switch in modern ICs
gate
source drainoxide
A positivevoltage here...
...attracts electrons here,turning the channel
between source and draininto aconductor.
(a)
IC package
IC
does notconduct
0
conducts
1gate
nMOS
does notconduct
1gate
pMOS
conducts
0
Silicon -- not quite a conductor or insulator:Semiconductor
a
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Boolean Logic GatesBuilding Blocks for Digital Circuits (Because Switches are Hard to Work With)
“Logic gates” are better digital circuit building blocks than switches (transistors) Why?...
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Boolean Algebra and its Relation to Digital Circuits To understand the benefits of “logic gates” vs. switches, we should first understand Boolean algebra
“Traditional” algebra Variable represent real numbers Operators operate on variables, return real numbers
Boolean Algebra Variables represent 0 or 1 only Operators return 0 or 1 only Basic operators
AND: a AND b returns 1 only when both a=1 and b=1 OR: a OR b returns 1 if either (or both) a=1 or b=1 NOT: NOT a returns the opposite of a (1 if a=0, 0 if a=1)
a0011
b0101
AND0001
a0011
b0101
OR0111
a01
NOT10
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Boolean Algebra and its Relation to Digital Circuits Developed mid‐1800’s by George Boole to formalize human thought Ex: “I’ll go to lunch if Mary goes OR John goes, AND Sally does not go.” Let F represent my going to lunch (1 means I go, 0 I don’t go) Likewise, m for Mary going, j for John, and s for Sally Then F = (m OR j) AND NOT(s)
Nice features Formally evaluate m=1, j=0, s=1 ‐‐> F = (1 OR 0) AND NOT(1) = 1 AND 0 = 0
Formally transform F = (m and NOT(s)) OR (j and NOT(s)) Looks different, but same function We’ll show transformation techniques soon
a0011
b0101
AND0001
a0011
b0101
OR0111
a01
NOT10
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Evaluating Boolean Equations Evaluate the Boolean equation F = (a AND b) OR (c AND d) for the given values of variables a, b, c, and d: Q1: a=1, b=1, c=1, d=0.
Answer: F = (1 AND 1) OR (1 AND 0) = 1 OR 0 = 1.
Q2: a=0, b=1, c=0, d=1. Answer: F = (0 AND 1) OR (0 AND 1) = 0 OR 0 = 0.
Q3: a=1, b=1, c=1, d=1. Answer: F = (1 AND 1) OR (1 AND 1) = 1 OR 1 = 1.
a
a0011
b0101
AND0001
a0011
b0101
OR0111
a01
NOT10
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Converting to Boolean Equations Convert the following English statements to a Boolean equation Q1. a is 1 and b is 1.
Answer: F = a AND b
Q2. either of a or b is 1. Answer: F = a OR b
Q3. both a and b are not 0. Answer: (a) Option 1: F = NOT(a) AND NOT(b) (best solution) (b) Option 2: F = a OR b (can be a solution)
Q4. a is 1 and b is 0. Answer: F = a AND NOT(b)
a
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Converting to Boolean Equations Q1. A fire sprinkler system should spray water if high heat is sensed and the system is set to enabled. Answer: Let Boolean variable h represent “high heat is sensed,” e
represent “enabled,” and F represent “spraying water.” Then an equation is: F = h AND e.
Q2. A car alarm should sound if the alarm is enabled, and either the car is shaken or the door is opened. Answer: Let a represent “alarm is enabled,” s represent “car is shaken,”
d represent “door is opened,” and F represent “alarm sounds.” Then an equation is: F = a AND (s OR d).
(a) Alternatively, assuming that our door sensor d represents “door is closed” instead of open (meaning d=1 when the door is closed, 0 when open), we obtain the following equation: F = a AND (s OR NOT(d)).
a
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Relating Boolean Algebra to Digital Design
Implement Boolean operators using transistors Call those implementations logic gates. Let’s us build circuits by doing math ‐‐ powerful
concept
Booleanalgebra
(mid-1800s)
Boole’s intent: formalizehuman thought
Switches(1930s)
Shannon (1938)
Digital design
Showed applicationof Boolean algebrato design of switch-
based circuits
x0011
y0101
F0001
x0011
y0101
F0111
x01
F10
Fxxy F
ORNOT
Fxy
AND
Symbol
Truth tableFor telephoneswitching and other
electronic uses
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Building Circuits Using Gates
Recall Chapter 1 motion‐in‐dark example Turn on lamp (F=1) when motion sensed (a=1) and no light (b=0) F = a AND NOT(b) Build using logic gates, AND and NOT, as shown We just built our first digital circuit!
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Example: Converting a Boolean Equation to a Circuit of Logic Gates
Q: Convert the following equation to logic gates: F = a AND NOT( b OR NOT(c) )
aF
(a)
ab
cF
(b)
a
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Example: Converting a Boolean Equation to a Circuit of Logic Gates
Q: Convert the following equation to logic gates: F = a AND (s OR d)
a
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Example: Converting a Boolean Equation to a Circuit of Logic Gates
Q: Convert the following equation to logic gates: F = (a AND NOT(b)) OR (b AND NOT(c))
a
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Example: Using AND and OR gates with more than two inputs
Q: Convert the following equation to logic gates: F = a AND b AND c
Use two input AND gates Use three input AND gate
a
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Example: Seat Belt Warning Light System Design circuit for warning light Sensors
s=1: seat belt fastened k=1: key inserted
Capture Boolean equation seat belt not fastened, and key inserted
Convert equation to circuit Notice
Boolean algebra enables easy capture as equation and conversion to circuit How design with switches? Of course, logic gates are built from
switches, but we think at level of logic gates, not switches
w = k AND NOT(s)
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Example: Seat Belt Warning Light System Draw the timing diagram
w = k AND NOT(s)
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Example: Seat Belt Warning Light System Design circuit for warning light Sensors
s=1: seat belt fastened k=1: key inserted p=1: person in seat
Capture Boolean equation person in seat, and seat belt not fastened,
and key inserted Convert equation to circuit Notice
Boolean algebra enables easy capture as equation and conversion to circuit How design with switches? Of course, logic gates are built from
switches, but we think at level of logic gates, not switches
w = p AND NOT(s) AND k
k
p
s
w
BeltWarn
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Some Circuit Drawing Conventions
xy
F
no yes
no
not ok
ok
yes
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Boolean Algebra By defining logic gates based on Boolean algebra, we can use algebraic methods
to manipulate circuits So let’s learn some Boolean algebraic methods
Start with notation: Writing a AND b, a OR b, and NOT(a) is cumbersome Use symbols: a * b, a + b, and a’ (in fact, a * b can be just ab).
Original: w = (p AND NOT(s) AND k) OR t New: w = ps’k + t
Spoken as “w equals p and s prime and k, or t” Or even just “w equals p s prime k, or t” s’ known as “complement of s”
While symbols come from regular algebra, don’t say “times” or “plus”
Boolean algebra precedence, highest precedence first.
Symbol Name Description
( ) Parentheses Evaluate expressions nested in parentheses first
’ NOT Evaluate from left to right
* AND Evaluate from left to right
+ OR Evaluate from left to right
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Boolean Algebra Operator Precendence Evaluate the following Boolean equations, assuming a=1, b=1, c=0, d=1. Q1. F = a * b + c.
Answer: * has precedence over +, so we evaluate the equation as F = (1 *1) + 0 = (1) + 0 = 1 + 0 = 1.
Q2. F = ab + c. Answer: the problem is identical to the previous problem, using the shorthand notation for *.
Q3. F = ab’. Answer: we first evaluate b’ because NOT has precedence over AND, resulting in F = 1 * (1’) = 1 * (0) = 1 * 0 = 0.
Q4. F = (ac)’. Answer: we first evaluate what is inside the parentheses, then we NOT the result, yielding (1*0)’ = (0)’ = 0’ = 1.
Q5. F = (a + b’) * c + d’. Answer: Inside left parentheses: (1 + (1’)) = (1 + (0)) = (1 + 0) = 1. Next, * has precedence over +, yielding (1 * 0) + 1’ = (0) + 1’. The NOT has precedence over the OR, giving (0) + (1’) = (0) + (0) = 0 + 0 = 0.
a
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Boolean Algebra Terminology Example equation: F(a,b,c) = a’bc + abc’ + ab + c Variable Represents a value (0 or 1) Three variables: a, b, and c
Literal Appearance of a variable, in true or complemented form Nine literals: a’, b, c, a, b, c’, a, b, and c
Product term Product of literals Four product terms: a’bc, abc’, ab, c
Sum‐of‐products Equation written as OR of product terms only Above equation is in sum‐of‐products form. “F = (a+b)c + d” is not.
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Boolean Algebra Operator Precedence
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Fundamentals of Boolean Algebra (Basic Postulate Postulate 1. If x, y A, then
x + y A x ∙ y A
This is called the closure property.
Postulate 2. Identity elements, denoted as 0 and 1, must exist such that a) x + 0 = x b) x ∙ 1 = x for all elements of A.
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Fundamentals of Boolean Algebra (Basic Postulate Postulate 3. If x, y A, then
a) x + y = y + xb) x ∙ y = y ∙ x that is, + and ∙ operations are commutative.
Postulate 4. If x, y, z A, thena) x + (y + z) = (x + y) + xb) x ∙ (y ∙ z) = (x ∙ y) ∙ z that is, + and ∙ operations are associative.
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Fundamentals of Boolean Algebra (Basic Postulate Postulate 5. If x, y, z A, then
a) x + (y ∙ z) = (x + y) ∙ (x + z)b) x ∙ (y + z) = (x ∙ y) + (x ∙ z) that is, + and ∙ operations are distributive.
Postulate 6. For every element x in A there exists an element x’, called the complement of x, such thata) x + x’ = 1b) x ∙ x’ = 0
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Duality The principle of duality If an expression is valid on Boolean Algebra, then the dual of the expression is also valid
Found by replacing All + operator with ∙ All ∙ operator with + All ones with zeros All zeros with ones
Example Find the dual of the expression
a + (bc) = (a+b)(a+c) a(b+c) = ab + ac Careful not to alter the position of the parentheses
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Finding Dual f(a,b)=a+b dual of f(a,b)=a∙b
f(x)=x+0 dual of f(x)=x∙1
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Boolean Algebra Properties Identity P2
a) 0 + a = a + 0 = ab) 1 * a = a * 1 = a
Commutative P3a) a + b = b + ab) a * b = b * a
Associative P4a) (a + b) + c = a + (b + c)b) (a * b) * c = a * (b * c)
Distributive P5a) a + (b * c) = (a + b) * (a + c)
(this one is tricky!)b) a * (b + c) = a * b + a * c
Complement P6a) a + a’ = 1b) a * a’ = 0
Show abc’ equivalent to c’ba. Use commutative property:
a*b*c’ = a*c’*b = c’*a*b = c’*b*a = c’ba. Show abc + abc’ = ab.
Use first distributive property abc + abc’ = ab(c+c’).
Complement property Replace c+c’ by 1: ab(c+c’) = ab(1).
Identity property ab(1) = ab*1 = ab.
Show x + x’z equivalent to x + z. Second distributive property
Replace x+x’z by (x+x’)*(x+z). Complement property
Replace (x+x’) by 1, Identity property
replace 1*(x+z) by x+z.
Example uses of the properties
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Example that Applies Boolean Algebra Properties Want automatic door opener circuit
(e.g., for grocery store) Output: f=1 opens door Inputs:
p=1: person detected h=1: switch forcing hold open c=1: key forcing closed
Want open door when h=1 and c=0, or h=0 and p=1 and c=0
Equation: f = hc’ + h’pc’
Found inexpensive chip that computes:
f = c’hp + c’hp’ + c’h’p Can we use it?
Is it the same as f = c’(p+h)?
Use Boolean algebra:
f = c’hp + c’hp’ + c’h’p
f = c’h(p + p’) + c’h’p (by the distributive property)
f = c’h(1) + c’h’p (by the complement property)
f = c’h + c’h’p (by the identity property)
f = hc’ + h’pc’ (by the commutative property)
Same!
fh
cp
DoorOpener
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Fundamental Theorems of Boolean Algebra Theorem 1. The Idempotent Laws
a) x + x = xb) x ∙ x = x Proof
x + x = (x + x)1 P2(b) = (x + x)(x + x’) P6(a) = x + xx’ P5(a) = x + 0 P6(b) = x P2(a)
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Fundamental Theorems of Boolean Algebra Theorem 2. Null elements for + and ∙ operators
a) x + 1 = 1b) x ∙ 0 = 0 Proof
x + 1 = (x + 1)1 P2(b) = 1(x + 1) P3(b) = (x + x’)(x + 1) P6(a) = x + x’1 P5(a) = x + x’ P2(b) = 1 P6(a)
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Fundamental Theorems of Boolean Algebra Theorem 3. Involution (x’)’ = x Proof
From 5(a) : x’ is the complement of x and x is the complement of x’. Since the complement of x’ is unique then (x’)’ = x
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Fundamental Theorems of Boolean Algebra Theorem 4. Absorption
a) x + xy = xb) x (x + y) = x Proof
x + xy = x ∙ 1 + xy P2(b) = x(1 + y) P5(b) = x(y + 1) P3(b) = x ∙ 1 T2(a) = x P2(b)
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Example (x + y) + (x + y)z (x + y) + (x + y)z = x + y T4(a)
AB’(AB’ + B’C) AB’(AB’ + B’C) = AB’ T4(b)
AB’C + B’ AB’C + B’ = B’ T4(a)
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Fundamental Theorems of Boolean Algebra Theorem 5.
a) x + x’y = x + yb) x (x’ + y) = xy Proof
x + x’y = (x + x’)(x + y) P5(a) = 1(x + y) P6(a) = (x + y)1 P3(b) = (x + y) P2(b)
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Example B + AB’C’D B + AB’C’D = B + AC’D T5(a)
Y’(X + Y + Z) Y’(X + Y + Z) = Y’(X + Z) T5(b)
(X + Y)((X + Y)’ + Z) (X + Y)((X + Y)’ + Z) = (X + Y)Z T5(b)
AB + (AB)’CD’ AB + (AB)’CD’ = AB + CD’ T5(a)
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Fundamental Theorems of Boolean Algebra Theorem 6.
a) xy + xy’ = xb) (x + y)(x + y’) = x Proof
xy + xy’ = x(y + y’) P5(b) = x ∙ 1 P6(a) = x P2(b)
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Example ABC + AB’C ABC + AB’C = AC T6(a)
(AD + B + C)(AD + (B + C)’) (AD + B + C)(AD + (B + C)’) = AD T6(b)
(W’+X’+Y’+Z’)(W’+X’+Y’+Z)(W’+X’+Y+Z’)(W’+X’+Y+Z) = (W’+X’+Y’)(W’+X’+Y+Z’)(W’+X’+Y+Z) T6(b) = (W’+X’+Y’)(W’+X’+Y) T6(b) = (W’+X’) T6(b)
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Fundamental Theorems of Boolean Algebra Theorem 7.
a) xy + xy’z = xy + xzb) (x + y)(x + y’ + z) = (x + y)(x + z) Proof
xy + xy’z = x(y + y’z) P5(b) = x(y + z) T5(a) = xy + xz P5(b)
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Example xy + xy’(w’+z’) xy + xy’(w’+z’) = xy + x(w’+z’) T7(a)
(x’y’ + z)(w + x’y’ + z’) (x’y’ + z)(w + x’y’ + z’) = (x’y’ + z)(w + x’y’) T7(b)
(A’+B’+C’)(B’+C)(A+B’) = (A’+B’)(B’+C)(A+B’) T7(b) = B’(B’+C) T6(b) = B’ T4(b)
wy’+ wx’y + wxyz + wxz’ = wy’+ wx’y + wxy + wxz’ T7(a) = wy’ + wy + wxz’ T6(a) = w + wxz’ T6(a) = w T4(a)
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Fundamental Theorems of Boolean Algebra Theorem 8. DeMorgan’s Theorem
a) (x + y)’ = x’ ∙ y’b) (x ∙ y)’ = (x’ + y’) Proof
Let A = x + y and A’ = (x + y)’ By P6 : A ∙ A’ = 0 and A + A’ = 1 If A ∙ B = 0 and A + B = 1 then B = A’ Therefore, we let B = x’ ∙ y’ and test A ∙ B and A + B
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DeMorgans Theorems Proof A ∙ B = (x + y)(x’y’) = (x’y’)(x + y) P3(b) = (x’y’)x + (x’y’)y P5(b) = x(x’y’) + (x’y’)y P3(b) = (xx’)y’ + x’(y’y) P4(b) = 0 ∙ y’ + x’(y ∙ y’) P6(b), P3(b) = y’ (X + Y’)’ 0 + x’ ∙ 0
P3(b), P6(b) = 0 + 0 T2(b) = 0 P2(a)
A + B = (x + y) + (x’y’) = (y + x) + (x’y’) P3(a) = y + (x + x’y’) P4(a) = y + (x + y’) T5(a) = (x + y’) + y P3(a) = x + (y’ + y) P4(a) = x + (y + y’) P3(a) = x + 1 P6(a) = 1 T2(a)
Therefore B = A’ then x’y’ = (x + y)’
Can be generalizeda) (a + b + … + z)’ = a’ ∙ b’ ∙ ∙ ∙ z’b) (ab ∙ ∙ ∙z)’ = a’ + b’ + … + z’
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Example Complement the expression a + bc (a + bc)’ = (a + (b ∙ c))’ = a’ ∙ (b ∙ c)’ = a’ ∙ (b’ + c’) = a’b’ + a’c’
(X + Y’)’ (X + Y’)’ = X’ ∙ (Y’)’ T8(a) = X’ ∙ Y T3
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Example (a(b+z(x+a’)))’ (simplify until the only complementedterms are individual variable) (a(b+z(x+a’)))’ = a’ + (b+z(x+a’))’ T8(b) = a’ + b’(z(x+a’))’ T8(a) = a’ + b’(z’+(x+a’)’) T8(b) = a’ + b’(z’ + x’(a’)’) T8(a) = a’ + b’(z’ + x’a) T3 = a’ + b’(z’ + x’) T5(a)
(a(b+c)+a’b)’ (a(b+c)+a’b)’ = (ab + ac + a’b)’ P5(b) = (b + ac)’ T6(a) = b’(ac)’ T8(a) = b’(a’ + c’) T8(b)
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Fundamental Theorems of Boolean Algebra Theorem 9. Concensus
a) xy + x’z + yz = xy + x’zb) (x + y)(x’ + z)(y + z) = (x + y)(x’ +z) Proof
xy + x’z + yz = xy + x’z + 1yz P2(b) = xy + x’z + (x + x’)yz P6(a) = xy + x’z + xyz + x’yz P5(b) = (xy + xyz)(x’z + x’yz) T4(a) = xy + x’z
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Example AB + A’CD + BCD AB + A’CD + BCD = AB + A’CD
(a+b’)(a’+c)(b’+c) (a+b’)(a’+c)(b’+c) = (a+b’)(a’+c)
ABC + A’D + B’D + CD ABC + A’D + B’D + CD = ABC + (A’ + B’)D + CD P5(b) = ABC + (AB)’D + CD T8(b) = ABC + (AB)’D T9(a) = ABC + (A’ + B’)D T8(a) = ABC + A’D + B’D P5(b)
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Boolean Algebra: Additional Properties Null elements
a + 1 = 1 a * 0 = 0
Idempotent Law a + a = a a * a = a
Involution Law (a’)’ = a
DeMorgan’s Law (a + b)’ = a’b’ (ab)’ = a’ + b’ Very useful!
To prove, just evaluate all possibilities
Circuita
b
c
S
• Behavior• Three lavatories, each with
sensor (a, b, c), equals 1 if door locked
• Light “Available” sign (S) if any lavatory available
• Equation and circuit• S = a’ + b’ + c’
• Transform• (abc)’ = a’+b’+c’ (by
DeMorgan’s Law)• S = (abc)’
• New equation and circuit
CircuitSa
bc
• Alternative: Instead of lighting “Available,” light “Occupied”
– Opposite of “Available” function S = a’ + b’ + c’
– So S’ = (a’ + b’ + c’)’• S’ = (a’)’ * (b’)’ * (c’)’
(by DeMorgan’s Law)
• S’ = a * b * c (by Involution Law)
– Makes intuitive sense• Occupied if all doors
are locked
Aircraft lavatory sign example
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Signal Active States and Bubbles Depends on positive or negative logic So we denote a signal is active or not active Active State ‐ signal state (0 or 1) that indicates the assertion of some condition or action
Also called the excitation state A signal is asserted when it is in the active state A signal is negated when it is in the inactive state Active‐1 (active high) is when active state is logic 1 Active‐0 (active low) is when active state is logic 0
Symbol pins without bubbles denote active‐1 Symbol pins with bubbles denote active‐0
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Inverter
Inverter (NOT operator) has two different forms
Input assertedactive‐1
Output assertedactive‐0
Input assertedactive‐0
Output assertedactive‐1
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AND Gate Alternate Symbol
X0011
Y0101
X∙Y0001
XFFTT
YFTFT
X∙YFFFT
XTTFF
YTFTF
X+YTTTF
Active‐1
Active‐0
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OR Gate Alternate Symbol
X0011
Y0101
X+Y0111
XFFTT
YFTFT
X+YFTTT
XTTFF
YTFTF
X∙YTFFF
Active‐1
Active‐0
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Other Gate Alternative Symbols
NAND
NOR
XOR
XNOR
Active‐1 Active‐0
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Representations of Boolean Functions
A function can be represented in different ways Above shows seven representations of the same functions F(a,b), using four
different methods: English, Equation, Circuit, and Truth Table
a
a
b
F
F
Circuit 1
Circuit 2
(c)
(d)
English 1: F outputs 1 when a is 0 and b is 0, or when a is 0 and b is 1.English 2: F outputs 1 when a is 0, regardless of b’s value
(a)
(b)
a0011
b0101
F1100
The function F
Truth table
Equation 2: F(a,b) = a’Equation 1: F(a,b) = a’b’ + a’b
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Truth Table Representation of Boolean Functions Define value of F for each possible combination of input values 2‐input function: 4 rows 3‐input function: 8 rows 4‐input function: 16 rows
Q: Use truth table to define function F(a,b,c) that is 1 when abc is 5 or greater in binary
c0011001100110011
d0101010101010101
a0000000011111111
b0000111100001111
Fc01010101
a00001111
b00110011
Fa0011
b0101
F
(a)
(b)
(c)
c01010101
a00001111
b00110011
F00000
11
1
a
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Converting among Representations1. Equation to Circuit Straightforward
2. Circuit to Equation Start from Circuit input to output
3. Equation to Truth Table Evaluate for all inputs
4. Truth Table to Equation Create the sum of product terms
5. Circuit to Truth Table Circuit to equation then truth table
6. Truth Table to Circuit Truth table to equation then circuit
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Converting among Representations Can convert from any representation to
any other Common conversions
Equation to circuit (we did this earlier) Truth table to equation (which we can
convert to circuit) Easy ‐‐ just OR each input term that should
output 1 Equation to truth table
Easy ‐‐ just evaluate equation for each input combination (row)
Creating intermediate columns helps
a0011
b0101
FInputs Output
a' b' a' b
a0011
b0101
F1100
Inputs OutputsF = sum ofa’b’a’b
Term
F = a’b’ + a’b
c01010101
a00001111
b00110011
F00000
11
1
Q: Convert to equation
a
F = ab’c + abc’ + abc
ab’cabc’abc1
100
1000
0100
a
Q: Convert to truth table: F = a’b’ + a’b
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Standard Representation: Truth Table How can we determine if two
functions are the same? Recall automatic door example
Same as f = hc’ + h’pc’? Used algebraic methods But if we failed, does that prove not
equal? No.
Solution: Convert to truth tables Only ONE truth table representation
of a given function Standard representation ‐‐ for given
function, only one version in standard form exists
f = c’hp + c’hp’ + c’h’
f = c’h(p + p’) + c’h’p
f = c’h(1) + c’h’p
f = c’h + c’h’p
(what if we stopped here?)
f = hc’ + h’pc’
a0011
b0101
F1101
F = ab + a'
a0011
b0101
F1101
F = a’b’ + a’b + ab
Q: Determine if F=ab+a’ is samefunction as F=a’b’+a’b+ab, by convertingeach to truth table first
a
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Algebraic Forms of Switching Functions Formulation of Boolean Algebra Equations Sum of Products (SOP) is the logical OR of product terms. Each product terms is the AND of binary literals. xy’ + x’ + yz + xy’z
Product of Sums (POS) is the logical AND of sum terms. Each sum terms is the OR of binary literals. (x + y + z)(y’ + z’)
Minterms is a special case product terms. Minterms contains all the input variable (each literal no more than once)
Maxterms is a special case of sum terms. Maxterms contains all the input variable (each literal no more than once)
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Canonical Form Truth tables too big for numerous inputs Use standard form of equation instead Known as canonical form Regular algebra: group terms of polynomial by power
ax2 + bx + c (3x2 + 4x + 2x2 + 3 + 1 ‐‐> 5x2 + 4x + 4) Boolean algebra:
Canonical SOP or POS forms SOP of minterms POS of maxterms
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Canonical Form Boolean algebra: SOP of minterms
Uncomplemented variable: 1 Complemented variable: 0 Example
A’BC’ : 010
POS of maxterms Uncomplemented variable: 0 Complemented variable: 1 Example
A’+B+C’ : 101
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Minterm & Maxterm Notations
Input Variables MInterms Maxterms
a b c Terms Designation Terms Designation
0 0 0 a’b’c’ m0 a+b+c M0
0 0 1 a’b’c m1 a+b+c’ M1
0 1 0 a’bc’ m2 a+b’+c M2
0 1 1 a’bc m3 a+b’+c’ M3
1 0 0 ab’c’ m4 a’+b+c M4
1 0 1 ab’c m5 a’+b+c’ M5
1 1 0 abc’ m6 a’+b’+c M6
1 1 1 abc m7 a’+b’+c’ M7
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Procedure to place boolean expression in canonical forms SOP Identify missing variables in each product term AND the missing term and its complement Expand the terms using distributive property
Example xy xy(z + z’) because (z + z’) = 1 xyz + xyz’
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Procedure to place boolean expression in canonical forms POS Identify missing variables in each product term OR the missing term and its complement Expand the terms using distributive property
Example (x + y) (x + y + zz’) because zz’ = 0 (x + y + z)(x + y + z’)
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Examples f(a,b,c) = ab’ + ac’ + bc ab’(c + c’) = ab’c + ab’c’ ac’ (b + b’) = abc’ + ab’c’ bc(a + a’) = abc + a’bc f(a,b,c) = ab’c + ab’c’ + abc’ + ab’c’ + abc + a’bc
The second and fourth terms are the identical Only one is needed
f(a,b,c) = ab’c + ab’c’ + abc’ + abc + a’bc
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Examples f(w,x,y,z) = w’x + yz’ w’x(y + y’)(z + z’) = (w’xy + w’xy’)(z + z’)
= w’xyz + w’xyz’ + w’xy’z + w’xy’z’ yz’(w + w’)(x + x’) = (wyz’ + w’yz’)(x + x’)
= wxyz’ + wx’yz’ + w’xyz’ + w’x’yz’ f(w,x,y,z) = w’xyz + w’xyz’ + w’xy’z + w’xy’z’ + wxyz’ + wx’yz’ +
w’xyz’ + w’x’yz’ f(w,x,y,z) = w’xyz + w’xyz’ + w’xy’z + w’xy’z’ + wxyz’ + wx’yz’ +
w’x’yz’
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Examples f(a,b,c) = (a + b’)(b’ + c) a + b’ + cc’ = (a + b’ + c)(a + b’ + c’) b’ + c + aa’ = (a + b’ + c)(a’ + b’ + c) f(a,b,c) = (a + b’ + c)(a + b’ + c’)(a + b’ + c)(a’ + b’ + c) f(a,b,c) = (a + b’ + c)(a + b’ + c’) (a’ + b’ + c)
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Canonical Form Example
Q: Determine if F(a,b)=ab+a’ is same function as F(a,b)=a’b’+a’b+ab, by converting first equation to canonical form (second already in canonical form)
F = ab+a’ (already sum of products)F = ab + a’(b+b’) (expanding term)F = ab + a’b + a’b’ (SAME -- same three terms as other equation)
a
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Exercise SOP f(a,b,c) = ab + ac’ + a’c f(p,q,s) = p(q’ + s)
POS f(w,x,y,z) = (w’+ x)(y + z’) f(a,b,c,d) = (a + b’ + c)(a’ + d)
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More concise notation of canonical forms (SOP) f(a,b,c) = a’bc’ + abc’ + a’bc + abc
f(a,b,c) = m2 + m3 + m6 + m7
f(a,b,c) = ∑m(2, 3, 6, 7) Remember must order the input variable as the order shown in function notation f(a, b, c)
Input Variable Minterms
a b c Terms
0 1 0 a’bc’ m2
1 1 0 abc’ m6
0 1 1 a’bc m3
1 1 1 abc m7
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SOP to Truth Table f(a,b,c) = ∑m(2, 3, 6, 7)
Input m2a’bc’
m3a’bc
m6abc’
m7abc
F
000 0 0 0 0 0
001 0 0 0 0 0
010 1 0 0 0 1
011 0 1 0 0 1
100 0 0 0 0 0
101 0 0 0 0 0
110 0 0 1 0 1
111 0 0 0 1 1
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More concise notation of canonical forms (POS) f(a,b,c) = (a+b+c)(a+b+c’)(a’+b+c)(a’+b+c’)
f(a,b,c) = M0 + M1 + M4 + M5
f(a,b,c) = ∏M(0, 1, 4, 5) Remember must order the input variable as the order shown in function notation f(a, b, c)
Input Variable Maxterms
a b C Terms
0 0 0 a+b+c M0
0 0 1 a+b+c’ M1
1 0 0 a’+b+c M4
1 0 1 a’+b+c’ M5
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POS to truth table f(a,b,c) = ∏M(0, 1, 4, 5)
Note ∏M(0, 1, 4, 5) = ∑m(2, 3, 6, 7)
Input M0a+b+c
M1a+b+c’
M4a’+b+c
M5a’+b+c’
F
000 0 1 1 1 0
001 1 0 1 1 0
010 1 1 1 1 1
011 1 1 1 1 1
100 1 1 0 1 0
101 1 1 1 0 0
110 1 1 1 1 1
111 1 1 1 1 1
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Exercise Find the minterms and maxterms
Input variablesW X
a b c
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1
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Exercise Find the minterms (∑) and maxterms (∏) f(a,b,c) = ab + ac’ + a’c f(p,q,s) = p(q’ + s)
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Exercise Write the SOP f(x,y,z) = ∑m(2,4,5) f(x,y,z) = ∑m(0,1,3,6,7)
Write POS f(x,y,z) = ∏M(2,4,5) f(x,y,z) = ∏M(0,1,3,6,7)
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Multiple‐Output Circuits Many circuits have more than one output Can give each a separate circuit, or can share gates Ex: F = ab + c’, G = ab + bc
ab
c
F
G
(a)
ab
c
F
G
(b)
Option 1: Separate circuits Option 2: Shared gates
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Multiple‐Output Example: BCD to 7‐Segment Converter
a = w’x’y’z’ + w’x’yz’ + w’x’yz + w’xy’z + w’xyz’ + w’xyz + wx’y’z’ + wx’y’z
abcdefg = 1111110 0110000 1101101
afb
d
gec
(b)(a)
b = w’x’y’z’ + w’x’y’z + w’x’yz’ + w’x’yz + w’xy’z’ + w’xyz + wx’y’z’ + wx’y’z
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Combinational Logic Design ProcessStep Description
Step 1 Capture the function
Create a truth table or equations, whichever is most natural for the given problem, to describe the desired behavior of the combinational logic.
Step 2 Convert to equations
This step is only necessary if you captured the function using a truth table instead of equations. Create an equation for each output by ORing all the minterms for that output. Simplify the equations if desired.
Step 3 Implementas a gate-based circuit
For each output, create a circuit corresponding to the output’s equation. (Sharing gates among multiple outputs is OK optionally.)
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Example: Three 1s Detector Problem: Detect three consecutive 1s in 8‐
bit input: abcdefgh 00011101 1 10101011 0
11110000 1
Step 1: Capture the function Truth table or equation?
Truth table too big: 2^8=256 rows Equation: create terms for each possible case of
three consecutive 1s
y = abc + bcd + cde + def + efg + fgh
Step 2: Convert to equation ‐‐ already done Step 3: Implement as a gate‐based circuit
bcd
def
fgh
abc
cde
efg
y
abc
d
e
f
g
h
aa
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Example: Number of 1s Count Problem: Output in binary on two outputs yz the number of 1s on three inputs
010 01 101 10 000 00
Step 1: Capture the function Truth table or equation? Truth table is straightforward
Step 2: Convert to equation y = a’bc + ab’c + abc’ + abc z = a’b’c + a’bc’ + ab’c’ + abc
Step 3: Implement as a gate‐based circuit
abc
abc
abc
abc
z
abc
abc
ab
y
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More Gates
NAND: Opposite of AND (“NOT AND”) NOR: Opposite of OR (“NOT OR”) XOR: Exactly 1 input is 1, for 2‐input XOR.
(For more inputs ‐‐ odd number of 1s) XNOR: Opposite of XOR (“NOT XOR”)
x0011
y0101
F1001
x0011
y0101
F0110
x0011
y0101
F1000
x0011
y0101
F1110
xy
xy FF
NORNAND XOR XNOR1
0
x y
Fx
y
1
0
x
x
y
y
F
NAND NOR
• NAND same as AND with power & ground switched
• Why? nMOS conducts 0s well, but not 1s (reasons beyond our scope) -- so NAND more efficient
• Likewise, NOR same as OR with power/ground switched
• AND in CMOS: NAND with NOT• OR in CMOS: NOR with NOT• So NAND/NOR more common
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More Gates: Example Uses
Aircraft lavatory sign example S = (abc)’
Detecting all 0s Use NOR
Detecting equality Use XNOR
Detecting odd # of 1s Use XOR Useful for generating “parity” bit common for detecting errors
S
Circuit
abc
000
1 a0b0
a1b1
a2b2
A=B
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Completeness of NAND Any Boolean function can be implemented using just NAND gates. Why? Need AND, OR, and NOT NOT: 1‐input NAND (or 2‐input NAND with inputs tied together)
AND: NAND followed by NOT OR: NAND preceded by NOTs
Likewise for NOR
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NAND‐NOR Logic Network DeMorgan’s theorem
x1
x2
x1
x2
x1
x2
x1
x2
2121 xxxx
2121 xxxx
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Examplef(a,b,c) =∑m(2,3,4,6,7) Find canonical SOP form Find minimum (simplified) SOP Draw logic circuit Covert to NAND only implementation
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Example f(a,b,c) =∑m(2,3,4,6,7) Canonical SOP f(a,b,c) = a’bc’ + a’bc + ab’c’ + abc’ + abc
Minimum SOP f(a,b,c) = a’bc’ + a’bc + ab’c’ + abc’ + abc = a’bc’ + a’bc + ab’c’ + abc’ + abc’ + abc = a’b(c’+c) + a(b’+b)c’ + ab(c’+c) = a’b + ac’ + ab = (a’+a)b + ac’ = b + ac’
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Example Logic Circuit
)( cabcabf
cabf
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Example
b
c
d
f
a
b
c
d
f
a
b
c
d
f
a
)()())((
))((
dcbadcbaf
dcbaf
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Introduction We now know how to build digital circuits
How can we build better circuits? Let’s consider two important design criteria
Delay – the time from inputs changing to new correct stable output Size – the number of transistors For quick estimation, assume
Every gate has delay of “1 gate‐delay” Every gate input requires 2 transistors Ignore inverters
22 transistors2 gate-delays
F1
wxy
wxy
F1 = wxy + wxy’
(a)
6 transistors1 gate-delay
F2
F2 = wx
(b)
wx
= wx(y+y’) = wx
Transforming F1 to F2 represents an optimization: Better in all
criteria of interest
(c)
20
15
10
5
F1
F2
1 2 3 4delay (gate-delays)
size
(tran
sist
ors)
Note: Slides with animation are denoted with a small red "a" near the animated items
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Introduction Tradeoff Improves some, but worsens other, criteria of interest
Transforming G1 to G2 represents a tradeoff: Some criteria better, others worse.
20 transistors2 gate-delays
18 transistors3 gate-delays
G1 G2
w wxyz
x
wyz
G1 = wx + wy + z G2 = w(x+y) + z
20
15
10
5
G1G2
1 2 3 4delay (gate-delays)
size
(tran
sist
ors)
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Introduction
We obviously prefer optimizations, but often must accept tradeoffs You can’t build a car that is the most comfortable, and has the best fuel efficiency, and is the fastest – you have to give up something to gain other things.
delaydelay
OptimizationsTradeoffs
All criteria of interestare improved (or at least kept the same)
Some criteria of interest are improved, while others are worsenedsi
ze
size
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Combinational Logic Optimization and Tradeoffs Two‐level size optimization using algebraic
methods Goal: circuit with only two levels (ORed AND
gates), with minimum transistors Though transistors getting cheaper (Moore’s
Law), they still cost something
Define problem algebraically Sum‐of‐products yields two levels
F = abc + abc’ is sum‐of‐products; G = w(xy + z) is not.
Transform sum‐of‐products equation to have fewest literals and terms Each literal and term translates to a gate input,
each of which translates to about 2 transistors (see Ch. 2)
Ignore inverters for simplicity
F = xyz + xyz’ + x’y’z’ + x’y’z
F = xy(z + z’) + x’y’(z + z’)
F = xy*1 + x’y’*1
F = xy + x’y’
F
xy
x’y’
m
n
4 literals + 2 terms = 6 gate inputs
6 gate inputs = 18 transistors
Note: Assuming 6-transistor 2-input AND/OR circuits;iNAND/NOR are so efficient.
Example
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Minimum Cost Without counting transistors we can use a minimum cost to be the total number of gates + the total number of inputs to all gates
The total number of gates = 3 The total number of inputs = 6 Minimum cost = 9
F
xy
x’y’
m
n
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Number of Possible Boolean Functions How many possible functions of 2 variables?
22 rows in truth table, 2 choices for each 2(22) = 24 = 16 possible functions
N variables 2N rows 2(2N) possible functions
a0011
b0101
0 or 1 2 choices0 or 1 2 choices0 or 1 2 choices0 or 1 2 choices
F
24 = 16possible functions
f00000
b0101
a0011
f10001
f20010
f30011
f40100
f50101
f60110
f70111
f81000
f91001
f101010
f111011
f121100
f131101
f141110
f151111
0
a A
ND
b a b
a X
OR
b
a O
R b
a N
OR
b
a X
NO
R b b’ a’
a N
AN
D b 1
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Additional ConsiderationsNon‐Ideal Gate Behavior ‐‐ Delay
Real gates have some delay Outputs don’t change immediately after inputs change