Dynamic Logic Circuits

9 9 -- 11

CMOS Digital Integrated Circuits

Chapter 9 Dynamic Logic Circuits

馮武雄教授長庚大學電子系

9 9 -- 22

Dynamic Logic Circuits

1. Pass transistor circuits2. Voltage bootstrapping3. Synchronous dynamic circuit techniques4. Dynamic CMOS circuit techniques5. High-performance dynamic CMOS

circuits

9 9 -- 33

Static v.s. DynamicStatic Logic Gates

• Valid logic levels are steady-state operating points• Outputs are generated in response to input voltage levels after

a certain time delay, and it can preserve its output levels as long as there is power.

• All gate output nodes have a conducting path to VDD or GND, except when input changes are occurring.

Dynamic Logic Gates• The operation depends on temporary storage of charge in

parasitic node capacitances.• The stored charge does not remain indefinitely, so must be

updated or refreshed. This requires establishment of an update or recharge path to the capacitance frequently enough to preserve valid voltage levels.

9.1 Introduction

9 9 -- 44

Static v.s. Dynamic (Continued)Advantages of Dynamic Logic Gates

• Allow implementation of simple sequential circuits with memory functions.

• Use of common clock signals throughout the system enables the synchronization of various circuit blocks.

• Implementation of complex circuits requires a smaller silicon area than static circuits.

• Often consumes less dynamic power than static designs, due to smaller parasitic capacitances.

9 9 -- 55

Pass-Transistor Latch: Circuit and Operation

Operation• CK = H, D=H or L : CX is charged up or down through MP,

and X becomes H or L (depends on D input) since MP is on ⇒D and X are connected.

• CK = L: X is unchanged since MP is off and CX is isolated from D, and the charge is stored on capacitances CX.

• For X = H, Q = L and Q = H• For X = L, Q = H and Q = L

Cost: 3 to 5 devices (very low)

MP

CKCx

D VxML

MD

Q Q

Soft note

X

9.2 Basic Principles of Pass Transistor Circuits

9 9 -- 66

Pass-Transistor Latch: Soft Node Concept• During CK = 1: Let D = 1, i.e. VD = VOH = VDD MP is

conducting and charges CX to a “weak 1” (VX = VDD – VTD) ⇒Q = L (VQ<VTD) and Q = H(VQ=VDD).

• During CK = 0: Logic-level VX is preserved through charge storage on CX. However, VX starts to drop due to leakage.

• What value does VX have to deteriorate to no longer like a stored ?Example (see p359~359, Kang and Leblebici): For an inverter with VDD = 5V, VT,n = 0.8V , VOL = 2.9V and VIH = 2.9V, initial VX =4.2 V. But due to leakage currents, this will decline over time. When it declines below VIH(2.9V), then a logic 0 out of the inverter can no longer guaranteed.Thus, to avoid an erroneous output, the charge stored in CX

must be restored or refreshed to its original level before VX

declines below 2.9 V.

9 9 -- 77

Basic Principles of Pass Transistor CircuitsLogic “1” Transfer

Logic “1” Transfer: VX(t=0)=0V, Vin=VOH=VDD, CK=0 →VDD

• VGS = VDD - VX, VDS = VDD - VX = VGS. • Therefore, VDS> VGS – VT,MP⇒ MP is in saturation.

• Note that the VT,MP is subject to substrate bias effect and therefore, depends on the voltage level VX. We will neglect the substrate bias effect for simplicity.

MP

CKCx

Vx

Soft note

X MP

CKCx

Vin=VDDVx

X

IDVin ⇒ D S

( )VVVkdt

dVC MPTXDDnX

X ,2

2−−=

Fig. 9.2Fig. 9.1

9 9 -- 88

Basic Principles of Pass Transistor CircuitsLogic “1” Transfer (Cont.)

• Integrating the above equation with t from 0 → t and VX

from 0 → VX, we have

• Therefore,

• and,

( )V

MPTXDDn

X

V

MPTXDD

X

n

Xt

X

X

VVVkC

VVVdV

kCdt

0,

0 ,2

0

12

2

−−=

−−= ∫∫

⎟⎟⎠

⎞⎜⎜⎝

⎛−

−−−

=VVVVVk

CtMPTDDMPTXDDn

X

,,

112

( )( )

( ) tC

VVk

tC

VVk

VVtV

X

MPTDDn

X

MPTDDn

MPTDDX

21

2)(,

,

, −+

−

−=

9 9 -- 99


• VX rises from 0V and approaches a limit value Vmax = VX(t)|t=∞= VDD-VT,MP, but it can not exceed this value, since the pass transistor will turn off at this point (VGS=VT,MP). Therefore, it transfers a “weak logic 1”.

• The actual Vmax by taking the body effect into account is,

• and tcharge = time to VX = 0.9Vmax,

• Body Effect: Reduce VX, and Increase tcharge

⎟⎟⎠

⎞⎜⎜⎝

⎛−

−−−

=VVVVVk

CMPTDDMPTmaxDDn

Xcharget

,,

19.0

12

( )φφγ 22,0 FmaxFMPTDDmax VVVV −+−−=

VX

VmaxVmax=VDD-VT,MP

t0Fig. 9.3

9 9 -- 1010

9 9 -- 1111

9 9 -- 1212

Basic Principles of Pass Transistor Circuits: Logic “0” Transfer

Logic “0” Transfer: VX(t=0)=Vmax= VDD – VT,MP, Vin=VOL=0V, CK= 0 → VDD

•VGS = VDD, VDS = Vmax = VDD – VT,MP. •Therefore, VDS≤VGS – VT,MP⇒ MP is in linear region.

•Note that the VSB=0. Hence, there is no body effect for MP(VT,MP= VT0,MP). But the initial condition VX(t=0)=VDD –VT,MP contains the threshold voltage with body effect. To simplify the expressions, we will use VT,MP in the following.

MP

CKCx

Vx

Soft note

X MP

CKCx

Vin=0 Vx

X

IDVin ⇒ DS

( )[ ]VVVVkdt

dVC XXMPTDDnX

X2

,22

−−=−

Fig. 9.6

9 9 -- 1313


•Integrating the above equation with t from 0 → t and VX from VT,MP → VX, we have

•Therefore,

•and,

( )[ ]

( )( ) V

VVX

XMPTDD

MPTDDn

X

V

VV XXMPTDD

X

n

Xt

X

MPTDD

X

MPTDD

VVVV

VVkC

VVVVdV

kCdt

,

,

,

,

2,0

2ln

22

−

−

⎥⎦

⎤⎢⎣

⎡⎟⎠

⎞⎜⎝

⎛ −−−

=

−−= ∫∫

( )( )

⎟⎠

⎞⎜⎝

⎛ −−−

=V

VVVVVk

CtX

XMPTDD

MPTDDn

X ,

,

2ln

( )( )e

VVtV CVVtkMPTDD

XXMPTDDn+

−=

−12)(

/,

,

9 9 -- 1414


• VX drops from Vmax = VDD-VT,MP, to 0V. Hence, unlike the charge-up case, it transfers a “strong logic 0”.•τfall = time of VX drops from 0.9Vmax to 0.1Vmax,

• where,

( )[ ]

( )VVkC2.74

VVkCtt

MPTDDn

X

MPTDDn

X

fall

,

,

%10%90

)22.1ln()19ln(

−=

−−

=

−=τ

( )( )( )

( )

( ) ( )

( ) ⎟⎠⎞

⎜⎝⎛

−=

−=

⎟⎟⎠

⎞⎜⎜⎝

⎛−−−

−=

0.11.9

VVkCt

1.22VVk

CVV0.9

VV0.92VVk

Ct

MPTDDn

X

MPTDDn

X

MPTDD

MPTDD

MPTDDn

X

ln

ln

ln

,%10

,

,

,

,%90

VX

VmaxVmax=VDD-VT,MP

t0

Fig. 9.7

9 9 -- 1515

Basic Principles of Pass Transistor CircuitsCharge Storage and Charge Leakage

• At t = 0, CK=0, VX= Vmax, Vin =0. The charge stored in CX

will gradually leak away, primarily due to the leakage currents associated with the pass transistor. The gate current of the inverter driver transistor is negligible.

n+ n+

VCK=0

Vin=0Ileakage VX

CX

Ireverse

Isubthreshold

p-type Si

MP

CK=0Cx

VxVin =0Ileakage Igate=0

Fig. 9.9

Fig. 9.8

9 9 -- 1616

Basic Principles of Pass Transistor CircuitsCharge Storage and Charge Leakage (Cont.)

• Isubthreshold is the subthreshold current for the pass transistor with CK=0.• Ireverse is the reverse current for the source/drain pn junction at node X• Cj (VX) : due to the reverse biased drain-substrate junction, a function of

VX， Cin: due to oxide-related parasitics, can be considered constants.

n+ n+

VCK=0Vin=0

Ileakage VX

CX

Ireverse

Isubthreshold

p-type Si

Cin

VxIleakage

Cj(VX)

Ileakage= Isubthreshold + Ireverse

Ireverse

Cin= Cgb + Cpoly + Cmetal

CX= Cin + Cj

Isubthreshold

Drain-substrate pn-junction Fig. 9.10

9 9 -- 1717


• The total charge stored in the soft node can be expressed as,Q = Qj (VX) + Qin where Qin = Cin•VX

• The total leakage current can be expressed as the time derivative of the total soft-node charge Q

Cin

VxIleakage

Cj

Ileakage= Isubthreshold + Ireverse

Ireverse

Cin= Cgb + Cpoly + Cmetal

CX= Cin + Cj

Isubthreshold

Drain-substrate pn-junction

dtdVCdt

dVdV

VdQdt

dQdt

VdQdt

dQI

Xin

X

X

Xj

inXj

leakage

+=

+=

=

)(

)(

9 9 -- 1818


• Where

• Therefore,

• We have to solve the above differential equation to estimate the actual charge leakage time from the soft node.

⎟⎠

⎞⎜⎝

⎛=

nNN

qkT

i

ASWDSW 20 lnφ⎟

⎠

⎞⎜⎝

⎛=

nNN

qkT

i

AD20 lnφ

φφ SW

X

SWj

X

j

XjX

Xj

VAC

VAC

VCdV

VdQ

0

0

0

0

11

)()(

++

+=

=

dtdVC

VPC

VAC

I Xin

SW

X

SWj

X

jleakage

⎟⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜⎜

⎝

⎛

++

++

=

φφ 0

0

0

0

11

9 9 -- 1919


A quick estimate of the worst-case leakage behavior• Assume that the minimum combined soft-node

capacitance isCX,min = Cgb + Cpoly + Cmental + Cdb,min

Cdb,min is the minimum junction capacitance, obtained when VX=Vmax

• The worst-case holding time (thold) is the shortest time for VX to drop from its initial logic-high value to the logic threshold voltage due to leakage.

thold = ΔQcritical,min/Ileakage,max

• whereΔQcritical,min =CX,min (Vmax-VDD/2)

Vth

9 9 -- 2020


Example 9.2: Consider the soft-node structure shown below, which consists of the drain (or source, depending on current direction) terminal of the pass transistor, connected to the polysilicon gate of an nMOS driver transistor via a metal interconnect.

Question: is to estimate thold if VDD=5V and the soft-node is initially charged to Vmax.

MP

Cx

Vx

CK

M1

2

31

41 1

3

6 65

52

2 4

soft node

M1MP

diffusion metal polysiliconCK

9 9 -- 2121


• Material parameters:VTO = 0.8V COX = 0.065 fF/μm2

γ = 0.4V1/2 C’metal = 0.036 fF/ μm2

|2φF| = 0.6V C’poly = 0.055 fF/ μm2

φ0 = 0.88V Cj0 = 0.095 fF/ μm2

φ0SW = 0.95V Cj0SW = 0.2 fF/μmIleakage,max = 0.85 pA

Soft-node Capacitance Calculation• Oxide-related (constant) parasitic capacitances

» Cgb = COX·W·Lmask = 0.065 fF/μm2· (4 μm×2 μm) = 0.52 fF» Cmetal = C’metal·W·Lmetal = 0.036 fF/μm2· (5 μm×5 μm) = 0.90 fF» Cploy = C’poly·W·Lpoly = 0.055 fF/μm2· (36+6+2 μm2) = 2.42 fF

2

31

41 1

3

6 65

52

2 4M1MP

diffusion metalpolysiliconCK

9 9 -- 2222


•Parasitic junction capacitanceBy zero-bias unit capacitance values in the previous slide, we have» Cbottom = Abottom·Cj0 = 0.095 fF/μm2· (36 μm2 + 12 μm2 ) = 4.56 fF» Csidewall = Cj0SW·Psidewall = 0.2 fF/μm2· (30 μm) = 6.00 fFTherefore» Cdb,max = Cbottom + Csidewall = 4.56 fF + 6.00 fF = 10.56 fFThe minimum drain junction capacitance is achieved as the

junction is biased with Vmax. We need to find Vmax to determine Cdb,min

» Vmax = 5.0 - 8.0 - 0.4 ( 0.6+ Vmax - 0.6 )⇒ Vmax = 3.68 V

Therefore,

fF

VC

VCC

SW

maxX

sidewall

maxX

bottommindb

71.4

95.068.31

0.6

88.068.31

56.4

110

,

0

,,

=+

++

=

++

+=

φφ

9 9 -- 2323


•Combining the Oxide-related (constant) parasitic capacitances with the parasitic junction capacitance, CX,min

can be got asCX,min = Cgb + Cpoly + Cmental + Cdb,min

= 0.52 + 2.42 + 0.90 +4.71 = 8.55 fF•The amount of the critical charge drop is

ΔQcritical = CX,min(VX,min-VDD/2)=8.55 (3.68-2.5)=10.09 fC

•Finally, thold = Δ Qcritical /Ileakage,max=11.87ms

•The worst-case hold time for this structure is relatively long, even with a very small soft-node capacitance of 8.55fF. It means that the logic gate can be preserved in a soft node for a long time period when the leakage current is small.

9 9 -- 2424

9.3 Voltage Bootstrapping• The Voltage bootstrapping is a technique to overcome

the threshold voltage drops of the output voltage levelsin pass transistor gates or enhancement-load inverters and logic gates.

• Consider the following circuit with VX≤VDD ⇒ M2 is in saturation. If Vin is low, the maximum output voltage is limited as

Vout(max) = VX – VT2(Vout)

M1 Cout

Vx

Vin

M2

VDD

Vout

Fig. 9.11

9 9 -- 2525

Voltage Bootstrapping (Cont.)• To overcome the voltage drop, the voltage VX must be increased. This

can be achieved by adding a third transistor M3 into the circuit.» CS and Cboot represent the capacitances which dynamically couple

VX to the ground and to the output.» The goal of the above circuit is to provide a high enough voltage VX

to let Vout go to VDD instead of VDD-VT2(Vout).

• Initially, let Vin=H⇒ M1 and M2 are on, and Vout=L.• Now Vin goes to L ⇒ M1 turns off, and Vout starts to rise. This change

will be coupled to VX through the bootstrap capacitor, Cboot.

M1 CoutVin

M2

VDD

Vout

Vx

M3

CbootCS

Fig. 9.12

9 9 -- 2626

Voltage Bootstrapping (Cont.)

• Let iCboot be the transient current through Cboot during the charge-up event, and let iCS be the current through CS. Assume iCS ≈ iCboot, we have

iCS ≈ iCboot⇔ CS·dVX/dt ≈ Cboot·d(Vout-VX)/dt⇒ (CS+Cboot)·dVX/dt ≈ Cboot·dVout/dt⇒ dVX/dt ≈ Cboot /(CS+Cboot) ·dVout/dt

• This expression can be integrated to give VX such that Vout will rise to VDD.

• If Cboot >> CS, then for Vout rising to VDD, VX(max) ≈ 2VDD – VT3 – VOL > VDD – VT2.

for realistic values of the voltages. Thus, it is feasible to use the circuit to obtain Vout =VDD.

( ) ( )VVCC

CVVV

dVCC

CdV

OLDDbootS

bootTDDX

V

Vout

bootS

bootV

VVX

DD

OL

X

TDD

−+

+−=⇒

+= ∫∫ −

3 .

3

9 9 -- 2727

Voltage Bootstrapping (Cont.)

• To overcome the threshold voltage drop at Vout, the minimum VX is

VX(min) = VDD + VT2|Vout = VDD

= [VDD-VT3(VX)]+Cboot /(CS+Cboot) ·(VDD-VOL)• Therefore, the required capacitance ratio Cboot /(CS+Cboot) is

• CS is the sum of the parasitic source-to-substrate capacitance of M3 and the gate-to-substrate capacitance of M2.

XDDout

XDDout

XDDout

VTVVTOLDD

VTVVT

S

boot

OLDD

VTVVT

bootS

boot

VVVV

VV

CC

VV

VV

CCC

32

32

32

.−−−

+=

−

+=

+

=

=

=

9 9 -- 2828

Voltage Bootstrapping (Cont.)• Cboot can be specifically constructed to control its value by

using a transistor with the source and drain connected together at Vout and the gate attached to VX. Since its drain and source tied together, it simply acts as an MOS capacitor between VX and Vout.

• See Kang and Leblebici at pp. 373 for a SPICE example.

M1Vin

M2

VDD

Vx

M3

Vout

Cboot

Fig. 9.13

9 9 -- 2929

9.4 Synchronous Dynamic Circuit Techniques –Dynamic Pass Transistor Circuits

• The multi-stage synchronous circuit is shown below. The circuit consists of cascaded combinational logic stages interconnected through nMOS pass transistors. Its operation depends on temporary charge storage in the parasitic input capacitances.

• Logic levels are stored on input capacitances during the inactive clock phase.

AB

φ1φ1 φ2C D

F1

F2

Comb.Logic

1

Comb.Logic

2

Comb.Logic

3

φ1

phase1 phase2

t

tφ2

φ1,φ2 non-overlapping clocks

Fig. 9.14

Fig. 9.15

9 9 -- 3030

Dynamic Pass Transistor CircuitsTwo-Phase Clock Dynamic Shift Register

Depletion-Load Dynamic Shift Register• The max clock frequency is determined by signal

propagation delay through one inverter stage.• One half-period of the clock signal must be long enough to

allow Cin to charge up or down, and Cout to charge to the new value.

• The logic-high input value is one VT0 lower than VDD.VDD

φ1 φ2 φ1

Vin

Vout

Cin1 Cin2 Cin3Cout1 Cout2

VDD VDD

Cout3

Fig. 9.16

9 9 -- 3131

9 9 -- 3232

9 9 -- 3333

Dynamic Pass Transistor CircuitsEnhancement-Load Dynamic Shift Register

Enhancement-Load Dynamic Shift Register 1• Instead of biasing load transistors with a constant gate voltage, a

clock signal is applied to the gate of the load transistor ⇒ power dissipation and silicon area are reduced.

• The power supply current flows only when the load devices are activated by the clock signal, the power consumption is lower than the depletion-load nMOS logic.

VDDφ1 φ2 φ1

Vin

Vout


VDD VDD

Cout3

φ2

Fig. 9.19

9 9 -- 3434

Enhancement-Load Dynamic Shift Register 1 (Cont.)General Structure

BC

φ1

VDD

nMOSLogic

Stage 1

nMOSLogic

Stage 2

A

D

VDD

φ2 φ1

Z

General Circuit Structure of Ratioed Synchronous Dynamic Circuit

Fig. 9.20

9 9 -- 3535

9 9 -- 3636

Enhancement-Load Dynamic Shift Register 1 (Cont.) VDD

φ1

φ2 φ1

Vin

Vout3


VDD VDD

Cout3

φ2Vout1 Vout2

Vout2⇒VOLVDD

φ1

φ2 φ1

VinCin1 Cin2 Cin3Cout1 Cout2

VDD VDD

Cout3

φ2

φ1=H

φ2=H

Vout1 Vout2 Vout3

Vout1⇒VOL Vout3⇒VOL

• VOL → kdriver/kload ⇒Ratioed Dynamic Logic.• Cout1, Cin2 & Cout2, Cin3 interact ⇒ Charge Sharing

9 9 -- 3737

Enhancement-Load Dynamic Shift Register 2

Enhancement-Load Dynamic Shift Register 2• The input pass transistor and the load transistor are driven by

the same clock phase.• The valid low-output voltage level VOL=0V can be achieved

regardless of the driver-to-load ratio, this circuit is a ratiolessdynamic logic.

VDDφ1 φ2 φ1

Vin

Vout


VDD VDD

Cout3

Fig. 9.21

9 9 -- 3838

Enhancement-Load Dynamic Shift Register 2(Cont.)General Structure

General Circuit Structure of Ratioless Synchronous Dynamic Circuit

BC

φ1

VDD

nMOSLogic

Stage 1

nMOSLogic

Stage 2

A

D

VDD

φ2

Z

Fig. 9.22

9 9 -- 3939

Enhancement-Load Dynamic Shift Register 2 (Cont.)

• VOL → 0V ⇒Ratioless Dynamic Logic.

VDD

φ1φ2 φ1

Vin

Vout3


VDD VDD

Cout3

Vout1 Vout2

Vout2⇒ 0V

φ1=H

Vout1⇒VOL Vout3⇒VOH

VOH ⇒0VOH

VDDφ1 φ2 φ1

VinCin1 Cin2 Cin3Cout1 Cout2

VDD VDD

Cout3

φ2=H

Vout1 Vout2 Vout3

Vout1⇒0V Vout2⇒VOH

VOH⇒0VOH 0

Vout3=VOH

9 9 -- 4040

Enhancement-Load Dynamic Shift Register 2 (Cont.)

• Cini << Couti-1 for i=2,3 ⇒ Minimum Charge Sharing

VDD

φ1φ2 φ1

Vin

Vout3


VDD VDD

Cout3

Vout1 Vout2

Vout2= VOH

φ1=H

Vout1=0V Vout3=?

0V 0VOH

Charge Sharing

VOH

9 9 -- 4141

Enhancement-Load Dynamic Shift Register 2 (Cont.)Charge Sharing

• φ2 = 0: Qout2 = Cout2Vb and Qin3 = Cin3Va

• φ2 = 1: Qtotal = Cout2Vb + Cin3Va and Ctotal = Cout2 + Cin3

The resulting voltage across Ctotal is VR = Qtotal / Ctotal = (Cout2Vb + Cin3Va )/ (Cout2 + Cin3)

• If Vb = VOH and Va << Vb ⇒ VR ≈ Cout2VOH /(Cout2 + Cin3)VR ≈ VOH if Cin3 << Cout2

φ2=1

Cin3Cout2

Va

Charge SharingCin1

Vi1=0

φ2=1

Cin2Cout1

Vb=VOL →0 Va

Cin1

Vin1=1

Vb=VOH

9 9 -- 4242

9.5 Dynamic CMOS Circuit TechniquesCMOS Transmission Gate Logic

• Each transmission gate is controlled by the clock signal and itscomplement. Therefore, the two-phase clocking need four clock signals.

• As in the nMOS structures, the CMOS dynamic circuit relies on charge storage in parasitic input capacitances during the inactive clock cycles.

D

φ1 φ2

A

B

CStage 1 Stage 2

φ1

φ1

φ1

φ2

F1

Fig. 9.23

9 9 -- 4343

Dynamic CMOS Transmission Gate LogicShift Register

• The basic building block of the shift register consists of a CMOS inverter, which is driven by a TG.

• CK=1⇒Vin is transferred onto the parasitic input capacitance CX.

• The low on-resistance of TG results in»A smaller transfer time compared to nMOS-only switches.»No threshold voltage drop across TG

CK

VDD

VoutVX

CX CyCK

Vin

soft node

Fig. 9.24

9 9 -- 4444

Dynamic CMOS Transmission Gate LogicShift Register (Cont.)

• The single-phase CMOS shift register is built by» Cascading identical inverter units» Driving each stage alternately with the CK and CK.

• Ideally: The odd-numbered stages are on as CK=1, while the even-numbered stages are off ⇒ the cascaded inverter stages are alternately isolated.

• Practically:» The CK and CK are not a truly nonoverlapping signal pair,

since their waveforms have finite rise and fall times.» One of the signals is generated by inverting the other ⇒ the

clock skew is unavoidable.» True two-phase clocking is preferred over single-phase

clocking.CK

CK

V1

CK

CK

CK

CK

V2 V3 V4

Fig. 9.225

9 9 -- 4545

Dynamic CMOS Precharge-Evaluate LogicReduced Transistor Count

•φ=0 ⇒ Mp on and Me off⇒ Cprecharges to VDD (output is not available during precharge)

•φ =1 ⇒ Mp off and Me on ⇒C selectively discharges to 0 (output is only available after discharge is complete)

φ

VDD

nMOSLogicinputs

C

Vout

Me

Mp

Internal capacitance

φ

t

t

Voutprecharge precharge

evaluate

9 9 -- 4646

Dynamic CMOS Precharge-Evaluate LogicAn Example

φ

VDD

Vout

Me

Mp

A1

A2

A3

B1

B2

Z is high when φ=0

Z=(A1 A2A3 +B1B2)

Fig. 9.26

9 9 -- 4747

Dynamic CMOS Precharge-Evaluate LogicAdvantages/Disadvantages

Advantages• Need only N+2 transistors to implement a N-input gate.• Low static power dissipation• No DC current paths to place constraints on device sizing• Input capacitance is same as pseudo nMOS gate.• Pull-up time is improved by active switch to VDD.

Disadvantages• The available time of output is less than 50 % of the time.• Pull-down time is degraded due to series active switch to 0.• Logic output value can be degraded due to charge sharing with other

gate capacitances connected to the output.• Minimum clock rate determined by leakage on C.• Maximum clock rate determined by circuit delays.• Input can only change during the precharge phase. Inputs must be

stable during evaluation; otherwise an incorrect value on an input could erroneously discharge the output node. (single phase P-E logic gates can not be cascaded)

• Outputs must be stored during precharge, if they are required during the next evaluate phase.

9 9 -- 4848

Dynamic CMOS Precharge-Evaluate LogicCascading Problem

• Evaluate:» Me1, Me2 ⇒ ON» Mp1, Me2 ⇒ OFF

• Problem: All stages must evaluate simultaneously one clock does not permit pipelining of stages.

φ

VDD

nMOSLogic

Vout1

1st stage

1

Vout2

VDD

2nd Vout1 does not switch fromt

t

φ

Vout

t

Voutcorrect state

erroneous state

precharge evaluate

“1” to “0” fast enoughinputs

Me1Me2

Mp1 Mp2

9 9 -- 4949

9.6 High Performance Dynamic CMOS CircuitsDomino CMOS Logic

φ

VDD

nMOSLogic

Vout

VDD

inputs

X

φ precharge evaluate1

t

Static inverter serves to buffer the logic part of the circuit from its output load

• φ=0 » X precharges to VDD, and Vout

= 0.• φ=1

» X remains high, and Vout

remains low.» X discharges to 0, and Vout

changes from 0 to 1. Fig. 9.27

9 9 -- 5050

9 9 -- 5151

9 9 -- 5252

9 9 -- 5353

9 9 -- 5454

Domino CMOS Logic

φ

VDD

nMOSLogicinputs

VDD

nMOSLogic

X1

VDD

nMOSLogic

X2 X3

t

tX1

t

precharge

evaluate

t

X2

X3

φ evaluate

teval

Max number gates limited: total propagation delay < teval

9 9 -- 5555

Domino CMOS Logic (Cont.)

•The problem in cascading conventional dynamic CMOS occurs when one or more inputs make a 1 to 0 transition during evaluation.•Domino circuits can fix the above problem

»During the evaluation, each buffer output can make at most one transition (from 0 to 1), and thus each input of all subsequent logic stages can also make at most one (0 to 1) transition.

X3

φ

VDD

nMOSLogicinputs

VDD

nMOSLogic

X1

VDD

nMOSLogic

X2

9 9 -- 5656

Domino CMOS Logic The Limitations

•The static CMOS and domino gates can be used together, see Fig. 9.31. in Kang and Leblebici. The limitation: the number of inverting static logic stages in cascade must beeven, to let the inputs of next domino stage can have only 0 to 1 transitions during the evaluation.•Can implement only non-inverting logic•Due to precharge use, can suffer from charge sharingduring the evaluation which may cause erroneous outputs.

»The problem will be described in the next slide, and several solutions will be presented later.

9 9 -- 5757

Domino CMOS LogicCharge Sharing

• Assume that all inputs are low initially, and the voltage acrossC2=0V

• During the precharge, C1 is charged to VDD

• If transistor N switches from 0 to 1 during the evaluation phase, the charge initially stored in C1 will be shared by C2. Therefore, the value of VX will reduced.

φ

VDD

Vout

VDD

VX

C1

C2VX = VDDC1/(C1+C2)

Keep C2 << C1

N

0V(initially)

Fig. 9.32

9 9 -- 5858

Domino CMOS LogicReduce Charge Sharing Degradation of VX

φ

VDD

nMOSLogicinputs

VoutVX

Push VX to VDD unless there is a strong pull-down path between Vout and ground

weak pull-up pMOS

Fig. 9.33

9 9 -- 5959

Domino CMOS LogicReduce Charge Sharing Degradation of VX (Cont.)

Use separate pMOS transistors to precharge all intermediate nodes in nMOS pull-down tree which have a large parasitic capacitance.

Effectively eliminate all charge sharing problems during evaluation

Allow implementation of multiple-output domino structures.

Can cause additional delay since the nMOS tree need to drain a larger charge to pull down VX

VDD

φ

nMOSLogic

Vout1

VX2

VX1

nMOSLogic

Vout2

C1

C2

Another Way: Use a smaller threshold voltage⇒ the final stage output is not affected by lowering of VX ⇒trade off the pull-up speed (weaker pMOStransistor)

Fig. 9.34

9 9 -- 6060

Domino CMOS LogicAn Example of Using Separate pMOS Transistor

VDD

φ

VDD

Vout

VDD

VX1

C1

C2

VA

VB

VX2

• Let C1 = C2 = 0.05pF. VX1 = 0, and VX2 = 0 at t=0

• Without this extra pMOStransistor

» Precharge: VX1 ≠VX2

» Evaluation: VX1 = VDDC1/(C1+C2) = VDD/2

• With this extra pMOS transistor » Presharge: VX1 = VX2

» Evaluation: VX1 = VDD

• See pp.392~393 for the HSPICE simulation result

• Note that there is a speed penaltyfor adding this extra pMOSprecharge transistor.

9 9 -- 6161

Domino CMOS LogicAn Example of Multiple-Output Domino Circuits

C1=G1+P1C0

C2=G2+P2G1+P2P1C0

C3=G3+P3G2+P3P2G1+P3P2P1C0

C4=G4+P4G3+P4P3G2+P4P3P2G1+P4P3P2P1C0

φ

P1

C0

P2

P3

P4

G2

G3

G1

G4

C4

C3

C2

C1

VDD

Gi = Ai · Bi

Pi = Ai ⊕ Bi

Reduce transistor count

Fig. 9.35

9 9 -- 6262

FET Scaling in Domino CMOS GatesThe transient performance can be improved by adjusting the nMOS transistor sizes in the pull-down path to reduce the discharge time.

φ

VDD

Vout

Me

Mp

A

B

C

D

CL

CLC1C0

R0 R10 1

ABCD

Fig. 9.36

9 9 -- 6363

The nMOS Scaling in Domino CMOS Gates

V1=V0=VDD⇒VDDe-1 after time T1T1 =R0(C0+C1+CL)+R1(C1+CL)

Let the last nMOS is increased by a fraction of ∆k thenC1⇒ C1(1+∆k); R1⇒ R1/(1+∆k)

T1 =R0(C0+C1+CL)+R1(C1+CL)+(C1-R1CL/R0)∆kIf

CL<(R0/R1)C1

T1 decreases by decreasing the size of the last nMOS. R0/R1 is the number of series-connected nMOS minus one, times a factor γ that takes the many effects that makes a real nMOS different from a linear resistor, into account. Using the approximation γ=1/2, we conclude

If CL<C1(N-1)/2 is satisfied, the overall delay can be reduced by decreasing the size of last nMOS.

The above result can be iteratively applied to the other transistors, which leads to graded sizing of all nMOS devices.

CLC1C0

R0 R10 1

9 9 -- 6464

NORA CMOS Logic (NP-Domino Logic)

•Advantages»An Inverter is not required at the output of stages»Allow pipelined system architecture

•Disadvantages: Also suffer from charge sharing and leakage

VDD VDD VDD

φ

nMOSLogic

pMOSLogic

nMOSLogic

φ φ

to nMOS stage to pMOS stagenMOS stageprechargepMOS stagepre-discharge

all stagesevaluate nMOS stageprechargepMOS stagepre-discharge

all stagesevaluateφ

Fig. 9.37

9 9 -- 6565

NORA CMOS Logic (NP-Domino Logic)Examples

VDD VDD VDD

φ φ φ

• φ=L: nMOS precharges to H, and pMOS pre-discharges to L.

• φ=L→H: All cascaded nMOS and pMOS logic stages evaluate one after the other.

Fig. 9.38

9 9 -- 6666

NORA CMOS Logic (NP-Domino Logic)Examples (Cont.)

• Pipelined System Architecture: See Fig. 9.39 – Use of CMOS2 latches (three state latches storing on logic inputs.)

• Zipper Logic: See Fig. 9.40 – Identical to NORA except for weird clock signals that keep precharge devices weakly on to handle charge leakage and charge sharing

9 9 -- 6767

9 9 -- 6868

9 9 -- 6969

Pipelined True Single-Phase Clock (TSPC) Dynamic CMOS

• φ=L: nMOS blocks precharge to VDD

pMOS blocks evaluate by selective pull-up to VDD

• φ=H: pMOS blocks pre-discharge to VDD

nMOS blocks evaluate by selective pull-down to 0V• φ is not used, no clock skew problem can arise.• Provide similar performance to NORA structure

Using tristate inverters between stages decouples the stages and enables pipelined operation

VDD VDD

φ

nMOSLogic

pMOSLogic

φ

VDD

φ

φ

VDD

N-block P-block

to next N-block

Fig. 9.41

9 9 -- 7070

TSPC-Based Rising Edge-triggered D-type Flip-Flop

• Need only 11 transistors. • Static Edge Triggered D Flip-flop (see Fig. 8.30) need 16

transistors.Common Advantages of dynamic Logic Styles

• Smaller area than fully static gates.• higher speed: smaller parasitic capacitances.• Glitch free operation if design carefully

VDD

φ

VDD

φ

VDD

Q

VDD

φD

Fig. 9.42

9 9 -- 7171

9 9 -- 7272

9 9 -- 7373

Summary •Full complementary static logic is best option in the majority of CMOS circuits.

»Noise-immunity is not sensitive to kn/kp

»Does not involve precharge of nodes»Dissipate no DC power»Layout can be automated»Large fan-in gates lead to complex circuit structures (2N transistors)

»Larger parasitics»Slower and higher dynamic power dissipation than alternatives

»No clock

9 9 -- 7474

Summary (Cont.)

•Pseudo-nMOS static logic finds widest utility in large fan-in NOR gates.

» Require only N+1 transistors for N fan-in» Smaller parasitics» Faster and lower dynamic power dissipation

than full CMOS» Noise immunity sensitive to kn/kp

» Dissipate DC power when pulled down» Not well suited for automated layout» No clock

9 9 -- 7575

Summary (Cont.)

• CMOS domino logic should be used for low-power, high speed applications

» Require only N+k transistors for N fan-in, size advantages of pseudo-nMOS.

» Dissipate no DC power» Noise immunity is not sensitive to kn/kp

» Use of clocks enables synchronous operation» Rely on storage on soft node» Require exhaustive simulation at all the process

corners to insure proper operation» Some of the speed advantage over static gates is

diminished by the required per-charge (pre-discharge) time.

Dynamic Logic Circuits

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