DSP McBSPDSP

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PART ONE McBSPMcBSPMcBSP

McBSP

McBSPTMS320C2XC20XC5XC54XMcBSP ADC/DAC

McBSP

_ T1/E1 framers_ MVIP switching compatible and ST-BUS compliant devices including:_ MVIP framers_ H.100 framers_ SCSA framers_ IOM-2 compliant devices_ AC97 compliant devices _ IIS compliant devices_ SPI_ devices 128 8, 12, 16, 20, 24, and 32 bits U-Law and A-Law 8 LSB or MSB

McBSP

McBSPDXRXCLKX, CLKR, FSX, and FSR DSPCPUDMADRR[12](DXR[1,2]) (DXR[1,2])(XSR[1,2]) DXDR(RSR[1,2]) (RBR[1,2]) (RBR[1,2])DRR[1,2]DRR[1,2]CPUDMA C54XXMcBSP16

1McBSP

2McBSP

31SPCR1 SPCR1McBSP Clock StopDXA-bis (RSR[1,2])

42SPCR2 SPCR2McBSPSOFT (XSR[1,2])

5PCR PCRMcBSPCLKSDXDRPCR I/O

11RCR1 RCR1McBSPFIRST PHASE112881216202432bits

22RCR2 RCR2McBSPRPHASE=1McBSP112881216202432bits RCR2McBSP

11XCR1 XCR1McBSPFIRST PHASE112881216202432bits

22XCR2 XCR2McBSPXPHASE=1McBSP112881216202432bits XCR2McBSP

1

(CLKG)(FSGMcBSPCLKG FSGCLKR/XFSR/X

CPU CLKSSRGR2CLKSM

(CLKGDV) (FPER) (FWID

2SRGR1/2 1SRGR1WDLEN CLKGCLK1 2SRGR2CLKS

McBSP11)1MCR1 MCR1McBSPPART-BPART-A

22MCR2 MCR2McBSPPART-APART-B31-0-

2

(R/X)PHASE = 0FRLEN1 = 128WDLEN1 = bitsRMCM=0XMCM=0RPA/BBLKXPA/BBLKRCERA/BXCERA/BRMCM=1XMCM0

PART TWO McBSPMcBSPMcBSPDMAMcBSPMcBSPMcBSPa-law/u-law

McBSP1McBSP

/RS=0/RRST/XRSTDRCLKR/XFSR/XDX/GRSTCLKG=CPU/2FSG/RS/RRST/XRST/GRST/FRSTMcBSPMcBSP

McBSPMcBSP/RRST=0/XRST=0/FRST=0I/OPCRXIOENRIOEN

/GRSTCLKGCPU-CLK/2FSG/RS/GRSTCLKGSRGR1/FRSTFPERCLKGFSG2

1) Set XRST = RRST = FRST = 0 in SPCR[1,2]. If coming out of device re-set, this step is not required. 2) Program only the McBSP configuration registers (and not the data regis-ters) listed in Table-1 McBSP Registers, as required when the serial port is in reset state (XRST = RRST = FRST = 0).

3) Wait for two bit clocks. This is to ensure proper synchronization internally.4) Set up data acquisition as required such as writing to DXR.5) Set XRST = RRST= 1 to enable the serial port. Note that the value written to SPCR[1,2] at this time should have only the reset bits changed to 1, and the remaining bit-fields should have the same value as in step 2 above. 6) Set FRST = 1, if internally generated frame sync is required.7) Wait two bit clocks for the receiver and transmitter to become active.Alternatively, on either write (steps 1 and 5), the transmitter and receiver may be placed in or taken out of reset individually by modifying the desired bit. Note that the necessary duration of the active-low period of XRST or RRST is at least two bit-clocks (CLKR/CLKX) wide.

McBSP1CPU

(R/X)INTM=00(R/X)RDY DMA

(R/X)INTM=0116PARTITIONCPUPARTITION

(R/X)INTM=10(R/X)INT

(R/X)INTM = 11

2McBSP

RRDYREVTRINTRRDY0RBR[1,2]DRR[1,2]RRDYCPU or DMACPU or DMARRDY0RRDYMcBSPDMA (REVT)SPCR1RINTM = 00RRDYMcBSP(RINT)CPU

XRDYXEVTXINTXRDY = 1DXR[1,2]XSR[1,2]DXR[1,2]/XRST01)XRDY01DXR[1,2]XRDYJIU 0XRDYDMA (XEVT or XEVTA)SPCR2XINTM = 00XRDY (XINT) CPU

McBSPFSR, FSX, CLKX, and CLKR012CLKG0CLKG

u-LAW/A-LAW McBSP(R/X)COMPANDR/XWDLEN[1,2]00CPUDMA 16

DSP1DXR1DRR1/4XCOMPANDRCOMPANDDXR14CPUDRR1CPUDMA2XCOMPANDRCOMPANDCPUDMA

McBSP

XCOMPANDRCOMPANDA-law u-law McBSP BLD=1 RCOMPAND=10u-law ar3 ar4 0

A-law/u-law 1u-lawu2552 u-law

3 u-law4 u-law

5 u-law

6A-law A-lawCCITTA=87.6 7A-law

8 A-law9 A-law

10 A-law

11 u-lawA-law 1--0--

PCM

TIDSPu-lawA-law0x55

;; This is McBSP test program. The work-mode of McBSP Series:;; BLD=1 (Digital loop back mode enabled) ;; RCOMPAND=10 or 11 (u-law/A-law Expand: 8bits -> 16bits);; (R/X)INTM=00 (generate an interrupt every word traxsmitted);; ar3 -> Transmit data buffer(buffer_1);; ar4 -> receive data buffer(buffer_2);; The program is applicable for VC5409 ;; Designed by liyubai;; Modifing 1.0 Time 2001,6,28

.title "Test McBSP Program".mmregs.global mainstart.global interrupt_vectordrr11.set 41h;McBSP1 receive data registerdxr11.set 43h;McBSP1 transmit data registerspsa1.set 48h;McBSP1 sub_bank address register

spcd1.set 49h;McBSP1 sub_bank data register.bss stack_memory,500.bss buffer_1,1000.bss buffer_2,1000interrupt_vector:;interrupt vector table.textrsb mainstart nopnopnmi b __ret .word 0,0sint17 b __ret .word 0,0sint18 b __ret .word 0,0sint19 b __ret .word 0,0sint20 b __ret .word 0,0

sint21 b __ret .word 0,0sint22 b __ret .word 0,0sint23 b __ret .word 0,0sint24 b __ret .word 0,0sint25 b __ret .word 0,0sint26 b __ret .word 0,0sint27 b __ret .word 0,0sint28 b __ret .word 0,0sint29 b __ret .word 0,0sint30 b __ret .word 0,0int0 b __ret .word 0,0int1 b __ret .word 0,0int2 b __ret .word 0,0tint b __ret .word 0,0brint0 b __ret .word 0,0bxint0 b __ret .word 0,0dmac0 b __ret .word 0,0dmac1 b __ret .word 0,0int3 b __ret .word 0,0hpint b __ret .word 0,0

brint1 b McBSP1_receive_intnopnopbxint1 b McBSP1_transmit_intnopnopq28 .word 0,0,0,0q29 .word 0,0,0,0q30 .word 0,0,0,0q31 .word 0,0,0,0

mainstart: ssbx intm;close all interruptstm #0ffffh,ifr;cleare all interrupt_flagstm #0,clkmd;switch to DIV modets: ldm clkmd,a and #01b,a bc ts,aneq stm #5207h,clkmd;clkout=clkin X 6rpt #100 ;waits enough clocks

nop

stm #stack_memory,sp ;sp => stack_memory stm #0ff80h,pmst ;vector table start: 0xff80 stm #3610h,swwsr;I/O wait: 3clks, data_0x8000-;0xffff wait:3clks;program_0x8000-0xffff;wait:2clks call Clear_McBSP1_receive_buf call McBSP1_initializingrpt #0ffhnopstm #buffer_1,ar3stm #buffer_2,ar4ld #799,b;pre_put numberS of McBSP interruptstm #1800h,imr;enable RINT1,XINT1rsbx intm;enable all intwait_McBSP_int:nop

nopbc __ret,beqnopnopb wait_McBSP_intnop

__ret:noprete

McBSP1_initializing:stm #0,spsa1;choose SPCR11stm #08000h,spcd1;1000000000000000 => SPCR11. ;DLB(15)=1(Digital loop back moden enabled);RJUST(14-13)=00;CLKSTP(12-11)=00;RES(10-8)=000,DXENA(7)=0,ABIS(6)=0;RINTM(5-4)=00,RSYNCERR(3)=0,RFULL(2)=0;RRDY(1)=0,RRST(0)=0stm #1,spsa1;choose spcr21

stm #0h,spcd1;0000000000000000 => SPCR21.;RES(15-10)=000000,FREE(9)=0,SOFT(8)=0;FRST(7)=0,GRST(6)=0,XINT(5-4)=00,XSYNCERR(3)=0;XFULL(2)=0,XRDY(1)=0,XRST(0)=0stm #2,spsa1;choose RCR11stm #0,spcd1;0000000000000000 => RCR11.;RES(15)=0,RFRLEN1(14-8)=000 0000;RWDLEN1(7-5)=000,RES(4-0)=0 0000stm #3,spsa1;choose RCR21stm #10H,spcd1;0000000000010000 => RCR21.;RPHASE(15)=0,RFRLEN2(14-8)=000 0000;RWDLEN2(7-5)=000,RCOMPAND(4-3)=10(u-law EXPAND);RFIG(2)=0,RDATDLY(1-0)=00stm #4,spsa1;choose XCR11stm #0,spcd1;0000000000000000 => XCR11.;RES(15)=0,XFRLEN1(14-8)=000 0000;XWDLEN1(7-5)=000,RES(4-0)=0 0000stm #5,spsa1;choose XCR21stm #0,spcd1;0000000000000000 => XCR21.;XPHASE(15)=0,XFRLEN2(14-8)=000 0000

;XWDLEN2(7-5)=000,XCOMPAND(4-3)=00(No compand);XFIG(2)=0,XDATDLY(1-0)=00stm #6,spsa1;choose SRGR11stm #10fh,spcd1;0000000100001111 => SRGR11;FWID(15-8)=0000 0001,CLKGDV(7-0)=0000 1111stm #7,spsa1;choose SRGR21stm #0300FH,spcd1;0011000000010011 => SRGR21;GSYNC(15)=0,CLKSP(14)=0,CLKSM(13)=1(use CPU_clk);FSGM(12)=1(Internal SRG generate Transmit FS);FPER(11-0)=0000 0000 1111stm #0eh,spsa1;choose PCR1stm #0c01h,spcd1;0000101000000001 => PCR1;RES(15-14)=00,XIOEN(13)=0,RIOEN(12)=0;FSXM(11)=1,FSRM(10)=0,CLKXM(9)=1,CLKRM(8)=0;RES(7)=0,CLKS_STAT(6)=0,DX_STAT(5)=0,RX_STAT(4)=0;FSXP(3)=0,FSRP(2)=0,CLKXP(1)=0,CLKRP(0)=1rpt #0ffhnop stm #055h,dxr11;first data writed to dxr11

stm #0,spsa1;choose SPCR11stm #08001h,spcd1;1000000000000001 => SPCR11. ;McBSP1 receive enabled. stm #1,spsa1;choose spcr21stm #0c1h,spcd1;0000000011000001 => SPCR21.;McBSP1 sample rate generator,transmit enabled. nopnoprete

Clear_McBSP1_receive_buf:stm #buffer_2,ar4rpt #999st #0,*ar4+nopnoprete

McBSP1_receive_int:sub #1,bldm drr11,astl a,*ar4+noprete

McBSP1_transmit_int:ld *ar3+,axor #055hastlm a,dxr11noprete.end

0283201455E-mailybli@postoff1.uestc.cn