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Transcript of Dma _mutammad Malik
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University of Babylon College of Computers Technology Department of Software
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Computer Architecture
Direct Memory Access (DMA)
Name: MUTAMMAD MALIK
Stage: Third
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After DMA finishes its job it will make HOLD go low and then theCPU will regain control over the buses
Fig (1): DMA Usage of System Bus
DMA will go through the following steps:1. The peripheral device (such as the disk controller) will request the
service of DMA by pulling DREQ (DMA request) high.
2. The DMA will put a high on its HRQ (hold request), signaling theCPU through its HOLD pin that it needs to use the buses.
3. The CPU will finish the present bus cycle and respond to the DMArequest by putting high on its HLDA (hold acknowledge), thus
telling the 8237 DMA that it can go ahead and use the buses to
perform its task.4. HOLD must remain active high as long as DMA is performing its
task.5. DMA will activate DACK (DMA acknowledge), which tells the
peripheral device that it will start to transfer the data.
6. DMA starts to transfer the data from memory to peripheral asfollows DMA puts the address of the first byte of the block on the
address bus Activates MEMR, Reads the byte from memory into the data bus Then activates IOW to write it to the peripheral. Then DMA decrements the counter and increments the
address pointer
Repeats this process until the count reaches zero and thetask is finished.
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7. After the DMA has finished its job it will deactivate HRQ,signaling the CPU that it can regain control over its buses.
DMA ControllerThe DMA controller can issue commands to the memory that behave
exactly like the commands issued by the CPU. The DMA controller in a
sense is a second processor in the system but is dedicated to an I/O
function. The DMA controller as shown below connects one or more I/O
ports directly to memory, where the I/O data stream passes through the
DMA controller faster and more efficiently than through the processor as
the DMA channel is specialised to the data transfer task
Fig (2): A microcomputer with a direct memory-access
controller The task of a DMA-controller (DMAC) is to execute the copy
operation of data from one resource location to another. The copy
of data can be performed from:
- I/O-device to memory- Memory to I/O-device
- Memory to memory
- I/O-device to I/O-device
A DMAC is an independent (from CPU) resource of a computer systemadded for the concurrent execution of DMA-operations. The first two
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operation modes are read from and write to transfers of an I/O-device
to the main memory, which are the common operation of a DMA-
controller. The other two operations are slightly more difficult to
implement and most DMA-controllers do not implement device to device
transfers
Fig (3): simplified logical structure of a system with DMA
The DMAC replaces the CPU for the transfer task of data from the I/O-device to the main memory (or vice versa) which otherwise would have
been executed by the CPU using the programmed input output (PIO)
mode. PIO is realized by a small instruction sequence executed
by the processor to copy data. The memcpy function supplied by the
system is such a PIO operation.The DMAC is a master/slave resource on the system bus, because it
must supply the addresses for the resources being involved in a DMA
transfer. It requests the bus whenever a data value is available for
transport, which is signaled from the device by the REQ signal. The
functional unit DMAC may be integrated into other functional units in a
computer system, e.g. the memory controller, the south bridge, or directlyinto an I/O-device.
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Basic DMA operationThe direct memory access (DMA) I/O technique provides direct
access to the memory while the microprocessor is temporarily
disabled.
A DMA controller temporarily borrows the address bus, databus, and control bus from the microprocessor and transfers thedata bytes directly between an I/O port and a series of memory
locations.
The DMA transfer is also used to do high-speed memory tomemory transfers.
Two control signals are used to request and acknowledge aDMA transfer in the microprocessor-based system.
The HOLD signal is a bus request signal which asks themicroprocessor to release control of the buses after the currentbus cycle.
The HLDA signal is a bus grant signal which indicates that themicroprocessor has indeed released control of its buses byplacing the buses at their high-impedance states.
The HOLD input has a higher priority than the INTR or NMIinterrupt inputs.
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DMA interface with I/OInterfacing with the I/O port requires two signals per port-- TRANSFER
REQUEST and TRANSFER ACKplus the ability to generate I/O
READ/WRITE L to indicate to the port the direction of the transfer. The
DMA controller accepts a TRANSFER REQUEST from the port whenthe port has data ready to write into memory or has an empty buffer thatcan accept data from memory. When a transfer is to take place, the DMA
outputs the control signal TRANSFER ACK, which indicates the port
should receive data from or write data into memory.
Controller accessing memoryAs described before the DMA controller has a HALT request O/P signal
and a HALT ACKNOWLEDGE I/P. During the byte-by-byte transfer of
a block of data, the controller watches for a TRANSFER REQUEST ona channel. Then the controller asserts HALT and waits for HALT
ACKNOWLEDGE. This instructs the processor to relinquish the memorybus. When the processor relinquishes the bus it asserts HALT
ACKNOWLEDGE and the DMA controller has access to memory. The
controller simultaneously:
1. Places an address on the bus
2. Sends TRANSFER ACK to the requesting I/O port and3. Sends the proper polarity of READ/WRITE L to memory and the
complement of this signal to the I/O system.
DMA Operations
A lot of different operating modes exist for DMACs. The simplest one ist
the single block transfer copying a block of data from a device to
memory. For the more complex operations please refer to the literature
[Mot81]. Here, only a short list of operating modes is given: Fly-by
Data is directly transferred between memory and theperipheral
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Memory to Memory Data is not directly transferred, but buffered in between
transfers
Data is copied from the source location into a temporary area in the DMAchannel, and then written into the destination location
All these operations normally access the block of data in a linearsequence. Nevertheless, there are more usefull access functions possible,
as there are:Constant stride, constant stride with offset, incremental stride...
Fig (4)
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Execution of a DMA-operation (single block transfer)The CPU prepares the DMA-operation by the construction of a descriptor
(1), containing all necessary information for the DMAC to independently
perform the DMA-operation (offload engine for data transfer).
It initalizes the operation by writing a command to a registerIn the DMAC (2a) or to a special assigned memory area (command area),where the DMAC can poll for the command and/or the descriptor (2b).
Then the DMAC addresses the device data register (3) and read the data
into a temporary data register (4). In another bus transfer cycle, it
addresses the memory block (5) and writes the data from the temporary
data register to the memory block (6).
DMA on the IBM-PCWhat it is and how it works
Direct Memory Access (DMA) is a method of allowing data to be moved
from one location to another in a computer without intervention from thecentral processor (CPU).
The way that the DMA function is implemented varies between computer
architectures, so this discussion will limit itself to the implementation andworkings of the DMA subsystem on the IBM Personal Computer (PC),the IBM PC/AT and all of its successors and clones.
The PC DMA subsystem is based on the Intel 8237 DMA controller. The
8237 contains four DMA channels that can be programmed
independently and any one of the channels may be active at any moment.
These channels are numbered 0, 1, 2 and 3. Starting with the PC/AT,
IBM added a second 8237 chip, and numbered those channels 4, 5, 6 and7.
The original DMA controller (0, 1, 2 and 3) moves one byte in eachtransfer. The second DMA controller (4, 5, 6, and 7) moves 16-bits from
two adjacent memory locations in each transfer, with the first byte always
coming from an even-numbered address. The two controllers are identical
components and the difference in transfer size is caused by the way the
second controller is wired into the system.
The 8237 has two electrical signals for each channel, named DRQ and -
DACK. There are additional signals with the names HRQ (HoldRequest), HLDA (Hold Acknowledge), -EOP (End of Process), and the
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bus control signals -MEMR (Memory Read), -MEMW (Memory Write),-IOR (I/O Read), and -IOW (I/O Write).
The 8237 DMA is known as a ``fly-by'' DMA controller. This means that
the data being moved from one location to another does not pass throughthe DMA chip and is not stored in the DMA chip. Subsequently, the
DMA can only transfer data between an I/O port and a memory address,
but not between two I/O ports or two memory locations.
In the PC architecture, each DMA channel is normally activated only
when the hardware that uses a given DMA channel requests a transfer
by asserting the DRQ line for that channel
A Sample DMA transfer (IBM-PC) Peripheral (say disk controller) asserts DRQ2 DMA requests buses by asserting HRQCPU releases bus and asserts HLDA DMA asserts theDACK2 to peripheral Peripheral places the byte to be transferred on the bus Data lines DMA will de-assert the HRQ signal.CPU sees this, and de-asserts the HOLDA signal
Here is an example of the steps that occur to cause and perform a
DMA transfer. In this example, the floppy disk controller (FDC) has
just read a byte from a diskette and wants the DMA to place it in
memory at location 0x00123456. The process begins by the FDC
asserting the DRQ2 signal (the DRQ line for DMA channel 2) to alertthe DMA controller.
The DMA controller will note that the DRQ2 signal is asserted. The
DMA controller will then make sure that DMA channel 2 has been
programmed and is unmasked (enabled). The DMA controller alsomakes sure that none of the other DMA channels are active or want to
be active and have a higher priority. Once these checks are complete,
the DMA asks the CPU to release the bus so that the DMA may use
the bus. The DMA requests the bus by asserting the HRQ signal whichgoes to the CPU.
The CPU detects the HRQ signal, and will complete executing the
current instruction. Once the processor has reached a state where it can
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release the bus, it will. Now all of the signals normally generated by
the CPU (-MEMR, -MEMW, -IOR, -IOW and a few others) are
placed in a tri-stated condition (neither high or low) and then the CPU
asserts the HLDA signal which tells the DMA controller that it is now
in charge of the bus.
Depending on the processor, the CPU may be able to execute a few
additional instructions now that it no longer has the bus, but the CPU
will eventually have to wait when it reaches an instruction that must
read something from memory that is not in the internal processorcache or pipeline.
Now that the DMA ``is in charge'', the DMA activates its -MEMR, -
MEMW, -IOR, -IOW output signals, and the address outputs from the
DMA are set to 0x3456, which will be used to direct the byte that isabout to transferred to a specific memory location.
The DMA will then let the device that requested the DMA transfer
know that the transfer is commencing. This is done by asserting the -
DACK signal, or in the case of the floppy disk controller, -DACK2 isasserted.
Sources
1- Vorlesung Rechnerarchitektur by Prof. Dr.-Ing. Bernhard Lang
2- Texas Instruments 2009, chapter 11 www.le.ac.uk/eg/fss1/
1.(ThirdThe Winn L. Rosch Hardware BibleWinn L. Rosch.-3
Edition), Sams Publishing, 1994
4- Frank Durda IV , 1995, 1997
http://www.freebsd.org/handbook/dma.html
http://www.whatis.com/booksrec.htm#roschhttp://www.whatis.com/booksrec.htm#roschhttp://www.freebsd.org/handbook/dma.htmlhttp://www.freebsd.org/handbook/dma.htmlhttp://www.whatis.com/booksrec.htm#rosch -
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