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Ph.D.Dissertation

A Study on Low-Power, High-

Speed PAM-4 Transmitter with

Current-Driven Feedback Driver

전류구동 피드백 드라이버를 활용한

저전력, 고속 PAM-4 송신기 설계에 관한 연구

by

Haram Ju

August, 2019

School of Electrical Engineering and Computer Science

College of Engineering

Seoul National University




지도 교수 정 덕 균

이 논문을 공학박사 학위논문으로 제출함

2019 년 6 월

서울대학교 대학원

전기·컴퓨터공학부

주 하 람

주하람의 박사 학위논문을 인준함

2019 년 6 월

위 원 장 (인)

부위원장 (인)

위 원 (인)

위 원 (인)

위 원 (인)




by

Haram Ju

A Dissertation Submitted to the Department of

Electrical and Computer Engineering

in Partial Fulfillment of the Requirements for the Degree of

Doctor of Philosophy

at

SEOUL NATIONAL UNIVERSITY

June, 2019

Committee in Charge:

Professor Hyuk-Jae Lee, Chairman

Professor Deog-Kyoon Jeong, Vice-Chairman

Professor Dongsuk Jeon

Professor Jung-Hoon Chun

Professor Yongsam Moon

ABSTRACT I

Abstract

The bandwidth requirement of wireline communications has increased exponen-

tially because of the ever-increasing demand for data centers and high-performance

computing systems. However, the per-pin bandwidth improvements of high-speed

I/O circuits are faced with difficulties due to various limitations of the copper-based

channel. As a result, instead of non-return-to-zero (NRZ) signaling, multi-level sig-

naling, which increases the data rate at the same Nyquist frequency, provides an ef-

fective solution for the next-generation high-bandwidth I/O interfaces. In special,

four-level pulse-amplitude modulation (PAM-4) is widely adopted to meet the

bandwidth demand for industrial standards. Conventional PAM-4 transmitters based

on typical voltage-driven drivers exhibit limited energy efficiency due to the power-

hungry pre-driver and multi-tap feed-forward equalization (FFE) structure. To over-

come the drawbacks of existing voltage-driven PAM-4 drivers, in this thesis, the

concept of the current-driven feedback driver newly defined by the author is intro-

duced, and two prototypes of low-power, high-speed PAM-4 transmitters using the

resistive-feedback (RFB) or the active-feedback (AFB) driver are proposed.

As the first prototype, a 28 Gb/s PAM-4 transmitter with a fractionally spaced 3-

tap FFE and a Gm-regulated RFB driver is fabricated in 28 nm CMOS technology.

Owing to the current-driven characteristic of the driver, the 3-tap FFE is realized at

the pre-driver stage in a simplified current-summing manner consuming low power

consumption. The output impedance of the driver is controlled by regulating the Gm

of the driver cell, which results in good signal integrity. To obtain the appropriate

ABSTRACT II

tap delay, a novel topology is introduced for the delay generator to enhance both the

delay and the bandwidth. All the transmitter circuits are CMOS-based implemented

thanks to the increased bandwidth by using a resistive feedback. The transmitter

achieves the data rate of 28 Gb/s while consuming 44.6 mW, which results in the

energy efficiency of 1.59 pJ/b.

As the second prototype, a 64 Gb/s PAM-4 transmitter with a current-summing

3-tap FFE and a Gm-regulated AFB driver is presented. An AFB inverter-based driv-

er is proposed to achieve a larger output swing compared with the RFB driver with

limited output swing. The FFE tap generation is embedded into the serializer to min-

imize the overhead of FFE, by replacing a power-hungry delay generator. As a result,

both the energy efficiency and the operating speed are considerably enhanced com-

pared to the first prototype. A prototype chip is fabricated in 28 nm CMOS technol-

ogy, and occupies 0.185 mm2. Owing to the improved loop bandwidth of the phase-

locked loop (PLL), the integrated RMS jitter from 1 kHz to 40 MHz is measured as

115 fs, which exhibits the state-of-the-art PLL figure-of-merit (FoM) of -244.1 dB.

The proposed transmitter achieves the data rate 64 Gb/s while consuming 97.2 mW,

which exhibits the best energy efficiency of 1.5 pJ/b among recently reported PAM-

4 transmitters with an internal PLL.

Keywords : CMOS, multi-level signaling, PAM-4 transmitter, resistive-feedback

(RFB) driver, active-feedback (AFB) driver, voltage- and current-driven driver

Student Number : 2013-20891

CONTENTS III

Contents

ABSTRACT I

CONTENTS III

LIST OF FIGURES VI

LIST OF TABLES XII

CHAPTER 1 INTRODUCTION 1

1.1 MOTIVATION .................................................................................................... 1

1.2 THESIS ORGANIZATION .................................................................................... 7

CHAPTER 2 BACKGROUND OF MULTI-LEVEL SERIAL LINK 9

2.1 OVERVIEW ........................................................................................................ 9

2.2 BASICS OF MULTI-LEVEL SIGNALING ............................................................ 13

2.3 THEORETICAL ANALYSIS ................................................................................ 21

2.3.1 SENSITIVITY ........................................................................................... 21

2.3.2 SYMBOL ERROR RATE AND BIT ERROR RATE ....................................... 22

CHAPTER 3 CURRENT-DRIVEN FEEDBACK DRIVER 28

3.1 OVERVIEW ...................................................................................................... 28

3.2 VOLTAGE-DRIVEN DRIVERS ........................................................................... 31

3.2.1 BASICS OF CONVENTIONAL DRIVERS .................................................... 31

3.2.2 DRAWBACKS .......................................................................................... 44

CONTENTS IV

3.2.3 CONVENTIONAL PAM-4 DRIVERS ......................................................... 49

3.3 BASIC CONCEPT .............................................................................................. 53

3.3.1 RESISTIVE-FEEDBACK (RFB) DRIVER ................................................... 53

3.3.2 ACTIVE-FEEDBACK (AFB) DRIVER ....................................................... 58

3.4 ANALYSES AND DESIGN ISSUES ..................................................................... 66

3.4.1 MATCHING CHARACTERISTIC ................................................................ 66

3.4.2 FEED-FORWARD EQUALIZATION ........................................................... 76

3.4.3 LINEARITY ............................................................................................. 86

3.4.4 CIRCUIT BANDWIDTH ............................................................................ 88

CHAPTER 4 LOW-POWER HIGH-SPEED PAM-4 TRANSMITTER 90

4.1 OVERVIEW ...................................................................................................... 90

4.2 SYSTEM ARCHITECTURE ................................................................................. 93

4.3 CIRCUIT IMPLEMENTATION ............................................................................ 96

4.3.1 FRONT-END WITH CURRENT-SUMMING FFE ........................................ 96

4.3.2 GM CALIBRATION ................................................................................. 100

4.3.3 SERIALIZER WITH TAP GENERATION ................................................... 104

4.3.4 HALF-RATE CLOCK GENERATION ....................................................... 109

4.4 MEASUREMENT RESULTS ............................................................................. 112

4.4.1 28-GBIT/S 1.6-PJ/BIT PAM-4 TRANSMITTER WITH RFB DRIVER ........ 112

4.4.2 64-GBIT/S 1.5-PJ/BIT PAM-4 TRANSMITTER WITH AFB DRIVER ....... 116

CHAPTER 5 CONCLUSION 122

BIBLIOGRAPHY 125

CONTENTS V

초 록 136

LIST OF FIGURES VI

List of Figures

FIG. 1.1 FORECAST OF GLOBAL IP TRAFFIC ................................................................................ 2

FIG. 1.2 (A) ESTIMATED U.S. DATA CENTER ELECTRICITY CONSUMPTION BY MARKET SEGMENT

IN 2011 (B) POWER BREAKDOWN OF DATA CENTER. ....................................................... 4

FIG. 1.3 TYPICAL ARCHITECTURE OF PAM-4 TRANSCEIVER ...................................................... 5

FIG. 2.1 TRENDS OF PER-LANE DATA RATE OF INDUSTRIAL I/O STANDARDS ........................... 10

FIG. 2.2 POSSIBLE CANDIDATES OF ELECTRICAL COPPER BACKPLANE ARCHITECTURE ............ 12

FIG. 2.3 NEXT-GENERATION INTERCONNECT APPLICATION SPACES ........................................... 12

FIG. 2.4 CLASSIFICATION AND CONDITIONS OF LINK FOR CEI-56G APPLICATION SPACES ....... 12

FIG. 2.5 BINARY (PAM-2) AND MULTI-LEVEL SIGNALING (PAM-4) ....................................... 13

FIG. 2.6 NORMALIZED POWER SPECTRAL DENSITY OF NRZ, PAM-4, PAM-8 AND PAM-16

DATA WITH (A) LINEAR SCALE AND (B) LOGARITHMIC SCALE ....................................... 16

FIG. 2.7 BASIC EYE DIAGRAMS OF (A) NRZ AND (B) PAM-4 SIGNAL ...................................... 17

FIG. 2.8 LINEARITY TEST PATTERN FOR PAM-4 TRANSMITTER ............................................... 18

FIG. 2.9 PAM-4 SYMBOL LEVELS WITH A HORIZONTAL EYE MASK .......................................... 20

FIG. 2.10 POWER DENSITY FUNCTION FOR PAM-M SIGNAL .................................................... 23

FIG. 2.11 SYMBOL ERROR RATE FOR PAM-M SIGNALS ........................................................... 25

FIG. 2.12 APPROXIMATED BERS OF PAM-M SIGNALS WITH USING (A) GRAY CODING AND (B)

LINEAR CODING ............................................................................................................. 27

FIG. 3.1 EQUIVALENT CIRCUITS OF (A) VOLTAGE- AND (B) CURRENT-MODE DRIVER ............... 29

FIG. 3.2 TYPICAL CIRCUIT DIAGRAM OF CONVENTIONAL (A) N-OVER-N VOLTAGE-MODE DRIV-

ER AND (B) P-OVER-N VOLTAGE-MODE DRIVER ........................................................... 33

LIST OF FIGURES VII

FIG. 3.3 REGULATORS FOR IMPEDANCE CALIBRATION OF N-OVER-N VOLTAGE-MODE DRIVER

...................................................................................................................................... 34

FIG. 3.4 (A) PULL-DOWN REGULATOR AND (B) PULL-UP REGULATOR FOR IMPEDANCE

CALIBRATION OF P-OVER-N VOLTAGE-MODE DRIVER .................................................. 36

FIG. 3.5 EQUIVALENT CIRCUIT OF VOLTAGE-MODE DRIVER WITH PRE-EMPHASIS .................... 38

FIG. 3.6 (A) ORIGINAL STACKED STRUCTURE IN [35] AND (B) STACKED STRUCTURE WITH SIN-

GLE SHARED LINEARIZATION RESISTOR ........................................................................ 40

FIG. 3.7 FINAL STRUCTURE WITH RELOCATED CLOCKED MUX TRANSISTORS ......................... 41

FIG. 3.8 TYPICAL CIRCUIT DIAGRAM OF A CONVENTIONAL CML DRIVER ............................... 42

FIG. 3.9 TYPICAL CIRCUIT DIAGRAM OF A PUSH-PULL CURRENT-MODE DRIVER ...................... 43

FIG. 3.10 SIGNAL DISTORTION CAUSED BY VARYING IMPEDANCE OF P-OVER-N VM DRIVER . 45

FIG. 3.11 SIMPLIFIED BLOCK DIAGRAMS OF SEGMENTED VOLTAGE-DRIVEN DRIVERS WITH

MULTI-TAP FFE: (A) VOLTAGE-MODE DRIVER AND (B) CURRENT-MODE DRIVER ......... 46

FIG. 3.12 SIMPLIFIED BLOCK DIAGRAMS OF (A) SST-BASED PAM-4 DRIVERS AND (B) CML-

BASED PAM-4 DRIVERS ................................................................................................ 50

FIG. 3.13 SIMPLIFIED BLOCK DIAGRAM OF HYBRID PAM-4 DRIVER IN [11] ............................ 51

FIG. 3.14 EQUIVALENT CIRCUIT OF CURRENT-DRIVEN FEEDBACK DRIVER .............................. 53

FIG. 3.15 CIRCUIT DIAGRAM OF RESISTIVE-FEEDBACK DRIVER AND GENERAL EFFECT OF RESIS-

TIVE FEEDBACK ON TRANSFER FUNCTION OF AMPLIFIER .............................................. 54

FIG. 3.16 TYPICAL CIRCUIT DIAGRAM OF RESISTIVE-FEEDBACK DRIVER WITH SUPPLY REGULA-

TION .............................................................................................................................. 56

FIG. 3.17 SIMPLIFIED BLOCK DIAGRAMS OF RFB INVERTER-BASED PAM-4 DRIVERS WITH (A)

TYPE-1 PRE-DRIVER AND (B) TYPE-2 PRE-DRIVER ......................................................... 57

FIG. 3.18 TWO EQUIVALENT CIRCUIT DIAGRAMS OF ACTIVE-FEEDBACK DRIVER .................... 58

LIST OF FIGURES VIII

FIG. 3.19 SMALL-SIGNAL EQUIVALENT CIRCUIT FOR OUTPUT IMPEDANCE CALCULATION OF

ACTIVE-FEEDBACK DRIVER WITH A POSITIVE INPUT BIAS (I.E. 0INI ). .................... 60

FIG. 3.20 SMALL-SIGNAL EQUIVALENT CIRCUIT FOR OUTPUT IMPEDANCE CALCULATION OF

ACTIVE-FEEDBACK DRIVER WITH A NEGATIVE INPUT BIAS (I.E. 0INI ) ................... 60

FIG. 3.21 SIMULATED AC OUTPUT IMPEDANCES OF RESISTIVE-FEEDBACK AND ACTIVE-

FEEDBACK DRIVER ACCORDING TO THE VARIOUS INPUT BIAS CURRENT ....................... 63

FIG. 3.22 SIMULATED OUTPUT SWING COMPARISON BETWEEN RESISTIVE-FEEDBACK DRIVER

AND ACTIVE-FEEDBACK DRIVER ................................................................................... 65

FIG. 3.23 TERMINATED TRANSMISSION LINE AND ITS THEVENIN-EQUIVALENT MODEL ........... 66

FIG. 3.24 CIRCUIT DIAGRAM OF (A) ONE-STACKED VM DRIVER AND (B) RFB DRIVER DRIVEN

BY A CMOS INVERTER-BASED PRE-DRIVER ................................................................. 68

FIG. 3.25 IDEAL 10 GB/S PRBS 27-1 DATA APPLIED TO BOTH PRE-DRIVER INPUTS .................. 71

FIG. 3.26 SIMULATED REAL-TIME OUTPUT IMPEDANCE OF (A) VOLTAGE-MODE DRIVER AND (B)

RESISTIVE-FEEDBACK DRIVER ....................................................................................... 72

FIG. 3.27 CALCULATED REAL-TIME (A) OUTPUT RETURN LOSS (RL) AND (B) VOLTAGE SWING

WAVE RATIO (VSWR) FROM SIMULATED OUTPUT IMPEDANCE .................................... 73

FIG. 3.28 SIMULATED PEAK-TO-PEAK JITTER WITH 10 GB/S PRBS 211-1 DATA FOR VARYING

RECEIVER-SIDE TERMINATION IMPEDANCE ................................................................... 74


RISE/FALL TIME OF THE INPUT SIGNAL WITH RXTR OF 70 Ω (+40%) .......................... 75


SUPPLY VOLTAGE OF DRIVER WITH RXTR OF 30 Ω (-40%) ......................................... 75

FIG. 3.31 THREE TYPES OF PRE-DE-EMPHASIS IMPLEMENTATION FOR VOLTAGE-MODE DRIVER

(A) RESISTIVE-DIVIDER-BASED PE, (B) CHANNEL-SHUNTING-BASED PE, AND (C) IM-

LIST OF FIGURES IX

PEDANCE-MODULATION-BASED PE ............................................................................... 76

FIG. 3.32 CIRCUIT DIAGRAM OF PSEUDO-DIFFERENTIAL VM DRIVER DRIVEN BY THE INVERTER

CHAIN ............................................................................................................................ 79

FIG. 3.33 COMPARISON OF DRIVER POWER CONSUMPTION WHEN USING THREE TYPES OF PE . 81

FIG. 3.34 COMPARISON OF PRE-DRIVER POWER CONSUMPTION WHEN USING THREE TYPES OF

PE ................................................................................................................................. 81

FIG. 3.35 OVERALL POWER CONSUMPTION OF VM DRIVERS VERSUS NORMALIZED OUTPUT

SWING ........................................................................................................................... 82

FIG. 3.36 CURRENT-SUMMING FFE IMPLEMENTATION FOR RFB DRIVER ................................ 83

FIG. 3.37 PSEUDO-DIFFERENTIAL RFB DRIVER WITH DC-COUPLED TERMINATION ................. 83

FIG. 3.38 OVERALL POWER CONSUMPTION OF RFB DRIVER VERSUS NORMALIZED OUTPUT

SWING ........................................................................................................................... 85

FIG. 3.39 DIFFERENTIAL OUTPUT SWING VERSUS DIFFERENTIAL INPUT CURRENT OF RFB DRIV-

ER .................................................................................................................................. 86

FIG. 3.40 SIMULATED LINEAR SWING RANGE (LSR) AND VOLTAGE SWING WAVE RATIO

(VSWR) OF RFB DRIVER ACCORDING TO OUTPUT IMPEDANCE ................................... 87

FIG. 3.41 CIRCUIT BANDWIDTH COMPARISON OF VOLTAGE-MODE DRIVER, CML-BASED DRIV-

ER, AND RESISTIVE-FEEDBACK DRIVER ......................................................................... 88

FIG. 3.42 CHANNEL MODEL FOR BANDWIDTH COMPARISON SIMULATION ............................... 89

FIG. 4.1 TRENDS OF NORMALIZED ENERGY EFFICIENCY OF RECENTLY REPORTED PAM-4

TRANSMITTERS IN [9], [11], [69]-[79], [82] VERSUS PER-PIN DATA RATE ..................... 91

FIG. 4.2 OVERALL ARCHITECTURE OF TWO PROTOTYPE PAM-4 TRANSMITTERS (A) PAM-4

TRANSMITTER WITH FRACTIONALLY SPACED 3-TAP FFE AND GM-REGULATED RFB

DRIVER (PROTOTYPE 1) AND (B) PAM-4 TRANSMITTER WITH 3-TAP FFE AND GM-

LIST OF FIGURES X

REGULATED AFB DRIVER (PROTOTYPE 2) .................................................................... 94

FIG. 4.3 CONCEPTUAL DIAGRAM OF PAM-4 DRIVER BASED ON CURRENT-DRIVEN FEEDBACK

DRIVER .......................................................................................................................... 96

FIG. 4.4 CIRCUIT DIAGRAM OF RFB PAM-4 DRIVER IN PROTOTYPE 1 WITH CURRENT-SUMMING

PRE-DRIVER FOR 3-TAP FFE IMPLEMENTATION ............................................................ 97

FIG. 4.5 SIMULATED PAM-4 EYE OUTPUT WITH VARIOUS CELL SIZE OF DATA-FEEDTHROUGH

COMPENSATION (DFC) ................................................................................................. 98

FIG. 4.6 BLOCK DIAGRAM OF AFB PAM-4 TRANSMITTER FRONT-END IN PROTOTYPE 2 CON-

SISTING OF AFB PAM-4 DRIVER, PRE-DRIVER, AND GM CALIBRATION CIRCUITS ......... 99

FIG. 4.7 CIRCUIT DIAGRAM OF AFB PAM-4 DRIVER IN PROTOTYPE 2 WITH CURRENT-SUMMING

PRE-DRIVER FOR 3-TAP FFE IMPLEMENTATION ............................................................ 99

FIG. 4.8 BASIC CONCEPT FOR CONSTANT- mG BIAS GENERATOR .......................................... 100

FIG. 4.9 CIRCUIT DIAGRAM OF mG CALIBRATION CIRCUIT CONSISTING OF CONSTANT- mG

BIAS GENERATOR AND VOLTAGE REGULATOR ............................................................ 102

FIG. 4.10 SIMULATED OUTPUT IMPEDANCE OF THE DRIVER FOR (A) PROCESS CORNER AND

TEMPERATURE (PT) VARIATIONS AND FOR (B) PROCESS CORNER AND VOLTAGE (PV)

VARIATIONS ................................................................................................................ 103

FIG. 4.11 CIRCUIT DIAGRAM OF SUB-UI TAP DELAY GENERATOR FOR FRACTIONALLY SPACED

FFE ............................................................................................................................. 104

FIG. 4.12 SIMULATED TUNABLE DELAY RANGE OF SUB-UI DELAY GENERATOR .................... 105

FIG. 4.13 BLOCK DIAGRAM OF CLOCK AND DATA PATH FOR SERIALIZATION AND TAP GENERA-

TION ............................................................................................................................ 105

FIG. 4.14 BLOCK DIAGRAM AND TIMING DIAGRAM OF THE TAP GENERATING SERIALIZER .... 106

FIG. 4.15 CIRCUIT DIAGRAM OF PROPOSED LAST-STAGE 2-TO-1 SERIALIZER ......................... 108

LIST OF FIGURES XI

FIG. 4.16 POST-LAYOUT SIMULATED EYE DIAGRAMS AT THE SERIALIZER OUTPUT (A) WITHOUT

PRE-CHARGING AND –DISCHARGING DEVICES AND (B) WITH PRE-CHARGING AND –

DISCHARGING DEVICES ............................................................................................... 108

FIG. 4.17 CIRCUIT DIAGRAM OF IMPLEMENTED TWO-STAGE RING OSCILLATOR .................... 109

FIG. 4.18 BLOCK DIAGRAM OF PHASE-LOCKED LOOP (PLL) FOR HALF-RATE CLOCK GENERA-

TION ............................................................................................................................ 110

FIG. 4.19 CIRCUIT DIAGRAM OF MISMATCH REDUCED CHARGE PUMP FOR WIDE-RANGE LOOP

BANDWIDTH CONTROL OF THE PHASE-LOCKED LOOP .................................................. 110

FIG. 4.20 CHIP MICROPHOTOGRAPH OF PAM-4 TRANSMITTER (PROTOTYPE 1) ..................... 112

FIG. 4.21 MEASURED DIVIDED-BY-16 TRANSMITTER CLOCK (437.5 MHZ) ........................... 113

FIG. 4.22 OUTPUT RETURN LOSS (S11) MEASURED AT DRIVER OUTPUT .................................. 113

FIG. 4.23 MEASURED DIFFERENTIAL PAM-4 EYE DIAGRAM AT 28 GB/S ............................... 114

FIG. 4.24 MEASURED DIFFERENTIAL PAM-4 EYE DIAGRAMS WITH VARIOUS FFE CONDITIONS

.................................................................................................................................... 114

FIG. 4.25 MEASURED POWER BREAKDOWN OF THE PROTOTYPE-1 PAM-4 TRANSMITTER ..... 115

FIG. 4.26 CHIP MICROPHOTOGRAPH OF PAM-4 TRANSMITTER (PROTOTYPE 2) AND MEASURED

POWER BREAKDOWN AT 64 GB/S OPERATION ............................................................. 116

FIG. 4.27 MEASUREMENT SETUP FOR PROTORYPE-2 PAM-4 TRANSMITTER .......................... 117

FIG. 4.28 MEASURED DIVIDED-BY-16 TRANSMITTER CLOCK (1 GHZ) ................................... 117

FIG. 4.29 MEASURED FREQUENCY SPECTRUM AND PHASE NOISE PLOT OF THE DIVIDED-BY-16

TRANSMITTER CLOCK (1 GHZ) .................................................................................... 118

FIG. 4.30 MEASURED SINGLE-ENDED OUTPUT RETURN LOSS OF PAM-4 DRIVER ................... 118

FIG. 4.31 MEASURED SINGLE-ENDED NRZ (22.5 GB/S, 28 GB/S, AND 32 GB/S) AND PAM-4 (45

GB/S, 56 GB/S, AND 64 GB/S) OUTPUT EYE DIAGRAMS ............................................... 119

LIST OF TABLES XII

List of Tables

TABLE 2.1 AVERAGE HAMMING DISTANCE OF PAM-M SIGNALS WITH VARIOUS CODING ...... 26

TABLE 3.1 CURRENT LEVEL CONSUMED BY THE DRIVER ACCORDING TO RECEIVER-SIDE TER-

MINATION ...................................................................................................................... 32

TABLE 3.2 COMPARISON OF SST-BASED PAM-4 DRIVERS AND CML-BASED PAM DRIVERS . 52

TABLE 3.3 OPERATING REGIONS OF THE TRANSISTORS OF RFB DRIVER ACCORDING TO OUTPUT

SWING ........................................................................................................................... 59

TABLE 4.1 PERFORMANCE SUMMARY AND COMPARISON OF PAM-4 TRANSMITTERS ........... 121

Chapter 1. Introduction 1

Chapter 1

Introduction

1.1 Motivation

Today, the emergence of the concept of the internet of things (or it’s also known,

IoT) allows everyone to be fully connected through the internet. For example, peo-

ple use personal cloud services to store documents, and social network services to

share their daily lives. Considering further expansion into the industrial sector, the

cloud-based computing, networking and storage infrastructure of the exponentially

growing data centers process a vast amount of information every day. In fact, Cisco

predicts that global IP traffic will increase to nearly 300 Exabytes/month by 2021

from the current trend of annual growth rates of more than 20%, as illustrated in Fig

1.1 [1]. Note that, this is very much related to the growing demand for streaming

media such as high-definition internet video and audio, which means that the


computing speed and throughput of the electronics (i.e. CPU, memory) must be im-

proved. In addition, this dramatic increase in the amount of information will lead to

the development of the data communication system in chip-to-chip, board-to-board,

and rack-to-rack interconnection applications. Indeed, Multi-core microprocessor

input/output (I/O) bandwidth has improved aggressively at a rate of 2-3X every two

years [2]. However, the per-pin bandwidth improvements of high-speed I/O circuits

for wireline communication are faced with difficulties due to various limitations of

the copper-based channel: signal attenuation, distortion, and cross-talk. As a result,

electrical links based on multi-level signaling (i.e. pulse-amplitude modulation

(PAM)) and optical links based on silicon photonics have attracted much attention as

new potential solutions for the next-generation high-bandwidth I/O interface [3].

According to survey results of data center user’s group (DCUG) surveyed in

2014, 32.3% (energy efficiency), 29.2% (heat density), and 23.8% (power density)

Fig. 1.1 Forecast of global IP traffic.


of respondents selected energy-related problems as one of the top concerns [4]. In

reality, U.S. data centers consumed an estimated 91 billion kilowatt-hours (kWh) of

electricity in 2013. By 2020, this figure is projected to increase to roughly 140 bil-

lion kWh which cost American business $13 billion per year in electricity bills [5].

Estimated U.S. data center electricity consumption by market segment and power

breakdown of the data center are illustrated in Fig. 1.2. As shown in Fig. 1.2(b), a

large proportion of energy consumption is used to cool the heat dissipation of serv-

ers [6]. Moreover, the unsatisfactory battery development also causes energy prob-

lems to deteriorate. As a simple example, the mobile battery energy density, unlike

microprocessors, is not met by Moore’s law and increased by only 1.3 times from

2007 to 2014. So, for these reasons, not only enhancing per-pin bandwidth but also

improving energy efficiency becomes a crucial issue for next-generation I/O systems.

Meanwhile, the use of multi-level signaling that multiplies the data rate at the

same Nyquist frequency as non-return-to-zero (NRZ) modulation makes I/O circuits

address higher data throughput even for bandwidth-limited interconnect. In special,

four-level pulse-amplitude modulation (PAM-4) is widely adopted to support higher

communication speed to meet newest electrical link standards: Optical internetwork-

ing forum common electrical I/O-56G-Very short-/ Medium-/ Long-reach (OIF-

CEI-56G-VSR/MR/LR) and IEEE P802.3bs 400 Gb/s Ethernet standards [7], [8].

Typical serializer/ deserializer (SerDes) structure of PAM-4 transceiver in standard

complementary metal-oxide-semiconductor (CMOS) interface is shown in Fig. 1.3

[9]. Similar to other serializing transmitters, there are several design issues with the

PAM-4 transmitter. The impact of reflection and crosstalk on PAM-4 signal could

be 3x worse in magnitude than on NRZ or PAM-2 signal [10]. As a result, supply


and impedance regulation of an output driver regardless of process, voltage, and

temperature (PVT) variation is more important for PAM-4 transmitter. The intra-

(a)

(b)

Fig. 1.2 (a) Estimated U.S. data center electricity consumption by market segment in

2011 (b) Power breakdown of data center.

49%

27%

19%

4%

1%

Small- and Medium-Sized Data Centers

Enterprise/ Corporate

Multi-Tenant Data Centers

Hyper-Scale Cloud Computing

High-Performance Computing

50%

26%

11%

10%

3%

0% 10% 20% 30% 40% 50% 60%

Cooling

Server & Storage

Power Conversion

Network Hardware

Lighting


pair skew of most-significant-bit (MSB) and least-significant-bit (LSB) can also de-

teriorate the signal integrity of the PAM-4 signal significantly. In addition, nonline-

arity can have a much larger impact on PAM-4 than on NRZ, which is greater as the

number of signal levels increases [11]. In general, multi-level signaling needs a large

dynamic range of the transmitter output from a signal-to-ratio (SNR) perspective,

but the output driver usually experiences a severe nonlinearity problem as the output

Map

pin

g &

Lo

cal E

nco

der

DRV

PLL

MUX

MUXMSB

LSB

CKref

Da

ta C

han

ne

l

Pre-amp/ EQ

Adaptation

DFE

CDR

PA

M-4

De

co

de

r

DMUX

DMUX

Lo

cal D

eco

der

AS

IC

FFE

Supply & Imp. Reg.

PAM-4 Transmitter

PAM-4 Receiver

Fig. 1.3 Typical architecture of PAM-4 transceiver.


swing rises. Therefore, when designing a multi-level signaling output driver (e.g.

PAM-4 driver), much care is required to find the optimal point in terms of trade-off

between linearity and swing. On the other hand, various feed-forward equalization

(FFE) techniques have been used in high-speed serializing transmitters to compen-

sate for the bandwidth degradation due to copper-based link and package, which is

not an exception to the PAM-4 transmitter [12]-[15]. However, the use of FFE often

increases hardware complexity and thus increases the dynamic power dissipation of

the pre-driving buffers. It can also causes the inherent circuit bandwidth to drop by

adding parasitic elements (e.g. parasitic capacitance, series resistance) depending on

the driver structure. Naturally, designing straightforward and energy-efficient equal-

ization structures is an important condition for improving the overall transmitter per-

formance [16]. To sum it up, the reduction of the driver size to reduce dynamic pre-

driver power, simplification of pre-driver stage and FFE structure, and all CMOS-

based implementation are key factors to implement the high-speed and energy-

efficient PAM-4 serializing transmitter. In this thesis, various circuit techniques for

enhancing both the per-pin bandwidth and energy efficiency of the transmitter are

proposed. The proposed design of PAM-4 transmitter achieves high data rate and

lower power consumption compared to the state-of-the-art designs.


1.2 Thesis Organization

This thesis is organized as follows. In Chapter 2, an overview of high-speed mul-

ti-level serial link is presented by reviewing the basics of multi-level signaling and

listing practical design issues of high-speed CMOS interface circuits for multi-level

signaling communication. In addition, theoretical analyses about sensitivity and er-

ror rate issues with using multi-level signaling are discussed in Chapter 2.

In Chapter 3, a brief review and discussion about conventional voltage-mode

(VM) and current-mode (CM) output driver classified as voltage-driven drivers by

the author are presented. The drawbacks of voltage-driven drivers are also examined

and conventional current-mode logic (CML) and source-series terminated (SST)

driver based PAM-4 transmitters are described. On the other hand, an introduction to

current-driven driver newly defined by the author is presented. As a detailed imple-

mentation of the current-driven feedback driver, two types of feedback driver, resis-

tive-feedback (RFB) driver and active-feedback (AFB) driver, are introduced and

analyzed to examine the possibility of resolving the shortcomings of existing volt-

age-driven drivers. On a more quantitative level, theoretical analyses are presented

in various aspects to support the excellence of the current-driven feedback driver. In

addition, an overview of circuit design for high-speed PAM-4 driver based on the

current-driven feedback drivers are described in Chapter 3.

In Chapter 4 presents detailed designs of two prototypes of high-speed energy-

efficient PAM-4 transmitter. The system architectures and circuit implementations

of both prototype chips fabricated in 28-nm CMOS technology are described. The


proposed PAM-4 transmitters employ current-summing 3-tap FFE and feedback in-

verter-based driver to achieve high data rate while consuming low power, which

exhibits the state-of-the-art energy efficiency. Measurement results of the two proto-

type chips for silicon verification are also presented in Chapter 4.

Chapter 5 summarizes the proposed works and concludes this thesis.

Chapter 2. Background of Multi-Level Serial Link 9

Chapter 2

Background of Multi-Level Serial

Link

2.1 Overview

As the bandwidth demand for wireline communication has rapidly been increased

to handle the increasing volume of data traffic, the next-generation I/O systems need

alternate signaling strategies such as higher-order modulation (e.g. PAM, quadrature

amplitude modulation (QAM), quadrature phase shift keying (QPSK)), and multi-

conductor signaling [17]. In addition, the future I/O systems are constrained not only

by the bandwidth limits of copper-based links and packages but also by limits on

power consumption, by limits on the size of a system, and by the need to provide a

cost-effective solution. Fig. 2.1 shows the recent trends of per-lane data rate of indu-


strial I/O standards. Note that, as you can see in the graph, I/O per-pin bandwidth of

the standards such as OIF-CEI, Ethernet, Infiniband, Fibre Channel, Peripheral

Component Interconnect Express (PCIe), and Universal Serial Bus (USB) are explo-

sively growing to double in 3 or 4 years. To deal with these dramatic data rate in-

crease, various researches on alternative electrical architecture are continuing [17].

Several candidates for the copper backplane architecture are shown in Fig. 2.2. Ar-

chitectures include standard backplane links, shorter midplane orthogonal systems,

and low-loss cabled solutions. In particular, OIF Next Generation Interconnect

Framework identifies various application spaces for next-generation systems and

areas of future work. As shown in Fig. 2.3, interconnection interfaces in a typical

system are needed for die-to-die within a package, chip-to-chip within a module,

chip-to-chip within a printed circuit board assembly (PCBA), between two PCBAs

over a backplane/ midplane, and between two chassis [18]. The detailed classificati-

0

10

20

30

40

50

60

2004 2006 2008 2010 2012 2014 2016 2018 2020

Pe

r-la

ne

Tra

ns

fer

Ra

te [

GT

/s]

0

10

20

30

40

50

60

Year

2004 2006 2008 2010 2012 2014 2016 2018 2020

: OIF-CEI

: Fiber Channel

: Infiniband

: Ethernet

: PCIe

: USB

Fig. 2.1 Trends of per-lane data rate of industrial I/O standards.


on and conditions of electrical channel published by OIF for the CEI-56G applica-

tion spaces are shown in Fig. 2.4. In order to achieve a target speed of more than 56

Gb/s in these various application spaces, many efforts have been made: development

of a high-density connector with a smaller pitch, design of a system architecture us-

ing advanced modulation, and improvement of an I/O system with lower loss [18].

Fig. 2.2 Possible candidates of electrical copper backplane architecture.

Fig. 2.3 Next-generation interconnect Application Spaces.


Especially, among modulation techniques, PAM-4 signaling is widely used for the

CEI-56G standard of very short-, medium-, and long-reach to support baud rates (i.e.

symbol rates) from 18 Gbaud to 29 Gbaud.

In the following chapter, we will describe the basics of multi-level signaling to see

why these multi-level serial links are widely used in industry. After that, we will

introduce what circuit techniques are used to implement the PAM-4 transceiver as

part of a review of prior works.

Chip Optics

Chip PluggableOptics

Chip Chip

Chip Chip

Chip to Nearby OE

Chip-to-Module

Chip-to-Chip & Midplane

Backplane or Passive Copper Cable

CEI-56G-LR

CEI-56G-MR

CEI-56G-VSR

CEI-56G-XSR

3D Stack

CEI-56G-USR

2.5D Chip-to-OE

Ultra short reach

Extra short reach

Very short reach

Medium reach

Long reach

USR: 2.5D/3D applications- 1 cm, no connectors, no packages

XSR: Chip to nearby optics engine- 5 cm, no connectors- 5-10 dB loss @ 28 GHz

VSR: Chip-to-module- 10 cm, 1 connector- 10-20 dB loss @ 28 GHz

MR: Chip-to-chip and midrange backplane

- 50 cm, 1 connector- 15-25 dB loss @ 14 GHz- 20-50 dB loss @ 28 GHz

LR: Chip-to-chip over backplane- 100 cm, 2 connectors- 35 dB loss @ 14 GHz

Fig. 2.4 Classification and conditions of link for CEI-56G application spaces.


2.2 Basics of Multi-Level Signaling

In this section, we examine basic terms and knowledge about multi-level signal-

ing, especially PAM-4 signaling. The pulse-amplitude modulation, equivalent to

multi-level modulation, is one of the formerly known data modulation techniques in

the field of communications. The principle of multi-level signaling is to use a larger

alphabet of M levels of symbol to represent data, so that each symbol can represent

more than one bit of data. As a result, the number of symbols that need to be trans-

mitted is less than the number of bits (the symbol rate is less than the bit rate), hence

the bandwidth is compressed [20]. Fig. 2.5 shows an example for a four-level

scheme with using linear coding instead of Gray coding. In a binary digital wave-

form, each symbol represents one bit of data. On the other hand, in a PAM-4 signal,

two consecutive bits combine to form a symbol, so data is transmitted even at half

0

0

1 1 1 0

0

1

00 10 11 01

M = 2

M = 4

V

V/3

Fig. 2.5 Binary (PAM-2) and multi-level signaling (PAM-4).


the symbol rate to obtain the same data rate, as you can see from Fig. 2.5. In particu-

lar, among the two consecutive bits constituting a PAM-4 symbol, the first bit is re-

ferred as the MSB, and the latter bit is referred as the LSB.

The bandwidth required for transmission of non-return-to-zero (NRZ) data may

be larger than for transmission of PAM-4 data. For a channel and I/O circuit of

bandwidth equal to BW (Hz) the maximum symbol rate (i.e. baud rate) is given by,

2SR BW (2.1)

symbols per second. At this time, NRZ format can transmit data at bit rate of maxi-

mum SR , but PAM-M format can transmit data at bit rate of maximum SM R . Of

course, considering the degradation of SNR, PAM-M may not be able to achieve

this high data rate. If M is the number of distinct signal levels, then each symbol

now carries 2logN M bits of information, and the overall data rate rises to

2

logSR M . (2.2)

No additional bandwidth is required for this increase. The increased information rate

comes either at the expense of added transmitter power or an increased error rate at

the receiver. In addition, the multi-level signaling scheme is more sensitive to the

non-linearity and noise than the binary scheme.

Now, let us represent discrete random sequences and examine the spectrum of

them. For a general pulse ( )bTh t , NRZ and PAM-4 sequences after the pulse-

shaping filter are expressed as follows:

,( ) ( )bNRZ NRZ k T b

k

x t b h t kT (2.3)

4 4,( ) ( )bPAM PAM k T b

k

x t b h t kT (2.4)


where , 1NRZ kb and 4, 1, 3PAM kb and bT denotes the symbol duration

[21]. If the Fourier transform of ( )bTh t , ,NRZ kb , and 4,PAM kb are ( )

bTH f ,

, 4 ( )B PAMS f , and , 4 ( )B PAMS f respectively, then the power spectral density of the

NRZ and the PAM-4 signal are derived as

2 2 ( 2 )

, , ,

1( ) ( ) ( ) ( ) ( ) b

b b

j fkTX NRZ T B NRZ T B NRZ

b k

S f H f S f H f R k eT

(2.5)

2 2 ( 2 )

, 4 , 4 , 4

1( ) ( ) ( ) ( ) ( ) b

b b

j fkTX PAM T B PAM T B PAM

b k

S f H f S f H f R k eT

(2.6)

where ,B NRZR and , 4B PAMR denote the auto-correlation functions of stationary

random sequences ,NRZ kb and 4,PAM kb .

If ( )bTh t is a rectangular pulse with magnitude A and duration bT , then nor-

malized power spectral density of the NRZ and the PAM-4 signal can be written as

2, ( ) sin ( )X NRZ b bS f T c fT (2.7)

2, 4 ( ) sin (2 )X PAM b bS f T c fT . (2.8)

Note that 2sin ( )bc fT in , ( )X NRZS f vanishes to zero when the frequency is an

integer multiple of the baud rate ( 1/ bT ) while , 4 ( )X PAMS f vanishes to zero when

the frequency is a multiple of the half of baud rate. As a result, the normalized pow-

er spectral density of the PAM-M data (M=2, 4, 8, 16) with linear scale and loga-

rithmic scale are calculated, as shown in Fig. 2.6. The PAM-4 only requires half of

the bandwidth of that of the NRZ as can be seen from their power spectral density

curves (NRZ: black, PAM-4: red), while it increases the complexity of the receiver

to a two-bit ADC, which is usually implemented with three comparators [22]. For


(a)

(b)

Fig. 2.6 Normalized power spectral density of NRZ, PAM-4, PAM-8 and PAM-16 data

with (a) linear scale and (b) logarithmic scale.

0 0.5 1 1.5 2 2.5 3

Frequency / Baud Rate

0

0.2

0.4

0.6

0.8

1NRZ

PAM-4

PAM-8

PAM-16


example, for the same data throughput of 56 Gb/s, NRZ and PAM-4 have different

baud rate (NRZ: 56 Gsym/s, PAM-4: 28 Gsym/s) and Nyquist frequency (NRZ: 28

GHz, PAM-4: 14 GHz). As you can guess from the Fig. 2.6, PAM-M signal has a

baud rate of only 21 / log M compared to NRZ at the same data rate.

Fig. 2.7 illustrates the basic eye diagrams of the NRZ and the PAM-4 waveforms.

Vertical eye opening for PAM-4 signal is 1 / 3 of that of NRZ, thus intrinsic SNR

loss of using PAM-4 signaling compared with NRZ signaling is given by,

1

20 log 9.5 ( )3

dB . (2.9)

If with using PAM-M signaling, the intrinsic SNR degradation is derived as

1

20 log ( )dBM

. (2.10)

In practice, there is further degradation due to nonlinearity, thus considerable SNR

degradation of > 11 dB should be taken into account to design PAM-4 serial link.

After all, if the difference between the channel loss at the Nyquist frequency and a

half of Nyquist frequency is greater than 9.5 dB, then using PAM-4 signaling may

(a) (b)

Fig. 2.7 Basic eye diagrams of (a) NRZ and (b) PAM-4 signal.


benefit the entire link rather than using NRZ. Meanwhile, although the Nyquist fre-

quency is half for PAM-4 than for NRZ, in reality the real horizontal eye opening is

only between 1 / 2 unit interval (UI) and 2 / 3 UI, less than 1 UI, as shown in Fig.

2.7(b). In addition, the middle eye in a PAM-4 signal is almost symmetrical, but the

top and bottom eye are not symmetrical [10]. As shown in Fig. 2.7(b), horizontal eye

openings of the top and bottom eye are slightly narrower compared with that of

middle eye. If nonlinearity exists, this difference will be even greater.

As mentioned earlier, non-linearity has a greater impact on PAM-4 signal than

NRZ signal. PAM-4 waveform has three vertical eyes, but system margin bottleneck

lies with the worst eye. Therefore, adjusting the vertical eye of a transmitted PAM-4

signal to equal height is a very important issue in terms of the overall link system

including the receiver side, and several parameters for measuring the degree of non-

linearity are defined. First, the level separation mismatch ratio, LMR indicates the

vertical linearity of the signal. Fig. 2.8 shows the transmitter linearity test pattern,

0

VB

VC

VDTransmitter

linearitytest pattern

Time [UI]

20 40 60 80 100 120 140 160

VA

Fig. 2.8 Linearity test pattern for PAM-4 transmitter.


which could be used for testing 400 Gigabit Ethernet (GbE) [23], [24]. In the test

pattern shown in Fig. 2.8, each level is sustained for 16 UI. The levels { AV , BV ,

CV , DV } are given by the average value of the voltages over the center 2 UI of each

16 UI symbols. The effective symbol separations are given by:

1B avg

A avg

V VES

V V

(2.11)

2C avg

D avg

V VES

V V

(2.12)

where the average voltage is given by the average of the four symbol voltage meas-

urements, 1 ( )4 A B C DV V V V . The ideal symbol separations are as follows:

1 2 1 / 3ES ES . (2.13)

One of the PAM-4’s complications is the possibility of amplitude compression: the

variation in the voltage (or power) swing between adjacent symbols. One way to

measure voltage compression is to define the minimum signal level, MINS , as half

of the swing between the closest adjacent symbols [23]:

1

min( , , )2

MIN B A C B D CS V V V V V V . (2.14)

So that the level separation mismatch ratio can be expressed as

6 MIN

LMD A

SR

V V

. (2.15)

A linear PAM-4 transmitter should satisfy 0.92LMR according to the 100 GbE

PAM-4 spec (100GBASE-KP4) [24].

Another way to measure the symbol levels is to extract them from a PAM-4 eye

diagram, as shown in Fig. 2.9. First, define a 1 4 UI horizontal mask through the


center of the middle eye. Then project histograms of the three symbols. The symbol

levels { 0V , 1V , 2V , 3V } are given by the mean of the corresponding histograms, as

shown in Fig. 2.9. { AV , BV , CV , DV } may be pretty close to { 0V , 1V , 2V , 3V },

but the histograms, especially the top and bottom, are likely to be asymmetric. Thus,

it’s unreasonable to expect the two sets of symbol levels to be the same.

By defining the symbol separations as 1 0lowAV V V , 2 1midAV V V , and

3 2uppAV V V , we can also define the eye linearity as the ratio of the largest to the

smallest adjacent symbol voltage swings,

max , ,

min , ,

low mid upp

low mid upp

AV AV AVEye linearity

AV AV AV (2.16)

While the first technique, the one that use the transmitter linearity test pattern, is ap-

pealing in its simplicity, the second one can be much easier to relate the measure-

ment to symbol error rate (SER) or bit error rate (BER) by measuring symbol levels

and compression with a real eye diagram [23].

¼UI

AVupp

AVmid

AVlow

V0

V1

V2

V3

histogram

Fig. 2.9 PAM-4 symbol levels with a horizontal eye mask.


2.3 Theoretical Analysis

2.3.1 Sensitivity

The sensitivity of an electronic device, such as a communication system receiver

or detection device, is the minimum magnitude of input signal required to produce a

specified output signal having a specified SNR or other specified criteria. Unfortu-

nately, from the sensitivity standpoint, the use of multi-level signaling is disadvan-

tageous compared to NRZ due to intrinsic SNR degradation.

As mentioned before, the baud rate of M-level PAM is 21 log ( )M of that of the

NRZ at the same bit rate [25]. Thus, the use of multi-level signaling can reduce the

symbol rate for the same bit rate at the expense of the input electrical power effi-

ciency manifested through the receiver sensitivity. Under assumptions that the noise

is additive, white, and stationary, the input power penalty [dB] for using a PAM-M

compared to NRZ to reach the same BER at the same symbol rate SP , is given by,

10log 1SP M (2.17)

Where M is the number of PAM levels [26]. This means that 4.8 dB more received

electrical power is needed for PAM-4 at the same symbol rate as NRZ. The penalty

is less when the bit rate is kept fixed, because of reduced signal bandwidth [27]. The

input power penalty [dB] for PAM-M relative to NRZ at the same bit rate BP , is

2

110log

logB

MP

M

. (2.18)

Thus, 3.3 dB more received power is needed for PAM-4 at the same bit rate as NRZ.


2.3.2 Symbol Error Rate and Bit Error Rate

To calculate the theoretical BER values for PAM-M systems, we start with the

SER calculation. Consider M amplitude levels centered on zero, with 2lM . If the

PAM-M signals are represented geometrically as M one dimensional signal point

values, then the PAM-M signal can be expressed as

, 1, 2, ...,2

gm m

ES A m M (2.19)

where gE and mA denote the energy of the basic signal pulse and amplitude val-

ues [20]. The amplitude values are as follows:

2 1 , 1, 2, ...,mA m M d m M (2.20)

where the Euclidean distance between adjacent signal points is 2 22

gg

Ed d E .

The average symbol energy symE can be calculated from:

2

1 1

22

1

22

1 1

2 12

1

6

M M

sym m m

m m

Mg

m

g

E E SM M

d Em M

M

Md E

. (2.21)

Placing the symbol decision threshold levels as shown in Fig. 2.10 helps in evaluat-

ing the probability of symbol error. We note that if the M-th amplitude level is trans-


mitted, the demodulation output will be:

2

gm m

Er S n A n (2.22)

where the noise variable n follows a Gaussian distribution with zero mean and var-

iance of 202N and all amplitude levels are equally likely a priori. The average

probability of a symbol error is simply the probability that the noise variable n ex-

ceeds in magnitude one-half of the distance between adjacent levels. As a result, the

SER can be derived as follows:

2

0

2

0

0

2

2

1 1 2

2

1 2

g

g

x

g Nm

Ed

u

Ed

N

EM MSER P r S d e dx

M M N

Me du

M

. (2.23)

The complementary error function, ( )erfc x , and Q-function are defined as

Error region

Si Si+1 Si+2 Si+3

THi+1THi THi+2

Fig. 2.10 Power density function for PAM-M signal.


2

( ) 1 ( )

2 t

x

erfc x erf x

e dt

, (2.24)

2

2

2

2

1( )

2

1 2

2

1

2 2

u

x

t

x

Q x e du

e dt

xerfc

(2.25)

where ( )erf x denotes the error function. Thus, the SER can be expressed by using

of the complementary error function or Q-function as follows:

2 2

0 0

2 11

2

g gd E d EMMSER erfc Q

M N M N

. (2.26)

Then again, the SER can be re-written in terms of average symbol energy, symE

20

62 1

( 1)

symEMSER Q

M M N

. (2.27)

Because it is customary to plot the probability of symbol error to use SNR per bit

as a variable, re-deriving the SER based on SNR per bit is necessary. First, average

bit energy, bitE can be derived as

2log

symbit

EE

M (2.28)

since 2log M bits are included in a symbol for PAM-M. Then, the SER is given by,


2

20

2 1 6log

( 1)bit

M M ESER Q

M M N

(2.29)

Where 0bitE N denotes the average signal-to-noise ratio per bit [20]. Thus, the

SER is re-induced on the basis of SNR per bit. The SER of the PAM-M signal cal-

culated from (2.29) is shown in the Fig. 2.11. As shown in the Fig. 2.11, each time

the number of bits of a symbol increases by one, the SNR achieving SER of 1210

increases by 4 dB. Note that, as the number of levels increases in multi-level signal-

ing, the distances between adjacent levels become narrower and the probability of

symbol error rises.

Meanwhile, the BER is also closely related to the SER. For high SNR, it can be

assumed that only errors between adjacent symbols occur. In that case, the BER can

be approximated as follows:

Fig. 2.11 Symbol error rate for PAM-M signals.

8 10 12 14 16 18 20 22 24 26

Average SNR per bit (dB)

10-12

10-10

10-8

10-6

10-4

10-2

NRZ

PAM-4

PAM-8

PAM-16


2log

approx avg

SERBER d

M (2.30)

where avgd denotes the average Hamming distance between the labels of adjacent

symbols [27]-[29]. The average Hamming distances of PAM-M signals with using

both Gray coding and linear coding are listed in Table 2.1. Using the values in the

Table 2.1, we can recalculate the approximate value of BER as follows:

,2log

approx Gray

SERBER

M ,

2,

2

log2

1 logapprox Linear

M SERBER

M M

. (2.31)

As a result of direct calculation using the approximated BER equations in (2.31),

BER graphs can be obtained according to the average SNR per bit as shown in Fig.

2.12. As illustrated in the Fig. 2.12, it can be seen that the difference between the

approximated BERs of PAM-M signals is not large when using Gray coding and

linear coding. In this chapter, we examined how SER and BER are calculated when

using multi-level signaling. PAM-4 has the advantage of reducing the baud rate by

half at the same bit rate compared with NRZ, but the SNR penalty for obtaining the

same BER is about 4 dB.

Table 2.1 Average Hamming distance of PAM-M signals with various coding

Average HammingDistance

Gray Coding Linear Coding

avgd 1 2log2

1

M

M


(a)

(b)

Fig. 2.12 Approximated BERs of PAM-M signals with using (a) Gray coding and (b)

linear coding.

Chapter 3. Current-Driven Feedback Driver 28

Chapter 3


3.1 Overview

As the required bandwidth demand for serial link systems has aggressively been

increasing, various types of CMOS interface circuit are employed for the design of

transmitter driver. The most popular topologies for designing high-speed output

driver these days are the voltage-mode driver (e.g. SST driver) and current-mode

driver (e.g. CML driver). Equivalent circuits of the voltage- and current-mode driver

are shown in Fig. 3.1. As shown in Fig. 3.1(a), a voltage-mode driver basically con-

sists of a voltage-controlled voltage source (VCVS) with series termination re-

sistance, 0R . On the other hand, a current-mode driver is equivalent with a voltage-

controlled current source (VCCS) with parallel termination resistance, 0R , as illus-

trated in Fig. 3.1(b). VCVS and VCCS can be regarded as a voltage amplifier with a


voltage gain of 0 OUT INA V V , and a transconductance amplifier with a trans-

conductance gain of m OUT ING I V , respectively. Because output impedance of

an ideal VCVS and VCCS are zero and infinite [30], respectively, the equivalent

circuits in Fig. 3.1 have same output impedance of 0R .

In Fig. 3.1, you can easily notice that both the voltage-mode and current-mode

drivers are driven by an input voltage, usually a digital data stream, regardless of the

type of both driver’s output. This is the reason why I want to classify and redefine

the conventional drivers represented by the voltage-mode and current-mode drivers

as voltage-driven drivers. From this thesis, the following chapters introduce what

inherent limitations voltage-driven drivers have and present how these problems can

be mitigated by using the proposed current-driven feedback drivers.

Z0

VIN VOUT

A0

R0

R0Voltage-ModeOutput Driver

(a)

Z0

VIN

IOUT

Gm

R0R0Current-ModeOutput Driver

(b)

Fig. 3.1 Equivalent circuits of (a) voltage- and (b) current-mode driver.


This chapter briefly examines the structure of conventional voltage- and current-

mode drivers that can be classified as voltage-driven drivers by the author in order to

understand the features of existing structures. Then, the limitations of existing driv-

ers are listed and proposed current-driven feedback drivers to resolve the drawbacks

of the conventional drivers are introduced: RFB driver and AFB driver. Finally,

analyses for performance comparison of existing drivers with resistive-feedback

driver for various performance metrics and summarize design issues of feedback

driver applying to multi-level serial link.


3.2 Voltage-Driven Drivers

3.2.1 Basics of Conventional Drivers

On the serializing transmitter side, the most power-hungry blocks are usually

high-speed circuits: serializer, clock buffer, pre-driver, and output driver [31], [32].

Especially, as the data rate increases, the dynamic power consumed by the serializer

and pre-driver increases drastically and is greatly influenced by the structure of the

output driver. Thus, majority of efforts have focused on improving the energy effi-

ciency of the pre-driver and output driver.

As mentioned in the overview, the voltage-mode (VM) and current-mode (CM)

drivers have been widely used for wireline serializing transmitters, especially VM

drivers for low-power applications and CM drivers for high data rate applications. In

particular, VM drivers are preferred in many recent wireline transmitters due to their

low power dissipation [12], [32]-[54]. As is well known, assuming that both trans-

mitter side and receiver side are terminated (i.e. double termination) and the receiver

side is differential terminated, the VM driver dissipates only a quarter of the current

compared to the CM driver. The current levels consumed by the driver according to

the type of receiver-side termination are listed in the Table 3.1. On the other hand, in

spite of the low power consumption of the voltage-mode driver, the CM driver is

widely employed for I/O interface requiring higher speeds due to good supply rejec-

tion and inherently fast rise/fall time [14], [55]-[65]. In recent years, however, it has

been re-examined that the SST driver has good linearity by increasing the ratio of


series resistors, which is particularly beneficial for multi-level signaling. In addition

to this, the SST driver is often used again in ultra-high-speed applications with per-

pin bandwidth of above 28 Gb/s because of the advantage of having a larger swing

than the CML driver and achieving additional SNR gain [36], [46], [47], [52].

In order to understand the functions of conventional drivers and to analyze their

limitations, this section briefly reviews the structure of existing VM and CM drivers.

Firstly, simplified circuit diagrams of a conventional N-over-N and P-over-N volt-

age-mode driver are shown in Fig. 3.2 [33]. The N-over-N voltage-mode driver is

widely used for low-swing application because of its low-power design capability.

But, the pull-up or pull-down NMOS of the N-over-N driver operates in the linear

region only with a relatively small output swing. On the contrary, the P-over-N de-

sign operates in the linear region when the output swing is high. As a result, the P-

over-N driver is suitable for high output swing and has better impedance matching

performance, which makes the P-over-N driver widely used as a basic structure of a

VM driver.

One of the most important design issues when designing the VM driver is how to

adjust the output impedance of the driver. The reason why output impedance is sig-

Table 3.1 Current level consumed by the driver according to receiver-side termination

VM Single-ended Vppd / 2Z0

VM Differential Vppd / 4Z0

CM Single-ended Vppd / Z0

CM Differential Vppd / Z0

Driver RX Termination Type Current Level


DinP

DinN

VR VS

(a)

DinP

DinN

VDDPDRV VDDDRV

(b)

Fig. 3.2 Typical circuit diagram of conventional (a) N-over-N voltage-mode driver and

(b) P-over-N voltage-mode driver.


nificant in wireline transmitters is that reflection can cause signal integrity degrada-

tion if it does not match the characteristic impedance, 0Z , of the transmission line.

So a practical transmitters set their output impedance to 0Z , usually a 50 Ω.

N-over-N VM driver in Fig. 3.2(a) consists of a pre-driver and main-driver stages

whose supply voltages are RV and SV , respectively. In the main-driver stage, the

upper NMOS transistor serves as a pull-up device while the lower NMOS transistor

serves as a pull-down device, and their impedances are controlled by appropriately

regulated supply voltages, RV and SV [16]. Background impedance calibration

loops shown in Fig. 3.3 automatically adjust the impedance of the N-over-N driver

to a desired value regardless of any variations of device parameters such as tempera-

ture. Before understanding the operation of the background regulator in Fig. 3.3, let

us review the basic operation of the VM driver. The VM driver basically operates

4Z0

2Z0 4Z0

VBIAS

VSVR

Fig. 3.3 Regulators for impedance calibration of N-over-N voltage-mode driver.


like a resistive divider when considering receiver-side termination. Naturally, pull-

up and pull–down devices of the VM driver operate in a linear region in order to act

like a resistance when turned on, which are determined by the size and overdrive

voltage of the devices. Therefore, regulating supply voltages of pre-driver and main-

driver is effective in that it can directly control the overdrive voltage of pull-up and

pull-down devices. In the N-over-N VM driver in Fig. 3.2(a), the impedance of the

lower NMOS is completely controlled by adjusting the RV . On the contrary, the

impedance of the upper NMOS is affected by both RV and SV due to its varying

source voltage. As a result, in order to perform impedance calibration, the regulators

that controls the RV and the SV must be correlated rather than independent of

each other. Indeed, the RV regulator in Fig. 3.3 regulates RV to make the sum of

two on-resistance equal to 02Z assuming receiver-side differential termination. At

the same time, the SV regulator regulates SV to make a total sum of two on-

resistance and 02Z termination resistance equal to 04Z . Because these two feed-

back loops operate simultaneously in the background, the output impedance can be

set to 0Z during pull-up and pull-down periods, respectively. Furthermore, the SV

regulator also adjusts output swing of the driver.

P-over-N VM driver in Fig. 3.2(b) consists of a pre-driver and main-driver stages

whose supply voltages are PDRVVDD and DRVVDD , respectively. Unlike the N-

over-N structure, the upper PMOS transistor serves as a pull-up device while the

lower NMOS transistor serves as a pull-down device in the P-over-N structure. The

pull-up and pull-down devices of P-over-N driver depend only on DRVVDD and

PDRVVDD , respectively. Naturally, two supply regulators are dedicated to the cali-

bration of the pull-up and pull-down impedance, as shown in Fig. 3.4 [34]. Therefo-


RREF

SegmentedPull-down

Replica

RINT RINT

VDDPDRV

Segmented Switch

(a)

Segmented Switch

RCM

SegmentedPull-up Replica

RCM

RREF

IREF

VDDDRV

(b)

Fig. 3.4 (a) Pull-down regulator and (b) pull-up regulator for impedance calibration of

P-over-N voltage-mode driver.


re, the impedance calibration loop for the P-over-N driver is more intuitive than the

N-over-N driver. Fig. 3.4 shows the pull-down and pull-up regulators for impedance

calibration of the P-over-N driver. These regulators in [34] use replicas of the triple-

stacked pull-up and pull-down devices and the off-chip reference resistors for output

impedance calibration. Additional resistors, INTR and CMR , are included to mimic

the DC operating condition of the output driver in the replica circuits. The output

driver and the replicas are segmented, and the number of activated segments of the

output driver and the replicas included in the feedback loop is designed to be adjust-

able. The selector switches are implemented using CMOS inverter powered by

PDRVVDD and DRVVDD , as appropriate. When the numbers of the activated seg-

ments are changed, the regulators adjust PDRVVDD and DRVVDD , to match the

impedances of the replica and the reference resistance. As a result, P-over-N driver

in Fig. 3.2(b) can scale the internal supply voltage ( PDRVVDD ) and the output swing

( DRVVDD ) without disturbing the output impedance. In this way, the number of re-

dundant slices is minimized, and any mismatch in the pull-up and pull-down re-

sistances is naturally cancelled without manual trimming, which is not feasible to

the slice programming schemes presented in [53], [54].

Recent high-speed wireline transmitters tend to merge equalization and parallel-

ism functions into the output driver as well as impedance control. In particular, time-

multiplexing is attractive for VM drivers because it allows full CMOS implementa-

tions without using any CML buffers that operate at high speeds. Further details

about multiplexing driver is discussed in the following sections, but time-

multiplexing is also employed for ultra-high-speed CML driver [66]. Meanwhile,

pre-emphasis (PE) is a traditional method widely used to pre-compensate the chan-


nel loss in the wireline transmitter. By varying the pre-emphasis coefficient, a nor-

mally positive 1-tap post cursor can be removed as appropriate. Fig. 3.5 shows the

equivalent circuit of the voltage-mode driver when using the pre-emphasis function.

In the VM driver, the PE is actually implemented as pre-de-emphasis, which reduces

the signal level by adding an additional PE driver slice in parallel with the main

driver slice. As the output impedance is inversely proportional to the total number of

activated slices, regardless of whether these slices belong to the main tap or the pre-

emphasis tap, the pre-emphasis coefficient can be tuned without altering the output

impedance, as shown in Fig. 3.5. Because the pre-emphasis is implemented in the

form of a resistive divider [42], [49], the total admittance of the driver is the sum of

admittances from the main tap and the pre-emphasis tap. Therefore, if the replica str-

YPE Ymain = N x Yunit

YPE = M x Yunit

Ymain

out

Zout = (M+N) x Yunit

1

M: # of activated pre slices

N: # of activated main slices

Yunit: Admittance of a slices

M/(M+N): PE coefficient

Fig. 3.5 Equivalent circuit of voltage-mode driver with pre-emphasis.


ength is determined by the total number of activated slices, ( )M N in Fig. 3.5,

the output impedance is constant regardless of the magnitude of the pre-emphasis

coefficient [34]. Using this structure, a FFE compensating for more than one tap can

be implemented without altering the output impedance by adding multi-tap slices in

parallel.

VM drivers have an inherent linearity issue not seen with CM drivers. A conven-

tional way to mitigate this linearity issue is to put linearization resistors in series

with the CMOS devices, which is commonly known as SST driver. The linearity of

the VM driver improves as the ratio of the linearization resistor in the output imped-

ance increases but resulting in a larger device size and a considerable increase in

dynamic power consumption of the pre-driver. Nonetheless, since the linearity per-

formance is strictly required in practical transmitters, the SST driver is now the most

common form of VM driver used in I/O interfaces. The VM driver, including the

SST driver, must be the stacked structure of the device in order to apply the FFE or

parallelism mentioned above. However, as the number of stacks increases, both the

device size and the parasitic component increases, which causes both power and

speed problems. From this point of view, a full-rate SST driver is certainly attractive

from a power perspective, but multiple full-rate buffer stages may suffer from severe

delay variations due to noise from data supply, ISI, and various device parameters.

Therefore, half-rate or quarter-rate SST drivers are often used despite the possible

power and speed losses [12], [34]. Fig. 3.6 and Fig. 3.7 depict the speed optimiza-

tion steps of existing half-rate SST driver in [35]. The driver incorporates a stacked

MUX that is selected by a complementary half-rate clock signal (C2, C2B) and driv-

en with half-rate even (dep, den) and odd (dop, don) data streams. A variable device


C2 C2B

C2B C2

out

Dep[3:0]

Den[3:0]

Dop[3:0]

Don[3:0]

(a)

C2 C2B

C2B C2

out

Dep[3:0]

Den[3:0]

Dop[3:0]

Don[3:0]

(b)

Fig. 3.6 (a) Original stacked structure in [35] and (b) Stacked structure with single

shared linearization resistor.


width with segmented structure is used for impedance tuning of the driver. Original

stacked structure shown in Fig. 3.6(a) suffers from limited slew rate, incomplete in-

ternal node settling, and data-dependent jitter due to parasitic capacitance within the

stacked driver. On the other hand, stacked structure with single shared linearization

resistor shown in Fig. 3.6(b) since some of parasitic capacitors may become undriv-

en when a clocked transistor is turned off. In the final step of the optimization, the

clocked MUX transistors (now operating as transmission gates) are relocated be-

tween the oven/odd branches and the single shared resistor, as illustrated in Fig. 3.7.

As a result, the SST driver has effectively been transformed from a stacked MUX to

a pass-gate MUX with programmable-width inverters for the even and odd data [12].

The CML driver, a typical CM driver, is still one of the most robust and powerful

options for high-speed output drivers despite the large static power dissipation. The

typical circuit diagram of a conventional full-rate CML driver is shown in Fig. 3.8,

Don[3:0]

Dop[3:0]C2

C2B

Den[3:0]

Dep[3:0]C2B

C2

out

Fig. 3.7 Final structure with relocated clocked MUX transistors.


whose differential output swing is determined by 0TAILI R for both single-ended

and differential receiver-side termination and output common level is set as

0

1

2DRV TAILVDD I R . (3.1)

Because of pull-down only characteristics, a conventional CML driver exhibits low-

er output swing relative to a push-pull CM driver under the same power consump-

tion conditions. In addition, difference between linear passive pull-up path and non-

linear active pull-down path makes the CML driver have asymmetric rise/fall times.

Meanwhile, the CML driver is well compatible with both DC and AC coupling to-

pologies and has better impedance matching characteristic than the VM drivers

without a linearization resistor. The signaling bandwidth of the CML driver is de-

termined by the time constant of parallel termination resistor 0R and the load ca-

pacitance.

DinP

DinN

R0 R0

ITAIL

Fig. 3.8 Typical circuit diagram of a conventional CML driver.


The push-pull CM driver shown in Fig. 3.9 has been widely used in low-voltage

differential signals (LVDS) standard. Compared with the pull-down only CML driv-

er, the push-pull driver requires only half the current to achieve the same output

swing [67]. This means that for the same driver current, the push-pull driver can

double the swing compared to the CML driver. The driver current in the push-pull

driver is ideally constant, resulting in low dI dt noise. Dual current sources with a

common-mode feedback allow good power supply rejection ratio (PSRR), but volt-

age headroom issue of the push-pull CM driver can be a more severe problem in

low-voltage technologies.

DinP

DinN

VCM,ref

VBP

R0 R0

Fig. 3.9 Typical circuit diagram of a push-pull current-mode driver.


3.2.2 Drawbacks

The previous section has reviewed briefly the features of conventional voltage-

driven drivers such as VM and CM drivers that have been widely used for I/O inter-

face circuits. To sum it up, an output driver of a serializing transmitter should pos-

sess several features in terms of various performance metrics: impedance controlla-

bility for output matching, equalization compatibility for high-speed operation, par-

allelism compatibility for power and speed optimization, output swing scalability

against various receiver sensitivity and channel loss, and good linearity for N-bit

DAC applicability. However, from the point of view of these characteristics, exist-

ing voltage-driven drivers have various drawbacks and we will examine how these

drawbacks can be solved by using the proposed current-driven driver schemes.

Firstly, the output impedance of an output driver must be time-invariant, which

improves signal integrity by absorbing reflections that return at any time on the re-

ceiver side. If receiver-side termination is ideally matched properly, there is no re-

flection at all, but in reality reflection occurs inevitably due to discontinuity in the

channel and package. In addition, since the actual output driver has an impedance

variation depending on the operating region, it is important to design this impedance

perturbation as small as possible. Because the N-over-N or P-over-N VM driver

regulates the impedance based on when pull-up or pull-down path is turned on, so

the output impedance is increased to hundreds of Ohms during a transition period,

which can severely degrade signal integrity. Therefore, as shown in Fig. 3.10, a re-

flected wave distorts the edge of the incident wave when the reflected wave arrives

during a transition unfortunately [50]. How this impedance variation degrades the


matching characteristics of the output driver and how it can be improved by using

the proposed current-driven feedback driver is discussed in the next chapter. The

CM driver, on the other hand, does not have significant impedance variations due to

the nature of parallel termination.

Second, an output driver must be able to embed transmit equalization or parallel-

ism without altering the output impedance. Recently, high-speed wireline transmit-

ters have applied various equalization techniques to compensate for frequency-

dependent loss of interconnection and to guarantee receiver sampling margins by

cancelling data ISI. As shown in Fig. 3.11, to implement the FFE, a widely used

equalization technique, the VM and CM driver that are classified as voltage-driven

drivers by the author must place multi-tap slices parallel to a main-tap slice at the

output node, so inherent bandwidth degradation by parasitics of disabled slices can-

not be avoided. Due to the nature of voltage-driven drivers driven by binary data, it

is not possible to sum the voltages by the tap weights at the driver inputs, so the

Transition occured

Reflectedsignal

Ideal impedance

Reflected signal wave is absorbed

Varying impendance

Reflected wave distorts edge of the incident wave

Fig. 3.10 Signal distortion caused by varying impedance of P-over-N VM driver.


multi-tap cursors of FFE can only be combined at the pad. In other words, pre-

processing that multiplies tap weight to multi-tap cursors and add to main cursor at

Nyquist rate before the last driver stage is not feasible. Of course, if you switch from

analog to digital-based FFE and use an N-bit DAC driver, you can implement the

FFE before the driver stage even using voltage-driven drivers, but you may lower

the operation speed until the digital logic allows. Therefore, regardless of whether

DinP

DinN

VDDPDRV VDDDRVMAIN

PRE/POST

(a)

DinP

MAIN

PRE/POST

IMAIN

DinN

VDDDRV

(b)

Fig. 3.11 Simplified block diagrams of segmented voltage-driven drivers with multi-tap

FFE: (a) voltage-mode driver and (b) current-mode driver.


the FFE is implemented at the pad or at the pre-pad, the speed limitation is inevita-

ble when the voltage-driven drivers are used. The bandwidth degradation due to

slice parasitics also occurs when implementing parallelism. In contrast, thanks to the

inherent nature of current-driven driver driven by the input current, it is possible to

sum the currents by the tap coefficients and to apply it to the driver. As a result, the

FFE tap summing can be performed at the driver input rather than at the output

where a relatively large dominant pole is located, so the bandwidth degradation due

to FFE parasitics can be mitigated. Detailed quantitative analysis is covered in the

following chapters.

The multiple slice issue also occurs for impedance control of VM drivers in addi-

tion to equalization and parallelism. In general, a VM driver is assisted by back-

ground supply regulators that regulate the supply voltages of the pre-driver or driver

to control the output impedance [34]. Since the driver supply determines the output

swing, using this scheme, the output impedance and output swing have a strong cor-

relation. Naturally, to meet the output swing specification in most I/O standards, the

range of output impedance that can be controlled by the supply regulator is limited.

As a result, in recent years, hybrid impedance control scheme has been introduced

that uses slice-based coarse tuning and analog loop-based fine tuning [36]. However,

as segmentation to obtain programmable width increases hardware complexity, the

multiple slice issue becomes even more intense. In addition, to implement the N-bit

DAC driver for multi-level signaling, the speed degradation is boosted as additional

slices are required. On the other hand, thanks to the addition of input current as a

variable, the current-driven drivers can compensate for the change in output swing

when adjusting output impedance by adjusting the driver input current.


The segmented slice structure of the VM driver is not only a matter of speed loss,

but also causes problems in terms of power consumption. When a slice-selecting and

-activating switches are added in series, the device size increases as the VM driver

employs a double- or triple-stacked structure. As a result, it exponentially increases

the dynamic power dissipation of the pre-driving stages. In summary, the VM driver

must pay for the significant power and speed overhead to support essential features

such as impedance control, equalization, parallelism, and multi-level signaling. The

CM driver is no exception because it also supports the above functions by combin-

ing the driver segments at the pad.


3.2.3 Conventional PAM-4 Drivers

As the per-pin bandwidth requirements of industrial I/O standards such as OIF-

CEI, Ethernet, Infiniband, Fibre Channel, PCIE, and USB are increasing, more and

more applications are taking advantage of multi-level signaling links. Especially, the

PAM-4 signaling is widely used for various application spaces: die-to-die, chip-to-

chip, and board-to-board interconnections. To reduce the cost of upgrading the in-

frastructure, industrial standards for 56 Gb/s PAM-4 interface have been enacted

that can support legacy VSR, MR, and LR channels designed for the current 28 Gb/s

NRZ electrical interface [73]. Recently, the forecast that the next generation of wire-

line I/O standards and applications will require 100 Gb/s+ SerDes transceivers with

improved energy efficiency are prevalent [79]. PAM-4 signaling has become the

most likely candidate for next-generation ultra-high-speed I/O format as the link

performance of multi-level serial link can be significantly improved with the help of

forward error correction (FEC).

Unlike NRZ, conventional PAM-4 transmitters have separate data paths for seri-

alizing MSB and LSB stream and combines the MSB and LSB at the output stage to

generate the PAM-4 symbol. The existing high-speed PAM-4 drivers are imple-

mented using various driver topologies: SST-based PAM-4 drivers [68]-[73], CML-

based PAM-4 drivers [9], [74]-[79], and hybrid PAM-4 drivers [11]. Simplified

block diagram of SST-based PAM-4 drivers, CML-based PAM-4 drivers, and hy-

brid PAM-4 driver in [11] are shown in Fig. 3.12 and Fig. 3.13. Like the NRZ driv-

ers, the conventional VM and CM PAM-4 drivers use the parallel segmented slice

structure. Since the SST driver is basically a resistive divider, the on-resistance of


the MSB path and LSB path differs by a factor of two to generate a PAM-4 symbol.

As illustrated in Fig. 3.12(a), in the SST-based PAM-4 driver, the series lineariza-

tion resistor of the MSB slice is half of that of the LSB slice. Similarly, the CML-

MAIN

MSBP

MSBN

VDDPDRV VDDDRV

1X

1X

LSBP

LSBN

2X

2X

PRE/POST

Pseudo differential

PAM-4 Symbol

(a)

MSBP

MSBN

LSBPLSBN

MAIN

PRE/POST

2X 1X

VDDDRV

Fully differential

PAM-4 Symbol

(b)

Fig. 3.12 Simplified block diagrams of (a) SST-based PAM-4 drivers and (b) CML-

based PAM-4 drivers.


based PAM-4 driver combines the MSB and the LSB with a weight of 2:1. As

shown in Fig. 3.12(b), the tail bias current of the MSB pair is twice the current of the

LSB pair in the CML-based PAM-4 driver. Two SST-based PAM-4 drivers transmit

pseudo-differential PAM-4 symbols, while CML-based PAM-4 driver transmits ful-

ly-differential PAM-4 symbols. On the other hand, a hybrid PAM-4 driver was in-

troduced that adds an additional current-mode path to the conventional SST-based

PAM-4 driver to enhance the output swing [11], as shown in Fig. 3.13. High output

swing and low distortion are key features for high data-rate PAM-4 transmitter to

maximize SNR and preserve signal integrity.

Since existing high-speed PAM-4 transmitters are implemented using voltage-

driven drivers, they are also exposed to the common drawbacks of the voltage-

driven drivers mentioned above, which is a significant burden to the designer in im-

MAIN

MSBP

MSBN

VDDPDRV VDDDRV

1X

1X

LSBP

LSBN

2X

2X

LSBP

LSBN

MSBP

1X 2X

MSBN

MSBP

MSBN

LSBP

2X 1X

LSBN

VDDDRV VDDDRV

PRE/POST

Fig. 3.13 Simplified block diagram of hybrid PAM-4 driver in [11].


plementing an energy-efficient PAM-4 driver. Comparison of the SST-based PAM-4

drivers and the CML-based PAM-4 drivers are listed in Table 3.2. Both architectures

suffer power and bandwidth degradation due to increased slice parasitics to support

FFE or parallelism, which can be aggravated by MSB and LSB segmentation for

PAM-4 signaling.

Table 3.2 Comparison of SST-based PAM-4 drivers and CML-based PAM drivers

Pros

No driver static power

Good linearity

High output swing

Cons

Large pre-driver dynamic power

Power-hungry multi-tap FFE

Low FFE programmability

BW limits due to FFE parasitics

SST-based PAM-4 driver

Simple implementation

Relatively high BW

High FFE programmability

Large driver static power

Less linearity

Low output swing

Power-hungry multi-tap FFE

BW limits due to FFE parasitics

CML-based PAM-4 driver


3.3 Basic Concept

3.3.1 Resistive-Feedback (RFB) Driver

An equivalent circuit of newly defined current-driven feedback driver is illustrat-

ed in Fig. 3.14. Unlike a voltage-driven driver, a current-driven driver is driven by

the current input, so low input impedance is the key to operating as an ideal current-

voltage amplifier (i.e. transimpedance amplifier) [30]. To reduce the input imped-

ance, an output network for the current-driven driver can be configured as an ampli-

fier with a shunt-shunt feedback, as shown in Fig. 3.14. The DC transfer gains of the

main amplifier and the feedback amplifier are denoted as 0A and FA , respectively.

By employing a CMOS inverter as the main amplifier and a resistor as the feedback

amplifier, the resistive-feedback inverter-based driver, or simply a resistive-

feedback (RFB) driver, becomes the most basic form of current-driven driver. A cir-

Z0

IIN VOUT

A0

R0

R0

AF

Fig. 3.14 Equivalent circuit of current-driven feedback driver.


cuit diagram of the RFB driver and general effect of resistive feedback on transfer

function of amplifier are shown in Fig. 3.15, where FR denotes the feedback re-

sistance. Assuming a inverter as a small-signal voltage-voltage amplifier whose DC

gain and 3-dB bandwidth are 0A and 0f , respectively, resistive feedback extends

the bandwidth by a factor of ,L L totR R , where ,L totR is a parallel summation of

load resistance LR and feedback resistance FR . On the other hand, the gain is re-

duced by the same factor. As a result, by reducing the input and output impedance,

the resistive feedback allows for high-speed operation of output driver. Meanwhile,

the transimpedance gain, drvR of the RFB driver can be calculated as

0

11

1drv m F

m

R g Rg r

, (3.2)

Where mg and 0r are the sum of the transconductances and the sum of the output

resistances of the PMOS and NMOS transistors, respectively. From the equivalent

circuit in Fig. 3.14, the advantages of the resistive feedback driver are clear. In case

of the conventional VM driver, the pre-driver has to drive output stages whose input

RF

-A0, f0 gmRL,tot

gmRL

f0 f0(RL/RL,tot)

Gain

f

-20dB/dec

A0 = gmRL,tot, RF >> 1/gm, RL,tot = RL // RF

Fig. 3.15 Circuit diagram of resistive-feedback driver and general effect of resistive

feedback on transfer function of amplifier.


capacitances are generally very large. On the other hand, because the RFB driver

takes a current input, the pre-driver does not have to drive a large capacitive load,

which means that the pre-driver can be much simplified and the power dissipation

can be significantly reduced [16]. As you can see from the derived drvR in (3.2),

FR is important parameter affecting the entire driver performance. In terms of

power consumption by the pre-driver, larger FR is desirable since even a small

input current results in a large output voltage with large FR . However, smaller FR

is appropriate to meet the low-input-impedance condition for the transimpedance

amplifier, thereby the optimum value of FR can be determined by considering

overall bandwidth and swing of the output driver. Meanwhile, the input impedance

of the RFB driver, inZ is given by,

0 0 0

11 1

1F F

in outm

R RZ Z

r g r r

(3.3)

Where outZ denotes the output impedance of the RFB driver that will be derived in

following chapter 3.4.

The concept of a feedback driver operating as a transimpedance amplifier has

been adopted for high-speed CMOS crosspoint switch [80] and I/O interface appli-

cations [16], [81]. In this thesis, I redefine these feedback drivers as current-driven

feedback drivers and revisit the advantages of the current-driven feedback drivers to

propose an energy-efficient PAM-4 transmitter.

Fig. 3.16 shows the typical circuit diagram of the RFB driver with supply regula-

tion. Like a pair of VM drivers, a pair of RFB drivers also transmit pseudo-

differential outputs. The pre-driver of the RFB driver can be simply configured as a


cross-coupled inverter chain as shown in Fig. 3.16, but it can be implemented as a

combination of a current bias to further regulate the driver input current. As a simple

example, you can configure the pre-driver of the RFB driver in two types: a current-

starved inverter-based pre-driver for controlling a current bias (type 1) and an in-

verter-based pre-driver with series resistors for improving the linearity of the pre-

driver current (type 2). By employing these two types of pre-drivers, you can im-

plement RFB inverter-based PAM-4 drivers as shown in Fig. 3.17. In the type-1 cur-

rent-starved inverter-based pre-driver, the current bias of the MSB branch is twice

the current of the LSB branch and the two currents are combined to supply a single

PAM-4 symbol of current to the driver. Similarly, in the type-2 inverter-based pre-

driver, the series linearization resistor of the MSB slice is half of that of the LSB

slice to supply twice the current.

DinP

DinN

VDDPDRV VDDDRV

RF RF

Fig. 3.16 Typical circuit diagram of resistive-feedback driver with supply regulation.


MAIN

MSBP LSBP

VDDPDRV

1X2X

1X2X

MSBN LSBN

VDDPDRV

1X2X

1X2X

PRE/POST

RF

RF

(a)

MAIN

MSBP

MSBN

VDDPDRV

1X

1X

LSBP

LSBN

2X

2X

PRE/POST

RF

RF

(b)

Fig. 3.17 Simplified block diagrams of RFB inverter-based PAM-4 drivers with (a) type-

1 pre-driver and (b) type-2 pre-driver.


3.3.2 Active-Feedback (AFB) Driver

In current-driven feedback drivers, passive resistors are not the only ones that can

be used as feedback amplifiers. It is feasible to use a transfer gate pair consisting of

PMOS and NMOS transistors as shunt-shunt feedback devices with a similar effect

on resistance. To the best of the author’s knowledge, a feedback driver using trans-

fer gate as feedback amplifier was first introduced in [80] to implement a speed-

enhanced output buffer stage of CMOS crosspoint switch. I redefine this type of

driver an active-feedback inverter-based driver, or simply an active-feedback (AFB)

driver, because it is opposed to the RFB driver in that it uses active transistors rather

than a passive resistor. Two equivalent circuit diagrams of the active-feedback driv-

er are illustrated in Fig. 3.18. The gate voltages of PMOS and NMOS pass gates can

also be design variables, but they are fixed to the ground and supply voltage of the

driver, respectively, for convenience. One of the advantages of the RFB driver is

=

Fig. 3.18 Two equivalent circuit diagrams of active-feedback driver.


that output impedance, outZ , is independent of the feedback resistance, FR , and

depends only on the transistor parameters. In general, since 01 r is negligible com-

pared to mg when a transistor operates in the saturation region, the output imped-

ance of the RFB driver, outZ can be approximated as

0

1 1

1out

m m

Zg r g

. (3.4)

If mg is designed to have fixed value of 01 Z , outZ can be constant with a value

of 0Z , which makes the RFB driver a good output driver in terms of impedance

matching. However, due to the fundamental assumption of this calculation that both

PMOS and NMOS operate in saturation region, (3.4) fits well at the DC operating

point near the switching threshold of the feedback inverter. Therefore, even if the

RFB driver is designed so that the output impedance at the equilibrium point is 0Z ,

outZ is distorted from 0Z as the input current increases. Assuming the input cur-

rent of the RFB driver of positive value, the operating regions of the PMOS and

NMOS of the driver according to the output swing are shown in the Table 3.3.

Table 3.3 Operating regions of the transistors of RFB driver according to output swing

Deep-linear

Cut-off

Linear

Saturation

NMOS Saturation

PMOS Saturation

Low Swing

Middle Swing

High Swing


On the other hand, the output impedance of the AFB driver is slightly different

because it uses active feedback instead of a fixed passive resistor. Fig 3.19 and Fig.

3.20 show the small-signal equivalent circuits for output impedance calculation of

the active-feedback driver with a positive and negative input bias, respectively. mpg ,

r0p' || r0n'

gmp' vin ‒ gmn' vout

(gmp + gmn) vin

r0p || r0n

voutvin

ioutopen

Fig. 3.19 Small-signal equivalent circuit for output impedance calculation of active-

feedback driver with a positive input bias (i.e. 0INI ).

r0p' || r0n'

gmn' vin ‒ gmp' vout

(gmp + gmn) vin

r0p || r0n

voutvin

ioutopen

Fig. 3.20 Small-signal equivalent circuit for output impedance calculation of active-

feedback driver with a negative input bias (i.e. 0INI ).


mng , 0 pr , and 0nr are the transconductances and the output resistances of the tran-

sistors in the main amplifier (i.e. inverter) of the AFB driver, while 'mpg , 'mng ,

0 'pr , and 0 'nr denote the transconductances and the output resistances of the tran-

sistors in the feedback amplifier (i.e. transfer gate pair). Firstly, applying Kirch-

hoff’s current law (KCL) to the small-signal equivalent circuit of the AFB driver

under a positive input bias condition in Fig. 3.19 yields the following two equations:

0 0 0 0

1 1' '

'|| ' '|| 'mp in mn out

p n p n

g v g vr r r r

, (3.5)

0 0'|| '

outmp mn in out

p n

vg g v i

r r . (3.6)

Solving (3.5) and (3.6) gives a relation between inv and outv as

0 0

0 0

1 ' ' || '

1 ' ' || '

mn p n

in out

mp p n

g r rv v

g r r

. (3.7)

By defining proportional constant K and substituting (3.7) into (3.6), the output im-

pedance outZ can be derived as follows:

in outv K v , (3.8)

0 0

0 0

1 ' ' || '

1 ' ' || '

mn p n

mp p n

g r rK

g r r

, (3.9)

0 0

1 1

1

||

outout

out m ds

mp mnp n

vZ

i K g gK g g

r r

, (3.10)

where the entire transconductance and conductance of the inverter are defined as

m mp mng g g and 0 01 1ds dsp dsn p ng g g r r .

Meanwhile, assuming 0 01 ' || 'p nr r is negligibly small compared to 'mpg


and 'mng , the proportional constant K and outZ can be approximated as

'

'mn

mp

gK

g , (3.11)

' '1 1

' '

mp mpout

mn mp mn m mn

g gZ

g g g g g

. (3.12)

Therefore, you can easily notice that the output impedance of the AFB driver can be

approximated as the output impedance of the RFB driver, 1 mg , multiplied by

' 'mp mng g . Note that the output impedance of the AFB driver also depends only on

the transistor parameters, like the RFB driver. As a result, the AFB driver exhibits a

relatively constant output impedance when the transistor parameters are stabilized.

On the other hand, applying KCL to the small-signal equivalent circuit of the

AFB driver under a negative input bias condition in Fig. 3.20, the output impedance

outZ can be derived in same manner as before:

in outv M v , (3.13)

0 0

0 0

1 ' ' || '

1 ' ' || '

mp p n

mn p n

g r rM

g r r

, (3.14)

0 0

1

1

||

1

outout

out

mp mnp n

m ds

vZ

iM g g

r r

M g g

. (3.15)

Applying the assumptions used in (3.11) and (3.12) yields approximated outZ as


' '1 1

' 'mn mn

outmn mp mp m mp

g gZ

g g g g g

. (3.16)

Similarly, for negative input bias condition, the output impedance depends only on

the transistor parameters.

Simulated AC output impedances of the RFB and AFB driver according to the

various input bias current are shown in Fig. 3.21. For a fair comparison, both drivers

are designed to have an output impedance of 50 Ω with zero input current condition.

Both drivers show that the simulated output impedance obtained from an AC simu-

lation and the value calculated by inserting the simulated transistor parameters into

the theoretical equations derived above are actually the same. As the absolute value

of the input current becomes larger, the inverter devices fall into the linear region, so

that the output of the RFB driver gradually deviates from the ideal 50 Ω. When the

input current is swept from -2 mA to 2 mA, the maximum peak-to-peak impedance

Input Current [mA]

35

40

45

50

55

60

-2 -1 0 1 2

LinearSaturation Saturation

Resistive-feedback

Active-feedback

Ou

tpu

tp I

mp

ed

an

ce

[Ω

]

Fig. 3.21 Simulated AC output impedances of resistive-feedback and active-feedback

driver according to the various input bias current.


variation of the RFB driver is about 7 Ω. On the other hand, since the AFB driver

adds feedback devices to the inverter devices, it is necessary to consider the operat-

ing regions of the feedback devices written in blue letter. As shown in Fig. 3.21, the

feedback transistors of the AFB driver operate in the linear region under low input

current whereas they operate in the saturation region under high input current, which

results in a considerable variation in the feedback resistance [82]. Fortunately, the

output impedance is less sensitive to the feedback resistance, so the simulated im-

pedance of the AFB driver is almost constant regardless of the operating region of

the feedback devices. In fact, the peak-to-peak impedance variation of the AFB

driver at the same input current range is about 9 Ω, much like the RFB driver.

On the other hand, since the output swing of a feedback driver is proportional to

the feedback resistance, a higher output swing can be achieved when the feedback

devices operate in the saturation region. As a result, the AFB driver is significantly

enhanced in output swing owing to the larger feedback resistance under high input

current, compared to the RFB driver. Simulation results in Fig. 3.22 verify that the

output swing of the AFB driver is increased by 2.5 times over that of the RFB driver

under equivalent input current swing (2 mApp) condition. In summary, the AFB

driver employs an active transistor rather than a passive resistor as a feedback device,

which greatly improves the output swing without distortion of the output impedance

due to the effect of varying feedback resistance. This is why the AFB driver is suita-

ble for multi-level signaling transmitters in that it can improve the SNR by obtaining

enhanced output swing with less input current. The structure of the proposed active-

feedback PAM-4 driver with enhanced output swing is covered later.


Dri

ve

r O

utp

ut

[V]

0Time [ps]

15 30

-0.2

-0.1

0

0.1

0.2

2.5XIncreased

RFB AFB

Fig. 3.22 Simulated output swing comparison between resistive-feedback driver and

active-feedback driver.


3.4 Analyses and Design Issues

3.4.1 Matching Characteristic

This chapter analyzes and compares the performance of voltage-driven drivers

such as VM driver and CM driver, and current-driven feedback driver, especially

RFB driver, in various aspects. Firstly, a study of the output matching characteristics

of the two types of drivers is presented. Fig. 3.23 illustrates the situation where an

incident wave, iV , reaches the end of a transmission line with impedance, 0Z , ter-

minated in an impedance of TZ . The right side of the Fig. 3.23 gives a Thevenin-

equivalent model of the line. The impedance is 0Z , and the open circuit voltage is

twice the amplitude of the incident wave [83]. With this model, the total current

through the terminator, TI , is given by

0

2 iT

T

VI

Z Z

. (3.17)

2Vi

ZT

Z0

Vi

Z0

ZT

If Ir

IT

Fig. 3.23 Terminated transmission line and its Thevenin-equivalent model.


This terminator current is the superposition of the current due to the forward travel-

ing wave, fI , and the reverse traveling wave due to the reflection, rI . We know

that the forward current is given by 0iV Z , and thus we can solve for the reverse

current as follows:

0 0

0

0 0

2

r f T

i i

T

i T

T

I I I

V V

Z Z Z

V Z Z

Z Z Z

. (3.18)

This is the Telegrapher’s equation that relates the magnitude and phase of the inci-

dent wave to those of the reflected wave. The reflection coefficient is defined as

0

0

Tr r

f f T

Z ZI V

I V Z Z

. (3.19)

Therefore, when the terminator impedance TZ perfectly matches the line imped-

ance 0Z , the reflection coefficient becomes zero and reflection does not occur. On

the other hand, if terminator impedance does not match properly, there will be signal

loss due to reflection. Two indicators are widely used as a measure of the degree of

this signal loss due to reflection: return loss (RL) and voltage swing wave ratio

(VSWR). These two parameters are defined as follows

0

0

( ) 20 log T

T

Z ZRL dB

Z Z

, (3.20)

0

0

1 max ,

1 min ,

T

T

Z ZVSWR

Z Z

. (3.21)

This section compares the output matching characteristics of the VM driver and the


RFB driver during transient data transmission using these two parameters.

For a comparison, it is assumed that the most basic form of one-stacked VM

driver and the RFB driver are driven by a CMOS inverter-based pre-driver, respec-

tively, as shown in Fig. 3.24. All the pre-driver and main-driver stage are assumed to

have supply voltages of 1V and 2V , respectively, for convenience. A small-signal

analysis of the voltage-driven VM driver and the current-driven RFB driver yields

the following output impedances:

,

1 1out VM

dsdsp dsn

Zgg g

, (3.22)

,

1 1out RFB

m dsmp mn dsp dsn

Zg gg g g g

, (3.23)

Both drivers show that the output impedance depends only on the device parameters

V1

V2

V1

V2

(a) (b)

Fig. 3.24 Circuit diagram of (a) one-stacked VM driver and (b) RFB driver driven by a

CMOS inverter-based pre-driver.


of the transistors.

Generally, the pull-up and pull-down path of the VM driver is in the linear region

when fully turned on, so the VM driver behaves like a resistive divider considering a

termination. Naturally, the VM driver is usually designed to have ,out VMZ equal to

the characteristic impedance of the channel, 0Z , when the pull-up or pull-down

path is fully turned on. Assuming that the transistors follow the long-channel square-

law model, the conductances of the NMOS and PMOS operating in a linear region

are calculated as

nDdsn n ox GS thn

DS n

pDdsp p ox SG thp

SD p

WIg C V V

V L

WIg C V V

V L

, (3.24)

where n , oxC , nW , nL and thnV denote the carrier mobility, gate-oxide capaci-

tance per unit, channel width and length, and threshold voltage of the NMOS, and

vice versa. Thus, by substituting (3.24) into (3.22), the output impedance ,out VMZ

during pull-up or pull-down period for impedance matching can be derived as

, 0

12

1 1out VM

p nn ox thnp ox thp

np

Z ZW W

C V VC V VLL

. (3.25)

On the other hand, the RFB driver is normally designed so that the output imped-

ance, ,out RFBZ , is equal to 0Z at zero input current, where both PMOS and NMOS

operate in the saturation region, simultaneously. The conductances and transcon-

ductances of the NMOS and PMOS operating in a saturation region are calculated as


0

0

dsn

nDmn n ox GS thn

GS n

dsp

pDmp p ox SG thp

SG p

g

WIg C V V

V L

g

WIg C V V

V L

. (3.26)

By substituting (3.26) into (3.23), the output impedance ,out RFBZ at zero input cur-

rent is expressed as

,

1

1out RFB

p np ox SG thp n ox thn

p n

ZW W

C V V C V VL L

. (3.27)

If the device transconductance parameters and threshold voltage of the PMOS and

NMOS are the same (i.e. p ox p p n ox n nC W L C W L and thn thp thV V V ),

the switching threshold of the RFB driver at zero input current is set to a half of

supply voltage, 2 2V . Therefore, the output impedance matching condition for the

RFB driver can be rewrittend as

, 02

1

22

out RFBn

n ox thn

Z ZW V

C VL

. (3.28)

Note that the matching condition of the VM driver in (3.25) depends on both

supply voltages of the pre-driver and driver (i.e. 1V and 2V ), whereas the matching

condition of the RFB driver in (3.28) depends only on the driver supply voltage, 2V .

Consequently, two supply regulators must be dedicated to the calibration of the pull-

up and pull-down impedance of the VM driver, whereas only one supply regulator is


needed to calibrate the impedance of the RFB driver. Obviously, the RFB driver

saves considerable power and hardware overhead compared to the VM driver, in

that it reduces the number of on-chip regulators that consume large power and area.

Meanwhile, the real-time output impedances of the VM and RFB driver deviate

from the desired value of 0Z during data transmission because the operating region

of the driver is time-varying. To observe these impedance variations, ideal 10 Gb/s

PRBS 27-1 data shown in Fig. 3.25 are applied to the input of both pre-drivers in Fig.

3.24 and the real-time output impedances of both drivers are simulated as shown in

Fig. 3.26. To assume equivalent conditions, both drivers are designed to have the

same output swing. The simulated output impedances are obtained equal to the val-

ues calculated by substituting the time-varying transistor parameters into (3.22) and

(3.23). As expected, if both drivers exceeded the ideal operating range, the imped-

ances would deviate from the desired value, in this simulation 50 Ω. The VM driver

0

0.2

0.4

0.6

0.8

1

1.2

0 1E-10 2E-10 3E-10 4E-10 5E-10 6E-10 7E-10 8E-10

1.2

1.0

0.8

0.6

0.4

0.2

00 100 200 300 400 500 600 700 800

Vin

[V

]

Time [ps]

10 Gb/s PRBS 27-1

Fig. 3.25 Ideal 10 Gb/s PRBS 27-1 data applied to both pre-driver inputs.


has a much greater variation than the RFB driver and the impedance increases to

hundreds of ohms during data transitions, as shown in Fig. 3.26. The average values

of the real-time impedances are 70.8 Ω and 44.7 Ω, respectively. On the other hand,

0

50

100

150

200

250

300

350

400

0 1E-10 2E-10 3E-10 4E-10 5E-10 6E-10 7E-10 8E-10

400

350

300

250

200

150

100

50

0

Zo

ut,

VM [Ω

]

Time [ps]

70.8 Ω

0 100 200 300 400 500 600 700 800

(a)

35

40

45

50

55

60

65

0 1E-10 2E-10 3E-10 4E-10 5E-10 6E-10 7E-10 8E-10

65

60

55

50

45

40

35

Zo

ut,

RF

B [Ω

]

Time [ps]

44.7 Ω

0 100 200 300 400 500 600 700 800

(b)

Fig. 3.26 Simulated real-time output impedance of (a) voltage-mode driver and (b) resis-

tive-feedback driver.


by using the obtained impedances, the plot of the two parameters for estimation of

the reflection loss, RL and VSWR, are calculated as shown in Fig. 3.27. Due to in-

creased impedance, the output RL of the VM driver increases instantaneously to -3

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0 1E-10 2E-10 3E-10 4E-10 5E-10 6E-10 7E-10 8E-10

0

-10

-20

-30

-40

-50

-60

-90

-100

Ou

tpu

t R

L [

dB

]

-70

-80

0 100 200 300 400 500 600 700 800

Time [ps]

VMRFB

(a)

0

1

2

3

4

5

6

7

8

0 1E-10 2E-10 3E-10 4E-10 5E-10 6E-10 7E-10 8E-10

VMRFB

7

6

5

4

3

1

VS

WR

2

0

8

0 100 200 300 400 500 600 700 800

Time [ps]

(b)

Fig. 3.27 Calculated real-time (a) output return loss (RL) and (b) voltage swing wave

ratio (VSWR) from simulated output impedance.


dB during the data transition, whereas the RFB driver maintains the RL below -20

dB while transmitting data.

The impact of varying impedance on signal integrity is also simulated with the

same model in Fig. 3.24. Peak-to-peak jitters simulated at the driver output while

transmitting 10 Gb/s PRBS 211-1 data are shown in Fig. 3.28 through Fig. 3.30 with

various simulation conditions: varying receiver-side termination impedance of

RXTR , varying rise/fall time of the input signal, and varying supply voltage of the

driver. If the receiver-side termination is perfect, no reflection occurs, so the RXTR

variation is assumed to be +40% and -40%, respectively, for second and third simu-

lation. As shown in simulation results, you can easily notice that the peak-to-peak

jitter of the VM driver output is higher than the RFB driver under all simulation

conditions. Thus, the RFB driver is superior to the VM driver in terms of matching.

0

2

4

6

8

10

-40 -20 0 20 40

Sim

ula

ted

Jit

ter

[ps

pp]

Variation of RRXT [%]

VM

RFB

Fig. 3.28 Simulated peak-to-peak jitter with 10 Gb/s PRBS 211-1 data for varying receiv-

er-side termination impedance.


0

2

4

6

8

10

12

10 20 30 40 50

Sim

ula

ted

Jit

ter

[ps

pp]

Input Rise/Fall Time [%]

VM

RFB

Fig. 3.29 Simulated peak-to-peak jitter with 10 Gb/s PRBS 211-1 data for varying rise/fall

time of the input signal with RXTR of 70 Ω (+40%).

0

2

4

6

8

10

12

14

0.9 0.95 1 1.05 1.1

Sim

ula

ted

Jit

ter

[ps

pp]

Supply Voltage of Driver [V]

VM

RFB

Fig. 3.30 Simulated peak-to-peak jitter with 10 Gb/s PRBS 211-1 data for varying supply

voltage of driver with RXTR of 30 Ω (-40%).


3.4.2 Feed-Forward Equalization

Equalization compatibility for channel pre-compensation is an essential charac-

teristic of a high-speed serializing transmitter as well as impedance controllability

for output matching. Implementation of multi-tap FFE, the most popular approach of

transmit equalization, often causes the power and speed loss due to segmentation

and stacking in the voltage-driven drivers such as VM and CM drivers. This section

examines several methods for implementing pre-emphasis (i.e. 2-tap FFE) in the

VM driver and the RFB driver, and calculates the power consumed by the pre-driver

and driver in each topologies. Thereafter, a comparison of the equalization perfor-

mance of the two drivers in terms of output swing and power consumption is pre-

sented.

Fig. 3.31 illustrates the three topologies for implementing the pre-emphasis of a

Vdrv

Gsig

Glost Gsig

Glost

Signal path

De-emphasis path

Vout

G0 /2

Gsig

Glost Gsig

Glost

Signal path

De-emphasis path 1

Vout

G0 /2

Gshunt Gshunt

De-emphasis path 2 Vdrv

Gsig

Gsig

Vout

G0 /2

Vdrv

Vdrv Vdrv

(a) (b) (c)

Fig. 3.31 Three types of pre-de-emphasis implementation for voltage-mode driver (a)

resistive-divider-based PE, (b) channel-shunting-based PE, and (c) impedance-

modulation-based PE.


VM driver: resistive-divider-based pre-emphasis (RDPE), channel-shunting-based

pre-emphasis (CSPE), and impedance-modulation-based pre-emphasis (IMPE) [42]

that are renamed by the author.

Fig. 3.31(a) shows the conventional VM driver with a RDPE. The output signal

level is lowered by adding the de-emphasis path passing through the PE conductance

( lostG ) in parallel to the main signal path consisting of the main conductance ( sigG )

and the channel ( 0 2G ). As detailed in the Appendix, the total current consumed by

the RDPE VM driver in Fig. 3.31(a) can be expressed as

,0

1 1

4drv RDPE drv

sig lost

I VZ R R

(3.29)

where drvV and 0Z are driver supply voltage and characteristic impedance of

channel and 0 01Z G , 1sig sigR G , 1lost lostR G , and 0 1 2G G G are

assumed. The second term in (3.29) becomes zero as lostR becomes infinite and

grows as lostR becomes smaller. In other words, enabling pre-emphasis causes the

driver to consume more power due to current leaking. Meanwhile, ,drv RDPEI can be

rewritten for differential output swing, outV , as follows

2

,0

1

2out drv

drv RDPEdrv

V VI

V Z

. (3.30)

As expressed in (3.30), more current is consumed when transmitting lower signal

power which is proportional to the square of outV . Therefore, as the pre-emphasis

level increases reducing the signal level, the RDPE driver becomes poorer in effi-

ciency.

In order to mitigate this inefficiency, another approach in Fig. 3.31(b) was pro-

posed. The CSPE adds an extra channel-shunting path in parallel with the main sig-


nal path to maintain total driver current constant. The second term of (3.29) can be

eliminated by adjusting the channel shunting conductance, shuntG , appropriately.

Therefore, the total current consumed by the CSPE VM driver in Fig. 3.31(b) is giv-

en by,

,04

drvdrv CSPE

VI

Z . (3.31)

To further reduce the signaling power, the most effective method is to use IMPE,

as shown in Fig. 3.31(c). Without any help of the de-emphasis path, the output

swing outV is determined by the voltage division ratio by modulating the conduct-

ance of the main path. Since the current flowing through the channel is the driver

current, the total current consumed by the IMPE VM driver in Fig. 3.31(c) is

,02

outdrv IMPE

VI

Z . (3.32)

By multiplying the equations from (3.30) to (3.32) by the high supply voltage DDV

of the on-chip driver supply regulator, the total power consumed by each driver in

Fig. 3.31 are derived as follows:

2

,0

,0

,0

1

2

4

2

out drv DDdrv RDPE

drv

drv DDdrv CSPE

out DDdrv IMPE

V V VP

V Z

V VP

Z

V VP

Z

. (3.33)

On the other hand, for the estimation of the dynamic power dissipation of the

pre-driver, a pseudo-differential VM driver driven by the inverter chain is assumed


as shown in Fig. 3.32. The power consumption of the pre-driver can be given by [50]

2

1 12

2 4

4

pdrv L pdrv DD avg

drv drv drv pdrv DD avg

drv pdrv DD avg

P C V V f

C C C V V f

C V V f

(3.34)

where drvC , pdrvV , and avgf denote the input capacitance of the driver, the supply

voltage of the pre-driver, and the average switching frequency of input data, respec-

tively. Assuming that the channel length of PMOS and NMOS are the same (i.e.

n pL L L ), the input capacitance of the output driver can be approximated as

drv ox n p effC C W W L (3.35)

where effL denotes the sum of channel length, L , and length of overlap. Therefore,

as detailed in Appendix, the input capacitance of the RDPE VM driver can be ex-

pressed as

,0

1 1 effdrv RDPE

p drv th n pdrv th

L LC

V V ZV V

(3.36)

CdrvCdrv /2Cdrv /4

Cdrv /2Cdrv /4 Cdrv

VdrvVpdrv

Fig. 3.32 Circuit diagram of pseudo-differential VM driver driven by the inverter chain.


where all device parameters are the same as defined above. By substituting (3.36)

into (3.34), the power consumption of the pre-driver of the RDPE VM driver is

,

0

41 1 effpdrv RDPE pdrv DD avg

p drv th n pdrv th

L LP V V f

V V ZV V

. (3.37)

Thus, ,pdrv RDPEP is constant regardless of the output swing, outV .

On the other hand, in the case of CSPE VM driver, output impedance matching

condition is slightly different as

0|| ||sig lost shungR R R Z (3.38)

where shuntR denotes the shunting resistance assuming 1shunt shuntR G . By using

(3.36) and (3.38), the power consumption of the pre-driver of the CSPE VM driver

and the IMPE VM driver can be derived as

2

, ,

12

2out

pdrv CSPE pdrv RDPEdrv

VP P

V

. (3.39)

, ,out

pdrv IMPE pdrv RDPEdrv out

VP P

V V

(3.40)

By substituting the actual design parameters of 28 nm CMOS technology while

transmitting random data at 32 Gb/s , the calculated power consumption of the driv-

ers and pre-drivers of three VM drivers against normalized output swing, out drvV V ,

are obtained as shown in Fig. 3.33 and Fig. 3.34. For convenience, drvV , pdrvV , and

ddV are assumed as 1 V, 1 V, and 1.2 V, respectively. Note that the IMPE driver in

which both ,drv IMPEP and ,pdrv IMPEP are scaled according to the output swing is

the most efficient structures of pre-emphasis. The overall power consumption com-

bined with the power dissipation of the pre-driver and the driver is shown in the Fig.

3.35.


The power consumption of the pre-driver, pdrvP , has a relatively smaller value

than the power consumption of the driver, drvP , because driver structure without

any stack is assumed. Naturally, in an actual segmented stacked structure, the pdrvP

may increase with grown device size and parasitics. This analysis of the pre-empha-

0

2

4

6

8

10

12

0 0.1 0.2 0.3 0.4 0.5

RDPE

CSPE

IMPE

Pd

rv [

mW

]

Vout / Vdrv

Fig. 3.33 Comparison of driver power consumption when using three types of PE.

0

0.4

0.8

1.2

1.6

2

0 0.1 0.2 0.3 0.4 0.5

RDPE

CSPE

IMPE

Pp

drv

[m

W]

Vout / Vdrv

Fig. 3.34 Comparison of pre-driver power consumption when using three types of PE.


sis VM driver can easily be extended for a VM driver with multi-tap FFE by consid-

ering the sum of pre- and post-tap conductances as lostG .

The structures of the pre-emphasis VM drivers shown in Fig. 3.31 are commonly

implemented by adding extra paths or by modulating the main path at the output

driver stage due to the inherent nature of the voltage-driven driver. On the other

hand, in the RFB driver, pre-emphasis can be implemented by modulating the input

current supplied from the pre-driver while keeping the driver stage intact. In this

respect, the RFB driver employs a current-summing FFE structure that combines the

tap currents at the pre-driver stage, as shown in Fig. 3.36. The sum of pre- and post-

tap currents is assumed to be lostI . To derive the power consumption of the RFB

driver with a pre-emphasis, a pseudo-differential RFB driver with a DC-coupled

termination is assumed as shown in Fig. 3.37. Assuming that both PMOS and

NMOS operate in the saturation region for the linear operation of the RFB driver,

0

2

4

6

8

10

12

14

16

0 0.1 0.2 0.3 0.4 0.5

RDPE

CSPE

IMPE

Driver

Total

Pre-driver

Pd

rv, P

pd

rv, P

To

tal [

mW

]

Vout / Vdrv

Fig. 3.35 Overall power consumption of VM drivers versus normalized output swing.


the current consumed by the pseudo-differential RFB driver (whose impedance is

matched as (3.28)) versus the output swing is expresses as:

2

20,

0 0

220

0 0 0

1 1

2 2 4

1 1

2 2 4 2

drv n Fdrv RFB th n ox out

n F

drv F drv outth

F drv th drv

V W R ZI V C V

Z L R Z

V R Z V VV

Z Z R Z V V V

(3.41)

RF

Isig

Ilost

I

Vpdrv

Fig. 3.36 Current-summing FFE implementation for RFB driver.

RF RFI I

Vout

Iup

Idn

Iup

Idn

2Z0

Vdrv Vdrv

Fig. 3.37 Pseudo-differential RFB driver with DC-coupled termination.


where all device parameters are the same as defined above and the device transcon-

ductance parameters and threshold voltage of the PMOS and NMOS are the same.

Therefore, the power consumption of RFB driver can be easily derived by multiply-

ing (3.41) by the supply voltage of the supply regulator as follows

220

,0 0 0

1 1

2 2 4 2drv F drv out

drv RFB th DDF drv th drv

V R Z V VP V V

Z Z R Z V V V

.(3.42)

As derived in (3.42), the driver power consumption ,drv RFBP is proportional to the

square of normalized output swing, out drvV V , in the range in which the driver op-

erates linearly. This range is about 600 mVppd as detailed later.

On the other hand, as detailed in Appendix, the absolute value of the transimped-

ance gain of the RFB driver operating linearly is given by

0RFB FR R Z . (3.43)

As a result, when the current-summing pre-emphasis for the linear RFB driver is

configured as shown in Fig. 3.36, the differential output swing follows

0 ,maxF sig outR Z I V (3.44)

0F sig lost outR Z I I V (3.45)

where ,maxoutV denotes the maximum output swing when disabling the de-emphasis

path. Solving (3.44) and (3.35) yields the total current consumed by the pre-driver as

, ,max0

12pdrv RFB out out

F

I V VR Z

, (3.46)

which results in

, ,max0

2pdrv

pdrv RFB out outF

VP V V

R Z

. (3.47)

For linear operation with sufficient margin, the maximum output swing, ,maxoutV , of


the RFB driver is assumed to be approximately 500 mVppd. Assuming that the RFB

driver transmits 32 Gb/s data using 28 nm CMOS design parameters, similar to the

VM driver, the overall power consumption of the pre-driver and the driver is calcu-

lated as shown in the Fig. 3.38. Supply voltages are assumed to be the same as VM

driver cases. Given that RDPE is still mainly used for VM drivers due to its simple

and straightforward structure, a comparison of Fig. 3.35 and Fig. 3.38 reveals that

the RFB driver with voltage-scalable efficiency in most of output swings is more

power efficient than the VM driver. This tendency is slightly reversed due to in-

creased driver power consumption as the output swing approaches the maximum

linear swing range of 600 mVppd of the RFB driver. Nevertheless, it can be seen that

the RFB driver is well suited for low-power, low-voltage application. Therefore, an

energy-efficient multi-level signaling transmitter can be proposed by using the AFB

driver with enhanced swing instead of the RFB driver while taking advantages of the

current-driven feedback driver.

0

2

4

6

8

10

12

0 0.1 0.2 0.3 0.4 0.5

Pd

rv, P

pd

rv, P

To

tal [

mW

]

Vout / Vdrv

Driver

Total

Pre-driver

Fig. 3.38 Overall power consumption of RFB driver versus normalized output swing.


3.4.3 Linearity

One of the most important characteristics of the output driver is linearity. As the

industrial standards requiring the multi-level signaling link are widespread, the im-

portance of linearity is being increased. In general, as the output swing of the driver

increases, the operation of the devices becomes saturated and nonlinear, thereby,

there is no ideal driver to maintain linearity up to the maximum achievable swing

range (MSR), unfortunately. Naturally, the linear swing range (LSR) of the driver is

somewhat smaller than the MSR. Conventional SST- or CML-based drivers usually

improve their linearity with the help of passive elements such as resistors to over-

come the inherent nonlinearity of the transistors.

The RFB driver also suffers a nonlinearity problem because it is based on the

CMOS inverter. Fig. 3.39 shows the simulated differential output swing according to

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

-6 -4 -2 0 2 4 6

Dif

f. O

utp

ut

Sw

ing

[V

]

Diff. Input Current [mA]

Saturation Linear

LSR

Linear

Fig. 3.39 Differential output swing versus differential input current of RFB driver.


the varying differential input current of the pseudo-differential RFB driver. When

the output impedance is set to 50 Ω with zero input current, the LSR of the RFB

driver is about 600 mVppd, as illustrated in Fig. 3.39. By coincidence, the LSR is ex-

actly the same as the region where both PMOS and NMOS of the RFB driver oper-

ate in saturation mode, as indicated by the red letter in Fig. 3.39. Compared with

table 3.3, the RFB driver works linearly with relatively low output swing.

Meanwhile, the only way to extend the LSR of the RFB driver without increasing

the supply voltage or using a passive element is to lower the driving impedance to

less than 50 Ω. Simulated LSR versus the output impedance and the corresponding

VSWR to represent the reflection loss are shown in Fig. 3.40. Depending on the ap-

plication, a higher LSR can be obtained through a trade-off between the matching

characteristics of the RFB driver, as shown in Fig. 3.40.

0.5

1

1.5

2

2.5

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

20 30 40 50 60 70

Lin

ea

r S

win

g R

an

ge [

V]

Output Impedance [Ω]

VS

WR

VSWR

LSR

Fig. 3.40 Simulated linear swing range (LSR) and voltage swing wave ratio (VSWR) of

RFB driver according to output impedance.


3.4.4 Circuit Bandwidth

This section compares the circuit bandwidth of the drivers as a final analysis of

the conventional voltage-driven drivers and the current-driven driver, especially the

RFB driver. The simulated 3-dB bandwidth comparison of the pseudo-differential

VM driver, the pseudo-differential RFB driver, and the fully-differential CML-based

driver is illustrated in Fig. 3.41. An output network consisting of ideal lossless

transmission lines, bonding pad capacitances of two chips and a board, and bonding

wire inductances, shown in Fig. 3.42, is used as a channel model for the simulation.

The VM and RFB driver is driven by a CMOS inverter and the CML-based driver is

driven by a CML buffer, all with a fanout of 2. For a fair comparison, all drivers are

differentially terminated with an AC-coupling configuration and all pre-drivers and

0

5

10

15

20

0.8 0.9 1 1.1 1.2 1.3

3-d

B B

an

dw

idth

[G

Hz]

Supply Voltage [V]

RFB

CML

VM

Fig. 3.41 Circuit bandwidth comparison of voltage-mode driver, CML-based driver, and

resistive-feedback driver.


drivers have same supply voltage. All drivers are designed to have an AC output

impedance of 50 Ω under their respective conditions and to have a differential out-

put swing of about 500 mVppd under supply voltage of 1 V in 28 nm CMOS technol-

ogy. The simulation results clearly show that the RFB driver is superior to the VM

driver or the CML-based driver in terms of circuit bandwidth for all supply voltages

of the pre-driver and driver, as shown in Fig. 3.41. Although this is a preliminary

step based on simplified assumptions, this study is meaningful in that it confirms

that the current-driven feedback driver has a remarkable potential as an I/O interface

circuit in high-speed link applications. In addition, design issues addressed in this

thesis provide a guideline for designing energy-efficient high-speed transmitters us-

ing current-driven feedback drivers.

LBW

LBW

LBW

LBW

CPAD

CPAD

CPCB

CPCB

CPAD

CPAD

RRXT

RRXT

LBW = 1 nH, CPAD = CPCB = 100 fF, RRXT = 50 Ω

DrvP

Z0DrvN

Vout

Z0

Chip 1 Chip 2PCB Board

PdrvP

PdrvP

CPCB

CPCB

Fig. 3.42 Channel model for bandwidth comparison simulation.

Chapter 4. Low-Power High-Speed PAM-4 Transmitter 90

Chapter 4

Low-Power High-Speed PAM-4

Transmitter

4.1 Overview

As the bandwidth demand for chip-to-chip communication is rapidly being in-

creased, multi-level signaling (e.g. PAM-4 signaling) has become a promising can-

didate for the next generation high-bandwidth I/O interface. To meet the require-

ments of the standards such as OIF CEI-56G, various FFE techniques are employed

in reported PAM-4 transmitters [9], [11], [68]-[79]. In addition to compensating for

channel loss by using an equalizer, achieving a good energy efficiency is also a cru-

cial issue for the next generation I/O systems. However, recent PAM-4 transmitters

often neglect improving the energy efficiency of the PAM-4 output driver and the


corresponding pre-driver stages, as they employ conventional driver topologies. Fig.

4.1 illustrates the trends of recently reported PAM-4 transmitters in [9], [11], [69]-

[79], [82] by normalizing their energy efficiency into 28 nm CMOS technology us-

ing a scaling factor (1 S ). Conventional PAM-4 transmitters based on a current-

mode (CM) driver [9], [74]-[79] and a source-series terminated (SST) driver [68]-

[73] have shown only limited energy efficiency due to their power-hungry pre-driver

and multi-tap FFE structure.

On the other hand, a Gm-regulated resistive-feedback driver, employed in the au-

thor’s first prototype PAM-4 transmitter [31], is a good candidate for the energy-

efficient PAM-4 driver thanks to its extremely light current-summing FFE at the

output of the pre-driver. However, due to the tap delay generator operating at the

0

1

2

3

4

5

6

7

8

9

20 30 40 50 60 70 80 90 100 110 120

No

rmalized

En

erg

yE

ffic

ien

cy [

pJ/b

]

0

1

2

3

4

5

6

7

8

9

020 30 40 50 60 70 80

* Energy efficiency including the PLL power

90

Data Rate [Gb/s]

: SST

: AFB

: CML

: SST + CML

100 110 120

This work*ISSCC '18

ISSCC '15*

ISSCC '16

ISSCC '15*

JSSC '15*

ISSCC '17

JSSC '17

ISSCC '17

ISSCC '18

ISSCC '17

ISSCC '18

ISSCC '18

ISSCC '18

High Data Rate

Low Power

Fig. 4.1 Trends of normalized energy efficiency of recently reported PAM-4 transmitters

in [9], [11], [69]-[79], [82] versus per-pin data rate.


baud rate, the transmitter in [31] has limited bandwidth and energy efficiency.

Moreover, the linear resistive feedback also limits the output swing.

To improve both the energy efficiency and the operating speed of the first version,

the FFE tap generation is merged into the serializer in the second transmitter. The

output swing of the PAM-4 transmitter in [82] is considerably enhanced by replac-

ing the resistive-feedback (RFB) driver with the active-feedback (AFB) driver. As a

result, a prototype PAM-4 transmitter with 3-tap FFE and Gm-regulated AFB driver

achieves the data rate of 64 Gb/s while consuming 97.2 mW, which exhibits the

state-of-the-art energy efficiency of 1.5 pJ/b.


4.2 System Architecture

Two prototype chips were fabricated in 28 nm CMOS technology to validate the

advantages of the current-driven feedback driver and to apply it to low-power high-

speed PAM-4 transmitter implementations: a PAM-4 transmitter with a fractionally

spaced 3-tap FFE and a Gm-regulated RFB driver [31] (prototype 1) and a PAM-4

transmitter with a 3-tap FFE and a Gm-regulated AFB driver [82] (prototype 2).

Overall architectures of two PAM-4 transmitters are shown in Fig. 4.2. As shown

in Fig. 4.2, both prototype transmitters incorporate a phase-locked loop (PLL) for

half-rate clock generation, pre-drivers with FFE summer, and a Gm calibration cir-

cuit for impedance control, in common. A 3rd-order charge-pump PLL employs a

two-stage ring oscillator to generate the half-rate transmitter clock and AC-coupled

level-shifting clock buffers are used for duty cycle correction. The major differences

between the two prototype PAM-4 transmitters are the implementations of the inter-

nal random data generation, the serializing data path with FFE tap generation, and

the output driver stage. In addition, there is a slight difference between two transmit-

ters in that the prototype 2 improves the bandwidth or stability of PLL and Gm cali-

bration circuit over the prototype 1. In the prototype 1, an internal PRBS-7 generator

and an 8-to-2 serializer are employed for the MSB and LSB data generation, while

the prototype 2 employs two on-die PRBS-7 generators synchronized to independent

reset signals and separate data paths for the MSB and LSB data for increasing the

randomness of the PAM-4 pattern. Furthermore, to make the FFE tap delay, the pro-

totype 1 incorporates a sub-UI tap delay generator with tunable latches, but the pro-


Half-rate Clock GEN.

222 DRVs

drvoutp

drvoutn

Pseudo-Diff.RFB driver

VDRV

PDRVs

drvinn

drvinp

PRE-Tap

MAIN -Tap

POST -Tap

PRE-Tap

MAIN -Tap

POST -Tap

MSBLSB

V/I Converter

V/I Converter

MSBLSB

222

PRBS GEN. + Tap GEN. + Serializer

CPPFD

upb

dn 2-stage Ring VCO

REF

/2

Constant-Gm Bias GeneratorRTRIM

Regulator

HVDD

Gm Calibration

VDRV

/8 or /16Delay

Delay

8:4SER

4:2SER

4 2PRBS GEN( )2 - 17

8

2

2

S/DConverter

MSB, LSB

Level Shifter, DCC

(a)

Half-rate Clock GEN.

2 22 DRVs

drvoutp

drvoutnVDRV

PDRVs

drvinn

drvinp

PRE-Tap

MAIN -Tap

POST -Tap

PRE-Tap

MAIN -Tap

POST -Tap

MSBLSB

V/I Converter

V/I Converter

MSBLSB

2 22

4:2SER

2

2 - 17

4

PRBS GEN. + Tap GEN. + Serializer

CPPFD

upb

dn 2-stage Ring VCO

REF

/2

Constant-Gm Bias GeneratorRTRIM

Regulator

HVDD

Gm Calibration

VDRV

PRBS GEN( )

2 - 17PRBS GEN

( )

2:1SERs

3-TapGEN

2

2

2

S/D

4:2SER

2 2:1SERs

3-TapGEN

2

2

2

4

MSB

LSB

S/D

3

3

3

3

3

3

RSTM

RSTL

/8 or /16

Level Shifter, DCC

Pseudo-Diff.AFB driver

(b)

Fig. 4.2 Overall architecture of two prototype PAM-4 transmitters (a) PAM-4 transmitter

with fractionally spaced 3-tap FFE and Gm-regulated RFB driver (prototype 1) and (b)

PAM-4 transmitter with 3-tap FFE and Gm-regulated AFB driver (prototype 2).


totype 2 merges FFE tap delay generation into the serializer to remove the power-

and bandwidth-hungry delay generator. Finally, the prototype 1 uses the RFB driver

as an output driver stage, while the prototype 2 employs the AFB driver as an output

driver stage to enhance the output voltage swing significantly with similar current

consumption.


4.3 Circuit Implementation

4.3.1 Front-End with Current-Summing FFE

In previous PAM-4 transmitters, the circuit and bandwidth overhead for imple-

menting a multi-tap FFE is a critical issue. Generally, a dominant pole is located at

the output node of the driver because of the parasitic elements of I/O pads, bonding

wires, or solder bumps. However, to implement FFE with the conventional voltage-

driven drivers mentioned earlier, additional shunt driver slices must be added at the

output node, which causes a significant increase in the parasitic capacitance. To

overcome this issue, the PAM-4 transmitter can be implemented using the current-

driven feedback driver such as the RFB driver or AFB driver, as described in Fig.

4.3. Owing to the current-driven operation of the driver, a 3-tap FFE is implemented

ILSB,DNAF

ILSB,UP

IMSB,DN

IMSB,UP

PRE

MAIN

POST

2x 1x

VDD

Gm Reg.

VDRV

ZOUT

RFB or AFB Driver

Fig. 4.3 Conceptual diagram of PAM-4 driver based on current-driven feedback driver.


simply by summing the currents of the pre-driver slices at the input node, instead of

the output node, of the driver. As a result, the proposed structure resolves the issue

of bandwidth degradation due to the FFE slices and therefore it achieves a higher

bandwidth compared with the conventional SST driver. Each tap branch of the pre-

driver is composed of two independent slices with weights of 2x, and 1x, which are

driven by an MSB and an LSB, respectively, to make a PAM-4 signal packet at the

baud rate. Meanwhile, the output impedance of the PAM-4 driver in Fig. 4.3 can be

controlled as constant by regulating transconductance, mG , of the feedback inverter,

as shown in Fig. 4.3.

Fig. 4.4 shows the detailed circuit implementation of the RFB PAM-4 driver in

prototype 1 and its corresponding current-summing pre-driver for 3-tap FFE imple-

mentation. Each tap slice of the pre-driver consists of a 5-bit controlled current bias,

data-driven switches, and data-feedthrough compensation (DFC). DFC transistors

are only included in pre- and post-tap slices. To compensate the data feedthrough,

the DFC transistor provides additional current with negative polarity to the tap cur-

RF

LSBMSB

Main VDRV

IM,PRE

IM,PRE

DMSB[n+1]

PDRV cell

2X

DbMSB[n+1]

DbMSB[n+1]

IBIAS,DN

IBIAS,UP

DFC

PrePost

IM,PRE

IM,PRE

DMSB[n+1]

PDRV cell

2X

IBIAS,DN

IBIAS,UP

Fig. 4.4 Circuit diagram of RFB PAM-4 driver in prototype 1 with current-summing pre-

driver for 3-tap FFE implementation.


rent. Fig. 4.5 shows the simulated PAM-4 eye diagrams of the driver output for var-

ious DFC cell sizes. As shown in the figure, the optimum size of the DFC transistor

is half of that of the main switch.

On the other hand, Fig. 4.6 illustrates the block diagram of the AFB PAM-4

transmitter front-end in prototype 2. The pre-driver is composed of a voltage-to-

current converter to flow current into the output driver and divided into two major

slices (MSB, LSB). Like the prototype 1, the 3-tap FFE is implemented by summing

the tap currents at the input node of the driver rather than at the output node unlike a

conventional driver, whereby a significant current is saved. The current bias of the

pre-driver is controlled by a simple feedback loop, as shown in Fig. 4.7. The AFB

output driver operates as a transimpedance amplifier and a mG calibration circuit is

used for PVT-invariant impedance control of the driver. The target mG value of the

driver is adjusted by trimming RREF.

0 20 40 60 80

0

0.05

0.1

0.15

-0.05

-0.1

-0.15

0 20 40 60 80

0

0.05

0.1

0.15

-0.05

-0.1

-0.15

Time [ps] Time [ps]

Vo

ltag

e [

V]

Vo

ltag

e [

V]

DFC : 2X DFC : 0.5X

Fig. 4.5 Simulated PAM-4 eye output with various cell size of data-feedthrough com-

pensation (DFC).


IL,MAIN

IL,MAIN

BIAS_L,MAIN

Bias Generator

DN,LSB[n]

PDRV cell

MainPre

Post

IM,MAIN

IM,MAIN

BIAS_M,MAIN

Bias Generator

DMSB[n]

PDRV cell

LSB

Active-Feedback Inverter-BasedOutput Driver

VDRV

Pre-driver (V-to-I Converter)

2X

1X

MSB

VSS

DN,MSB[n]

DN,MSB[n+1]

DN,MSB[n-1]

DN,OUT

DP,OUT

DP,MSB[n]

DP,MSB[n+1]

DP,MSB[n-1]

VDRV

Gm Calibration(Impedance Control)

RREF

CBYPASS

VREG

HVDD HVDD

HVDD

2X1X

20W/L

W/LW/L

DN,LSB[n]

DN,LSB[n+1]

DN,LSB[n-1]

DP,LSB[n]

DP,LSB[n+1]

DP,LSB[n-1]

MainPre

Post

Fig. 4.6 Block diagram of AFB PAM-4 transmitter front-end in prototype 2 consisting of

AFB PAM-4 driver, pre-driver, and Gm calibration circuits.

IM,MAIN

IM,MAIN

BIAS_M,MAIN

Bias Generator

DMSB[n]

PDRV cell

MSB

MainPre

Post

VDRVLSB

2X

Fig. 4.7 Circuit diagram of AFB PAM-4 driver in prototype 2 with current-summing pre-

driver for 3-tap FFE implementation.


4.3.2 Gm Calibration

The mG calibration block has two purposes: to regulate the driver supply to

prevent signal integrity degradation due to supply noise, and to stabilize the output

impedance by stabilizing mG . For these purposes, a mG calibration circuit in [16]

is employed for both prototypes of PAM-4 transmitters.

The mG calibration circuit is composed of a constant- mG bias generator and a

voltage regulator. Constant mG can be achieved by using a replica circuit shown in

Fig. 4.8. The replica circuit is composed of a 2X inverter with source degeneration

by a resistor, REFR and a 1X inverter. At a low DDV , when the source-

degeneration effect is not significant, 1I is larger than 2I . However, as DDV in-

creases, the source degeneration of the 2X inverter strengthens, making 2I larger

than 1I . For this reason, two D DDI V curves intersect at the point shown in Fig.

4.8 except when DDV is zero. At the point, the currents 1I and 2I are given as

follows:

0

100

200

300

400

0.0 0.5 1.0 1.5

I2I1

Lock point

I DS [

μA

]

VDD [V]

1X

RREF

2X

I1 I2

VDD

VG1 VG2

Fig. 4.8 Basic concept for constant- mG bias generator.


1 1

1 1

2

2

p DD G thp

n G thn REF

I V V V

V V I R

, (4.1)

2 2

2

p DD G thp

n G thn

I V V V

V V

. (4.2)

They are based on the alpha-power model that approximates the current equations

rather than sticking to the complicated short-channel equation. The parameters, βp

and βn in the above equations, contain technology-dependent parameters fitted to

actual simulation results. The alpha-power model for the given technology specifies

that βn is twice as large as βp with the same W/L ratio and α has a value of 1.3. On

the other hand, as derived in [16], if 1I is equal to 2I , mG of the replica inverter

can be expressed as

11

1

12

2

p nm

REF n p

GR

. (4.3)

Note that mG is now dependent only on REFR and the technology-dependent pa-

rameters, while it has nothing to do with process and temperature variations.

Fig. 4.9 details the implementation of a mG calibration circuit. To force the cur-

rents 1I and 2I to be equal, a feedback loop is enabled, and the resulting condi-

tion exactly corresponds to the point where (4.3) is derived, which means mG of

the 1X inverter is now make constant with 2V . Non-ideal distribution of the power

supply, however, mandates the use of a voltage regulator as shown in Fig. 4.9 in-

stead of directly using FBV for supplying the current for the driver. The voltage re-


gulator generates DRVV which is exactly the same as 2V , thereby providing con-

stant mG for the driver which is appropriately scaled to meet the impedance condi-

tion of 0Z .

With the mG calibration circuit, for any process and temperature variations,

DRVV is adequately adjusted to keep mG of the driver constant, which is well veri-

fied by the impedance simulation results for various corner conditions as illustrated

in Fig. 4.10. As shown in Fig. 4.10, the mG calibration circuit keeps the output im-

pedance of the feedback driver almost constant regardless of the PVT variations.

VDRV

VDD VDD

CBYPRREF

2X1X

W/L W/L

20W/L

I1I2

V1

V2 VFB

Fig. 4.9 Circuit diagram of mG calibration circuit consisting of constant- mG bias gen-

erator and voltage regulator.


49.5

50

50.5

51

-20 0 20 40 60 80 100 120

TT SS FF FS SFIm

ped

an

ce [Ω

]

Temperature [°C]

(a)

49

49.5

50

50.5

51

1.8 1.85 1.9 1.95 2

Imp

ed

an

ce [Ω

]

Supply voltage [V]

TT SS FF FS SF

(b)

Fig. 4.10 Simulated output impedance of the driver for (a) process corner and tempera-

ture (PT) variations and for (b) process corner and voltage (PV) variations.


4.3.3 Serializer with Tap Generation

In the prototype 1, a fractionally spaced 3-tap FFE is employed, which was intro-

duced for a PAM-4 transmitter in [69]. The fractionally spaced FFE can be more

effective than the baud-spaced FFE for channels with specific conditions. To im-

plement the fractionally spaced FFE, a controllable delay unit for sub-UI tap delay

generation is required. However, the sub-UI delay generator introduces large amount

of supply noise induced jitter and ISI in the process of adjusting the tap delay with a

wide range. In order to minimize the bandwidth loss while having a wide delay

range, the proposed delay generator proposed in prototype 1 employs a tunable latch.

Fig. 4.11 shows the proposed tap delay generator, in which two CMOS inverter

chains are coupled with tunable cross-coupled latches. Each latches increases the to-

Pre_p

Pre_n

Main_p

Main_n

Post_p

Post_n

1X

0.3X

n1

p1

n2

p2

n6

p6

...

...

enb[i]

nipi

en[i]

enb[i]

en[i]

pi

pi ni

ni

Pre-discharge & -charge

Tunable Latch

Pre-discharge & -charge

Fig. 4.11 Circuit diagram of sub-UI tap delay generator for fractionally spaced FFE.


tal delay when enabled. Owing to a regeneration characteristic of the cross-coupled

latches, the proposed delay generator introduces low jitter compared with conven-

tional topologies such as delay line based on capacitive tuning. Simulated tunable

delay range of the sub-UI delay generator according to various corner and the num-

ber of activated latches are shown in Fig. 4.12.

On the other hand, Fig. 4.13 and Fig. 4.14 illustrate the serializing data path of

16

18

20

22

24

26

28

30

32

0 1 2 30 1 2 316

18

20

22

24

26

28

30

32

# of the enabled tunable latches

De

lay [

ps]

SSTTFF

0.30 UI

0.35 UI

0.40 UI

Fig. 4.12 Simulated tunable delay range of sub-UI delay generator.

3-tapGENTX

PRBSGENs

4:2

4

4

2

2 3-tapGEN

22

2

22

2

2:1SER

+ S2D

MSBmain_cursor

MSBpost_cursor

MSBpre_cursor

LSBmain_cursor

LSBpost_cursor

LSBpre_cursor

/2

Level Shifter& DCC

CK2

CK4

Fig. 4.13 Block diagram of clock and data path for serialization and tap generation.


the prototype 2. A block diagram of clock and data path for serialization and tap

generation is shown in Fig. 4.13. In the clock path, AC-coupled clock buffers for

level shifting and duty-cycle correction are employed and bandwidth-enhanced

CMOS clock buffers with feedback resistance are used for improvement of logic

speed [16]. Also, tri-state inverter based flip-flops are employed for the first stage of

the frequency divider to further reduce the time delay from conventional true single

phase clocking (TSPC) flip flop (FF) based dividers. Meanwhile, two independent

parallel PRBS-7 sequences are generated in the internal PRBS-7 generators for veri-

fication, and they are serialized as final MSB and LSB data. In this process, the 3-

tap FFE tap data are generated before the last-stage of the serializer for robust opera-

tion. Fig. 4.14 shows the detailed implementation of the tap generating serializer. To

generate a baud-spaced tap delay, half-period spaced retimer is needed as shown in

the timing diagram of the Fig. 4.14. As a result, ten FFs must be added before the

CK2

D Q

CK2

PRE2:1MUX

CK2

D Q

CK2

D Q

CK2

D Q

CK2B

D Q

2:1MUX

CK2B

MAIN2:1MUX

CK2B

D Q

CK2B

D Q

CK2B

D Q

CK2

D Q

CK2

D Q

CK2

D Q

2:1MUX

CK2

POST2:1MUX

CK2

D Q

CK2

D Q

CK2

D Q

CK2

D Q

CK2

D Q

2:1 SER

2:1 SER

2:1 SER

4:2SER

D<0>

D<3>

D<1>

D<2>

D<0,2>

D<1,3>

D<0:3>Flip-flop Sharing

CK2

D Q

CK2

PRE2:1MUX

CK2

D Q

CK2B

D Q

2:1MUX

CK2B

MAIN2:1MUX

CK2B

D Q

CK2

D Q

CK2

D Q

CK2

D Q

2:1MUX

CK2

POST2:1MUX

CK2

D Q

CK2

D Q

CK2

D Q

2:1 SER

2:1 SER

2:1 SER

D<0,2>

D<1,3>

D<0:3>

10 flip-flops are added Only 4 flip-flops are added

CK2

CK2B

PRE

MAIN

POST

D0 D1

D0 D1 D2

D0

62.5 ps

1-UI (31.25 ps)

tck2q,mux

tck2q,mux

tck2q,mux

D2

D3

D1

Timing Diagram

(16GHz)

(16GHz)

Fig. 4.14 Block diagram and timing diagram of the tap generating serializer.


last-stage 2-to-1 serializers to generate 3-tap cursors in a conventional scheme using

the retimers. However, by sharing the intrinsic FFs in the 2-to-1 serializer, six FFs

can be removed for the same tap generating operation. A total of twelve FFs are re-

moved for both MSB and LSB data path by using this FF sharing technique whereby

reducing the circuit overhead and power consumption of the serializer. Each clocked

FF is implemented as the tri-state inverter based FF to reduce clock-to-q delay in

high-speed operation.

On the other hand, one of the building blocks of the transmitter that operates at

the highest speed is the last-stage serializer. Fig. 4.15 shows the circuit diagram of

the last-stage 2-to-1 serializer which is employed for both prototypes of PAM-4

transmitters. It is important to reduce the data ISI introduced by the last-stage serial-

izer. Therefore, the tri-state inverter based FF is employed to enhance the circuit

bandwidth in comparison with the typical TSPC FF, as shown in Fig. 4.15. Moreo-

ver, the pre-charging and -discharging transistors are added to a last-stage multi-

plexer (MUX) in the proposed serializer to further reduce the data-dependent ISI at

the serializer output, as shown in the post-layout simulation result of Fig. 4.16.


clkb

clk

clkclk

clkb

clkb

clk

clk

clkb

clk

D0_d

clk

clkb

clkb

D0

D1

D0_d

D1_d

D1_d

Qb

clkb

clkbclkb

clkclk

Pre-discharge

Pre-charge

Tri-State Inverter-Based FF

Last-stage MUX

Fig. 4.15 Circuit diagram of proposed last-stage 2-to-1 serializer.

0.2

0.0

0.4

0.6

0.8

1.0

Vo

ltag

e [

V]

1.2

Time [ps]0 10 20 30 40

w/o pre-ch. & -disch.

w/ pre-ch. & -disch.

Fig. 4.16 Post-layout simulated eye diagrams at the serializer output (a) without pre-

charging and –discharging devices and (b) with pre-charging and –discharging devices.


4.3.4 Half-Rate Clock Generation

The clock generation circuit is responsible for several issues relating to the de-

sign of a wide-range transmitter. Specifically, in covering a wide range of frequen-

cies, the clock generation circuit consumes a significant amount of resources. Be-

cause an LC oscillator has a higher operating frequency but narrow frequency range,

while a ring oscillator has a wider range but lower frequency, it is difficult to cover a

wide frequency range using a single PLL with a single oscillator. As a result, many

wide-range transmitter designs employ multiple PLLs or oscillators [68], [84]-[86].

In this work, a single PLL, which maximizes the operating frequency by using an

optimized two-stage ring oscillator shown in Fig. 4.17, is employed for high-speed

and area-efficient design. Thanks to the additional phase shift introduced by cross-

1x

0.7x

2-stage ring VCO

vctrl vbias

Fig. 4.17 Circuit diagram of implemented two-stage ring oscillator.


coupled latches due to the hysteresis effect, the two-stage ring oscillator can sustain

the oscillation meeting the Barkhausen criteria [87]. A latch ratio of 0.7 is used for

sufficient phase shift. The voltage-controlled oscillator (VCO) in Fig. 4.17 employs

a current-starved structure and only a pull-down current source at the bottom of the

CPPFD

upb

dn

Programmable Divider (/16 ~ /32)

REF2-stage

ring VCO

Level shifter & CLK Buffers

vctrl

Loop BW control

Fig. 4.18 Block diagram of phase-locked loop (PLL) for half-rate clock generation.

Vn1

Vp1

Vn1

Vp2

Vn2

Vp1

Vn1

Vp1

Vn2

Vp2

Replica-Feedback Bias CircuitCharge Pump (3 slices)

Upb<2> Upb<2>

dn<2> dn<2>

I1 I2I1 I2

Fig. 4.19 Circuit diagram of mismatch reduced charge pump for wide-range loop band-

width control of the phase-locked loop.


ring oscillator core. The pull-down current source is controlled by two analog volt-

ages for coarse- and fine-control of oscillation frequency.

On the other hand, the overall block diagram of the PLL for half-rate clock gen-

eration is described in Fig. 4.18. A VCO based on two-stage ring oscillator generates

a 90 degree spaced four-phase half-rate clock. Coarse frequency selection is used in

the ring-VCO to support a wide-range operation and to accommodate the PVT varia-

tions. The overall division factor of the PLL is from 16 to 32, and the first divider is

implemented with the tri-state inverter based divider which can operate at the maxi-

mum frequency that the VCO can generate. An AC-coupled clock buffer corrects

the common level and duty-cycle of the VCO output and the clock is buffered to the

data paths. A mismatch reduced charge pump with a replica-feedback bias is used,

as shown in Fig. 4.19, and its current is adjusted to control the PLL loop bandwidth.

Thanks to the wide current adjusting range of the charge pump by using 2-bit ther-

mometer, the wide-range loop bandwidth control of the PLL can be achieved.


4.4 Measurement Results

4.4.1 28-Gbit/s 1.6-pJ/bit PAM-4 Transmitter with

RFB Driver

The prototype chip of PAM-4 transmitter with RFB driver (prototype 1) is fab-

ricated in 28-nm CMOS technology and occupies an active area of 0.048 mm2, as

shown in Fig. 4.20. The test chip is wire-bonded to a test board for the silicon ver-

ification of the proposed PAM-4 transmitter. Firstly, the performance of the half-

rate clock generating PLL is verified. The measured waveform of the divided-by-

16 transmitter clock is shown in Fig. 4.21. The RMS jitter of the divided-by-16

PLL clock is measured as 3.347 ps, as shown in Fig. 4.21. To verify the impedan-

CLK GEN.

PRBS GEN.+ 8:2 SER.

Gm CAL.

1100 um

1000 umPDRV DRV

A

B C D

E

150u

80u

160u

250u

Fig. 4.20 Chip microphotograph of PAM-4 transmitter (prototype 1).


ce-matching characteristics of the proposed driver, the return loss of the differen-

tial outputs is measured using a network analyzer, as shown in Fig. 4.22. The

measured return loss is mostly below -10 dB, except for the high-frequency input;

this is mainly because of impedance discontinuities caused by the bonding wires

and the connectors at high frequency.

RMS Jitter : 3.347 ps

2.28 ns

437.5 MHz Clock

Fig. 4.21 Measured divided-by-16 transmitter clock (437.5 MHz).

Out (+)

Out (–)

-4.00E+01

-3.50E+01

-3.00E+01

-2.50E+01

-2.00E+01

-1.50E+01

-1.00E+01

-5.00E+00

0.00E+00

1.00E+07 1.00E+08 1.00E+09 1.00E+10

0

-5

-10

-15

-20

-25

-30

-35

-400.01 0.1 1 10

Frequency [GHz]

Mea

su

red

S1

1 [

dB

]

Out (+)

Out (–)

Fig. 4.22 Output return loss (S11) measured at driver output.


Fig. 4.23 presents an eye diagram of the PAM-4 output signal at 28 Gb/s meas-

ured by a real-time oscilloscope. Only post-tap calibration is enabled with the opti-

mum coefficient for a 3 cm PCB trace channel to deliver a peak-to-peak differential

output voltage swing of 207 mVpp,diff. Fig. 4.24 shows measured PAM-4 eye dia-

grams with various FFE conditions. Measured maximum differential output voltage

swing is 221 mVpp,diff, which is achieved when both pre- and post-tap calibrations

are disabled. Fig. 4.25 summarizes the measured power breakdown of the proposed

1 Post-tap comp. only (optimum)

207mV (differential)71.4ps

Fig. 4.23 Measured differential PAM-4 eye diagram at 28 Gb/s.

Without FFE 1 Post-tap + 1 pre-tap (overshoot)

221mV (differential) 197mV (differential)

Fig. 4.24 Measured differential PAM-4 eye diagrams with various FFE conditions.


PAM-4 transmitter operating at 28 Gb/s. For the optimum setting shown in Fig. 4.23,

the entire transmitter consumes a total power of 44.6 mW, which results in an ener-

gy efficiency of 1.59 pJ/b.

PDRV & 3-Tap FFE(23.0 mW)

SER& PLL

(10.2 mW)

DRV &Gm CAL.(11.4 mW)

* Total 44.6 mW @ data rate of 28 Gb/s

Fig. 4.25 Measured power breakdown of the prototype-1 PAM-4 transmitter.


4.4.2 64-Gbit/s 1.5-pJ/bit PAM-4 Transmitter with

AFB Driver

The prototype chip of PAM-4 transmitter with AFB driver (prototype 2) is also

fabricated in 28nm CMOS technology and occupies 0.185 mm2, as shown in Fig.

4.26. The test chip is wire-bonded to a test board for silicon verification. Fig. 4.26

also illustrates the measured power breakdown of the proposed PAM-4 transmitter.

The pre-driver and the driver with mG calibration circuits only consume 13.3 mW

while transmitting PRBS 27-1 data at 64 Gb/s. The measurement setup for three

types of measurement is depicted in Fig. 4.27. To verify the high-speed operation of

the test chip, the differential PCB trace is optimized through electromagnetic simula-

tion. Measured return loss and insertion loss of the test channel including PCB trace

PRBS Gen. & SER

(54.8 mW)

Front-End & Gm Cal. (13.3 mW)

PLL(29.1 mW)

Total Power Consumption97.2 mW @ 64 Gb/s

CLK GEN.

PRBS GEN.+ 4:2 SERs.

PDRV DRV

B C D

A

E

Gm CAL.

BIAS GEN.

240 μm

160 μm

F

Fig. 4.26 Chip microphotograph of PAM-4 transmitter (prototype 2) and measured pow-

er breakdown at 64 Gb/s operation.


and end-launch SMA connectors are shown in Fig. 4.28. Measured jitter histogram

of divided-by-16 PLL clock (1 GHz) and its frequency spectrum and phase noise

plot are shown in Fig. 4.29 and Fig. 4.30. The integrated RMS jitter from 1 kHz to

40 MHz is measured as 115 fs, which exhibits the state-of-the-art PLL figure-of-

merit (FoM) of -244.1 dB. The single-ended output return loss is measured by a

network analyzer to verify the matching characteristic of the proposed PAM-4 driver.

Measured return loss well satisfies the OIF-CEI-56G mask limit with sufficient

margin, as shown in Fig. 4.31. Fig. 4.32 shows the single-ended eye diagrams of the

PAM-4TX IC

Power & Bias Board

DC 6VBattery

DUT Board

Tektronix MSO73304 Real-time

Oscilloscope

BIAS-TDRVP

DRVN

REF CLK

DIV CLK

DC Block

DC Block

20cm Cable

20cm Cable

Agilent E4445ASpectrum A.

Agilent E5071CNetwork A.

Agilent E8267DVector Signal G.

HYPERLABSHL9404 Balun

64 Gb/s PAM-4 Data(Measure 3)

Output RL, TDR (Measure 2)

16 GHz PLL Clock(Measure 1)

Fig. 4.27 Measurement setup for prototype-2 PAM-4 transmitter.

-60

-50

-40

-30

-20

-10

0

0 5 10 15 20

-2.5

-2

-1.5

-1

-0.5

0

0 5 10 15 20

S11 S21

Fig. 4.28 Measured return loss and insertion loss of test channel.


Divided PLL Clock1 GHz

20mV

20ps

RMS: 1.5psPk-Pk: 11ps

Fig. 4.29 Measured jitter histogram of divided-by-16 transmitter clock (1 GHz).

Fig. 4.30 Measured frequency spectrum and phase noise plot of the divided-by-16

transmitter clock (1 GHz).

-2.50E+01

-2.00E+01

-1.50E+01

-1.00E+01

-5.00E+00

0.00E+00

1.00E+07 1.00E+08 1.00E+09 1.00E+10

0

-5

-10

-15

-20

-25Mea

su

red

S22 [

dB

]

0.01 0.1 1 10

Frequency [GHz]20

CEI-56G-PAM4-VSR

Fig. 4.31 Measured single-ended output return loss.


PAM-4 (64 Gb/s) 30mV 10ps

432 mVppd

NRZ (32 Gb/s) 30mV 10ps

324 mVppd


436.8 mVppd


312 mVppd


429.6 mVppd


312 mVppd


458.4 mVppd


336 mVppd


465.6 mVppd


338.4 mVppd

Fig. 4.32 Measured single-ended NRZ and PAM-4 eye diagrams with variable data rates.


NRZ and PAM-4 outputs at variable data rates. As shown in Fig. 4.32, the proposed

PAM-4 transmitter achieves multi-standard operation by supporting various speed.

At 64 Gb/s, the optimum FFE coefficients for the MSB path are measured as [C-1, C0,

C1] = [-1, 14, -1] compensating for insertion loss by 2.5 dB at the Nyquist frequency

whereas the optimum FFE coefficients for the LSB path are measured as [-1, 5, -1]

compensating by 7.4 dB due to a nonlinearity. The differential output swing of the

64 Gb/s PAM-4 eye diagram is about 450 mVppd, which corresponds to a maximum

output swing of ~600 mVppd when the FFE is disabled. Single-ended eye height and

eye width are measured as 48 mV and 0.4 UI, respectively, and the ratio of level

mismatch (RLM) is obtained as 96 %, which satisfies 0.92LMR condition of the

100 GbE PAM-4 spec (100GBASE-KP4). As illustrated in Fig. 4.33, both the power

consumption and the energy efficiency are well scaled for both signaling modes.

The overall performance of the transmitter is summarized and compared to pre-

vious works, as shown in Table 4.1. The proposed PAM-4 transmitter with AFB

driver achieves the data rate of 64 Gb/s while consuming the power of 97.2 mW,

which exhibits the best energy efficiency of 1.5 pJ/b among the reported PAM-4

transmitters with the data rates of above 56 Gb/s.

0.8

1

1.2

1.4

1.6

1.8

2

30

40

50

60

70

80

90

100

25 35 45 55 651.5

2

2.5

3

3.5

30

40

50

60

70

80

90

100

12 18 24 30 36

Po

we

r [m

W]

Data Rate [Gb/s]E

ne

rgy E

ffic

ien

cy [

pJ

/b]

Po

we

r [m

W]

Data Rate [Gb/s]

En

erg

y E

ffic

ien

cy [

pJ

/b]

Energy EfficiencyPower Consumption

Energy EfficiencyPower Consumption

PAM4 NRZ

Fig. 4.33 Measured power and energy efficiency scalability.


Table 4

.1 P

erforman

ce summ

ary and comparison of P

AM

-4 transmitters.

Tech

no

log

y N

od

e

Data

Ra

te (G

b/s

)

Po

wer (m

W)

Driv

er T

yp

e

Max

imu

m O

utp

ut

Sw

ing

(mV

pp

d )

FF

E

En

erg

y E

fficie

ncy

(pJ/b

it)

PL

L C

loc

kR

MS

Jitte

r (fs)

JS

SC

201

5[9

]

65

nm

56 −

62

290

CM

L

500

3-ta

p

508

(10

0H

z~

1G

Hz)

ISS

CC

201

7[7

6]

40

nm

56

220

CM

L

N/A

3-ta

p

3.5

7*

ISS

CC

201

7[7

5]

28

nm

FD

SO

I

64

145

*

CM

L

120

0

4-ta

p

2.2

7*

JS

SC

201

7[7

8]

16n

mF

inF

ET

56

140

*

CM

L

120

0

3-ta

p

2.5

*

ISS

CC

201

7[6

9]

14n

m

56

100

.7

SS

T

900

3-ta

p½

-bau

d

1.8

Th

is W

ork

28

nm

64

97

.2

Activ

e-

Feed

bac

k

600

3-ta

pb

au

d

1.5

* Po

wer c

on

su

mp

tion

, en

erg

y e

fficie

nc

y, a

nd

ran

do

m jitte

r ex

clu

din

g P

LL

blo

ck

** Fu

ll ch

ip a

rea

Activ

e A

rea (m

m2)

1.1

4**

1.1

4**

N/A

N/A

0.0

35

0.1

85

688

(10

0H

z~

1G

Hz)

291

(50

0k

Hz~

8G

Hz)

N/A

N/A

115

(1k

Hz~

40M

Hz)

290

(10

0H

z~

1G

Hz)

5.1

8(@

56

Gb

/s)

ISS

CC

201

8[7

9]

10n

mF

inF

ET

112

232

CM

L

750

3-ta

p

2.0

7

0.0

30

2***

ISS

CC

201

8[7

0]

14

nm

112

286

*

SS

T

920

8-ta

p

2.6

*

0.0

95

***

N/A

ISS

CC

201

8[7

3]

16

nm

Fin

FE

T

19 −

56

N/A

SS

T

100

0

4-ta

p

N/A

N/A

ISS

CC

201

8[7

1]

16n

mF

inF

ET

64

89

.7*

SS

T

100

0

N/A

1.4

*

0.0

9***

162

*

*** Ac

tive

are

a w

/o P

LL

154

(N/A

)

180

(N/A

)

��

� �

��

�=

��

��

[��

�

��

�

��

��

��

��

] ****

Chapter 5. Conclusion 122

Chapter 5

Conclusion

As the bandwidth demand for chip-to-chip or board-to-board communication is

rapidly being increased, multi-level signaling (e.g. PAM-4 signaling) has become a

promising candidate for the next generation high-bandwidth I/O interface. To meet

the requirements of the standards such as IEEE P802.3bs 400 Gb/s Ethernet or OIF

CEI-56G, various FFE techniques are employed in reported PAM-4 transmitters. In

addition to compensating for channel loss by using an equalizer, achieving a good

energy efficiency is also a crucial issue for the next generation I/O systems. Howev-

er, recent PAM-4 transmitters often neglect improving the energy efficiency of the

PAM-4 output driver and the corresponding pre-driver stages, as they employ typi-

cal voltage-driven driver topologies.

In this thesis, the drawbacks and limitations of the conventional voltage-mode or

current-mode PAM-4 drivers are discussed. To overcome the problems with existing

voltage-driven drivers, the concept of the current-driven driver newly defined by the


author is introduced. As a detailed implementation of the current-driven feedback

driver, two types of feedback driver, RFB and AFB driver, are introduced and ana-

lyzed. On a more quantitative level, theoretical analyses are presented in various

aspects to support the excellence of the current-driven feedback driver. Based on the

study, two prototypes of low-power, high-speed PAM-4 transmitters based on the

RFB or AFB driver are proposed.

As the first prototype, a 28 Gb/s PAM-4 transmitter with a fractionally spaced 3-

tap FFE and a Gm-regulated RFB driver is fabricated in 28 nm CMOS technology.

Owing to the current-driven characteristic of the driver, the 3-tap FFE is realized at

the pre-driver stage in a simplified current-summing manner consuming low power

consumption. The output impedance of the driver is controlled by regulating the Gm

of the driver cell, which results in good signal integrity. To obtain the appropriate

tap delay, a novel topology is introduced for the delay generator to enhance both the

delay and the bandwidth. All the transmitter circuits are CMOS-based implemented

thanks to the increased bandwidth by using a resistive feedback. The transmitter

achieves the data rate of 28 Gb/s while consuming 44.6 mW, which results in the

energy efficiency of 1.59 pJ/b.

As the second prototype, a 64 Gb/s PAM-4 transmitter with a current-summing

3-tap FFE and a Gm-regulated AFB driver is presented. An AFB inverter-based driv-

er is proposed to achieve a larger output swing compared with the RFB driver with

limited output swing. The FFE tap generation is embedded into the serializer to min-

imize the overhead of FFE, by replacing a power-hungry delay generator. As a result,

both the energy efficiency and the operating speed are considerably enhanced com-

pared to the first prototype. A prototype chip is fabricated in 28 nm CMOS technol-


ogy, and occupies 0.185 mm2. Owing to the improved loop bandwidth of the PLL,

the integrated RMS jitter from 1 kHz to 40 MHz is measured as 115 fs, which exhib-

its the state-of-the-art PLL FoM of -244.1 dB. The proposed transmitter achieves the

data rate 64 Gb/s while consuming 97.2 mW, which exhibits the best energy effi-

ciency of 1.5 pJ/b among recently reported PAM-4 transmitters with an internal PLL.

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초 록

최근 데이터 센터나 고성능 컴퓨팅 시스템의 수요가 늘어남에 따라 유

선 통신에서 요구되는 대역폭도 기하급수적으로 증가해왔다. 그러나 기존

구리선 기반 채널의 한계점으로 인해 고속 입출력 회로의 핀 당 대역폭

개선은 어려움에 직면해 있다. 그 결과, 비제로 복귀 (NRZ) 신호처리 방

식을 대신하여 같은 Nyquist 주파수에서 더 높은 전송 속도를 지원하는

다중레벨 신호처리 방식이 차세대 고속 입출력 인터페이스를 위한 해결책

으로 대두되었다. 그 중에서도, 4 레벨 펄스진폭변조 기술 (PAM-4)은 다

양한 산업 표준의 대역폭 요구에 부응하기 위해 널리 적용되고 있다. 전

통적인 전압구동형 드라이버에 기반한 기존 4 레벨 펄스진폭변조 송신기

들은 많은 전력을 소모하는 전치 드라이버와 다중탭 피드포워드 등화기

구조 때문에 제한된 에너지 효율만을 보여왔다. 본 논문에서는 이러한 기

존 전압구동형 드라이버의 문제점을 극복하기 위해 전류구동형 피드백 드

라이버의 개념을 새로 정의하고, 각각 저항성피드백 드라이버와 능동성피

드백 드라이버에 기반한 두 가지 타입의 저전력, 고속 4 레벨 펄스진폭변

조 송신기 구조를 제안한다.

첫 번째 프로토타입으로서, 부분간격 세 탭 피드포워드 등화기와 Gm

이 제어된 저항성피드백 드라이버를 이용하여 28 Gb/s 의 4 레벨 펄스진

폭변조 송신기가 28nm CMOS 공정에서 제작되었다. 드라이버의 전류구

동 특성 덕분에, 세 탭 피드포워드 등화기는 전치 드라이버 단에서 적은

전력만을 소모하는 전류합산 방식으로 간단하게 구현되었다. 드라이버의

출력 임피던스는 Gm 을 제어함으로서 조절 가능하고, 이는 송신기가 좋은

신호 특성을 갖도록 하였다. 또한, 적절한 탭 지연을 얻기 위하여 지연량

과 대역폭이 모두 늘어난 새로운 형태의 지연 생성기가 제안되었다. 송신

기 내의 회로들은 저항성피드백에 의해 늘어난 대역폭 덕분에 모두

CMOS 기반으로 구현된다. 제안된 송신기는 44.6 mW 의 전력만을 소모

하면서도 28 Gb/s 의 전송 속도를 달성하였고, 이는 약 1.59 pJ/b 의 에너

지 효율에 해당한다.

두 번째 프로토타입으로서, 전류합산 방식의 세 탭 피드포워드 등화기

와 Gm 이 제어된 능동성피드백 드라이버를 이용하여 64 Gb/s 의 4 레벨

펄스진폭변조 송신기가 구현되었다. 능동성피드백 인버터 기반의 드라이

버는 출력 스윙이 제한된 저항성피드백 드라이버에 비하여 더 큰 전압 출

력 스윙을 갖기 위하여 제안되었다. 피드포워드 등화기의 탭 생성은 직렬

화기에 내장되었는데, 많은 전력을 소모하는 지연 생성기를 대체함으로서

오버헤드를 대폭 줄일 수 있었다. 그 결과 첫 번째 프로토타입에 비하여

동작 속도와 에너지 효율이 모두 크게 향상되었다. 한편, 두 번째 프로토

타입의 칩도 28 nm CMOS 공정에서 제작되었고, 약 0.185 mm2 의 실리

콘 면적을 차지한다. 위상 동기화 루프의 향상된 루프 대역폭으로 인해 1

kHz 에서 40 MHz 까지 합산된 RMS 지터는 115 fs 으로 측정되었고, 이

는 좋은 FoM 인 -244.1 dB 에 해당한다. 제안된 송신기는 97.2 mW 의

전력을 소모하면서 64 Gb/s 의 전송 속도를 지원하였고, 최근에 보고된

위상 동기화 루프가 포함된 4 레벨 펄스진폭변조 송신기들 중에서 가장

좋은 에너지 효율인 1.5 pJ/b 을 달성하였다.

주요어 : CMOS, 다중레벨 신호처리, 4 레벨 펄스진폭변조 송신기, 저항성

피드백 드라이버, 능동성피드백 드라이버, 전압·전류구동형 드라이버

학 번 : 2013-20891

Disclaimers-space.snu.ac.kr/bitstream/10371/162002/1/000000157820.pdf · 2019. 11. 14. · Speed...

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