-

MOS . .

MOS n p . Sio2 ( 50 ) . . MOS SIO2 pn+ .

Cross-Section of CMOS Technology

Threshold Voltage: Concept

. . . . : MOSFET, BJT MOSFET BJT . .

Metal Oxide Semiconductor Field Effect Transistor p . n . . . . .Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

Source, Drain , Gate . : n p p n . . . p,n .

substrate . . n . . substrate p n (inversion layer)Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

NMOS n n-channel NMOS . VGS Vt . 0.5 , 1 . . . : n .

(Vds) id . . VGs-Vt . VGS vt . .Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS Vt and thus iD is proportional to (vGS Vt) vDS. Note that the depletion region is not shown (for simplicity).

Vgs-Vt Vds . VGS . VGS Vt . VGS . .Figure 4.4 The iDvDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS.

VDS 0 VDS VGS- VDS . .Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.

VDS iD-vDS . VDSsat = vGS Vt . VDS . : Triode region: VDS < VDSsatSaturation region: VDS VDSsatFigure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS Vt the channel is pinched off at the drain end. Increasing vDS above vGS Vt has little effect (theoretically, no effect) on the channels shape.

MOSFET vGS > Vt vDS < vGS Vt t triode .Figure 4.8 Derivation of the iDvDS characteristic of the NMOS transistor.

:

. x : . VDS

:

: : . :

:

. : . . :

(Sub Micron) . L . L . .

MOSFET p (PMOS) p n p+ . n VGS VDS Vt . NMOS PMOS .

CMOS MOS CMOS (Complementary MOS) p,n . CMOS . p n well . . n p n .Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

NMOS . . .Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant.

VGS

iD-VDS VGS .Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) The iDvDS characteristics for a device with kn (W/L) = 1.0 mA/V2. : .

iD-VDS : VGS>=Vt VDS . : : VDS : .

pinch off

: VDS VGS .

VDS .Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region.Figure 4.12 The iDvGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, kn W/L = 1.0 mA/V2).

iD VDS . VDS pinch off . VGS - V t = VDSsat . . .Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL). .Channel Length Modulation

.

VDS :

ID VDS .

VDSFigure 4.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L.

VDS :

: ID :VA (Early voltage) = 1/ with a typical value of 200 to 300V.VA is proportional to L, therefore, short-channel devices .suffer more from channel-length modulation

Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS and is given by Eq. (4.22).

PMOSFigure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal.

PMOS . Vt

BS BD . NMOS . VSB . . body Effect . .

Vt ~2mV . kn iD . iD .

( 20 150 ) .(Weak avalanche) . punch through . - ( 30 ). . (Gate-oxide breakdown) MOSFET . ( ). MOSFET .

MOS : Enhancement Depletion . N n+ . VGS=0 ID . VGS . . ID . Vt .

MOS transistors Types and SymbolsDSGDSGGSDDSGNMOSEnhancementNMOSPMOSDepletionEnhancementBNMOS withBulk Contact

(substrate) PN . . VSB . VGS . VSB = Source Bulk voltage

Vt .

VSB Vt ID . .

VSB=0

The Threshold VoltageFermi Potential (-0.3 V for typical p-type silicon substrates) inversion

- . .

NMOS VDD VDD/2 :

MOS . : MOS .

MOS

: . Cg : ( ) .

lateral diffusion . L Ld . (overlap capacitance). . .

MOS . . . . .

VGS=0 WLCox . - . . 2/3 .

:

diffusion capacitance . . : ( ). m=0.5 .

stopper . stopper . 0.33 .5 . Xj

Cj the junction capacitance per unit area

Diffusion Capacitance

Junction Capacitance

.

- . . :

RC the contact resistance, W the width of the transistor, and LS,D the length of the source or drain region is the sheet resistance per square of the drain sourcediffusion, and ranges from 20 to 100

- . . silicidation . .

layout .

. . 2 .

The Sub-Micron MOS Transistor

short-channel devices . . . . Xc scattering . NMOS 1um .

: :

: k : Vds L 1 . k 1 .

Vds . Vdsat :

Vds : VGT Vdsat

VSB . W,L,VDS . VGS . Inversion . VT0 . Vds . Vds the drain-induced barrier lowering, or DIBL . VDS punch-through . .

. DIBL . .

Latchup

MOS pn . VDD VSS . . . latch up . Rnwell and Rpsubs . .

Latchup

SPICE MODELS

SPICE . . Berkley .

MAIN MOS SPICE PARAMETERS

SPICE Parameters for Parasitics

SPICE Transistors Parameters

Technology Evolution

Process Variations

Impact of Device Variations

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