Day3 Open
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Transcript of Day3 Open
Day3Day3● Day2 Review
● Combinational Logic ● Verilog HDL Basic, Combinational Logic● HDL coding● ModelSim simulation, waveform display● Q: When & Why do I need simulation??
● Day3 Topics● 順序控制的邏輯實現 ( 組合邏輯)● 實驗板介紹 , Quartus 介紹 , ● Lab: 組合邏輯 LED 模擬● 順序控制的邏輯實現 ( 循序邏輯)● Lab: 自保回路 (R-S Latch) 電路實驗● Lab: 計時電路 (TIMER) 電路實驗
● HDL Coding Techniques, RTL Code Examplehttp://www.xilinx.com/itp/3_1i/data/fise/xst/chap02/xst02000.htm
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