Cy 62256

56
32K x 8 Static RAM

CY62256

Features

• High Speed (55 ns and 70 ns availability)• Voltage Range

— 4.5V–5.5V Operation• Low active power (70 ns, LL version)

— 275 mW (max.)• Low standby power (70 ns, LL version)

— 28 µW (max.)• Easy memory expansion with CE and OE features• TTL-compatible inputs and outputs• Automatic power-down when deselected• CMOS for optimum speed/power

Functional Description

The CY62256 is a high-performance CMOS static RAM orga-nized as 32K words by 8 bits. Easy memory expansion is pro-

vided by an active LOW chip enable (CE) and active LOWoutput enable (OE) and three-state drivers. This device has anautomatic power-down feature, reducing the power consump-tion by 99.9% when deselected. The CY62256 is in the stan-dard 450-mil-wide (300-mil body width) SOIC, TSOP, ReverseTSOP and 600-mil PDIP packages.

An active LOW write enable signal (WE) controls the writ-ing/reading operation of the memory. When CE and WE inputsare both LOW, data on the eight data input/output pins (I/O0through I/O7) is written into the memory location addressed bythe address present on the address pins (A0 through A14).Reading the device is accomplished by selecting the deviceand enabling the outputs, CE and OE active LOW, while WEremains inactive or HIGH. Under these conditions, the con-tents of the location addressed by the information on addresspins are present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unlessthe chip is selected, outputs are enabled, and write enable(WE) is HIGH.

Logic Block Diagram Pin Configurations

A9A8A7A6A5A4A3A2

COLUMNDECODER

RO

W D

EC

OD

ER

SE

NS

E A

MP

S

INPUTBUFFER

POWERDOWN

WE

OE

I/O0

CE

I/O1

I/O2

I/O3

1234567891011

14 1516

20191817

21

242322

Top ViewSOIC/DIP

1213

25

282726

GND

A6A7A8A9

A10A11A12A13

WEVCC

A4A3A2A1

I/O7I/O6I/O5I/O4

A14

A5

I/O0I/O1I/O2

CE

OEA0

I/O3

512x512ARRAY

I/O7

I/O6

I/O5

I/O4

A10

A13

A11

A12

A1

A14

A0

2223

242526272812

5 1011

151413

12

16

191817

34

20

21

76

89

OEA1A2A3A4

WEVCC

A5A6A7A8A9

A0CEI/O7I/O6I/O5

GNDI/O2I/O1

I/O4

I/O0A14

A10A11

A13A12

I/O3

222324252627

281

2

5 1011

15141312

16

19

1817

34

20

21

7

6

89

OEA1

A2

A3A4

WEVCC

A5

A6

A7

A8A9

A0

CEI/O7I/O6

I/O5

GNDI/O2

I/O1

I/O4

I/O0

A14

A10

A11A13

A12

I/O3

TSOP ITop View

(not to scale)

TSOP I

Top View(not to scale)

Reverse Pinout

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600Document #: 38-05248 Rev. ** Revised February 18, 2002

CY62256

Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Storage Temperature ..................................... −65°C to +150°CAmbient Temperature withPower Applied................................................... 0°C to +70°CSupply Voltage to Ground Potential(Pin 28 to Pin 14).................................................−0.5V to +7.0V

DC Voltage Applied to Outputsin High Z State[1] ....................................... −0.5V to VCC + 0.5V

DC Input Voltage[1].................................... −0.5V to VCC + 0.5V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......................................... >2001V(per MIL-STD-883, Method 3015)

Latch-Up Current.................................................... >200 mA

Operating Range

Range Ambient Temperature VCC

Commercial 0°C to +70°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

Document #: 38-05248 Rev. ** of 13

CY62256

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

CY62256-55 CY62256-70

UnitMin. Typ.[2] Max. Min. Typ.[2] Max.

VOH Output HIGH Voltage VCC = Min., IOH = −1.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.2 VCC+0.5V

2.2 VCC+0.5V

V

VIL Input LOW Voltage −0.5 0.8 −0.5 0.8 V

IIX Input Leakage Current GND < VI < VCC −0.5 +0.5 −0.5 +0.5 µA

IOZ Output Leakage Current

GND < VO < VCC, Output Disabled

−0.5 +0.5 −0.5 +0.5 µA

ICC VCC Operating Supply Current

VCC = Max., IOUT = 0 mA,f = fMAX = 1/tRC

28 55 28 55 mA

L 25 50 25 50 mA

LL 25 50 25 50 mA

ISB1 Automatic CEPower-Down Current— TTL Inputs

Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX

0.5 2 0.5 2 mA

L 0.4 0.6 0.4 0.6 mA

LL 0.3 0.5 0.3 0.5 mA

ISB2 Automatic CE Power-Down Current— CMOS Inputs

Max. VCC, CE > VCC − 0.3VVIN > VCC − 0.3V or VIN < 0.3V, f = 0

1 5 1 5 mA

L 2 50 2 50 µA

LL 0.1 5 0.1 5 µA

Indust’l Temp Range LL 0.1 10 0.1 10 µA

Capacitance[3]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,VCC = 5.0V

6 pF

COUT Output Capacitance 8 pFNotes:1. VIL (min.) = −2.0V for pulse durations of less than 20 ns.2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions

(TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.3. Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

3.0V

5V

OUTPUT

R1 1800Ω

R2990Ω

100 pF

INCLUDINGJIG ANDSCOPE

GND

90%10%

90%10%

< 5 ns < 5 ns

5V

OUTPUT

R1 1800 Ω

R2990Ω

5 pF

INCLUDINGJIG ANDSCOPE

(a) (b)

OUTPUT 1.77V

Equivalent to: THÉ VENIN EQUIVALENT

ALL INPUT PULSES

639Ω

Document #: 38-05248 Rev. ** of 13

CY62256

Data Retention Characteristics

Parameter Description Conditions[4] Min. Typ.[2] Max. Unit

VDR VCC for Data Retention 2.0 V

ICCDR Data Retention Current L VCC = 3.0V,CE > VCC − 0.3V,VIN > VCC − 0.3V orVIN < 0.3V

2 50 µA

LL 0.1 5 µA

LL Ind’l 0.1 10 µA

tCDR[3] Chip Deselect to Data

Retention Time0 ns

tR[3] Operation Recovery Time tRC ns

Data Retention Waveform

Note:4. No input may exceed VCC+0.5V.

3.0V3.0V

tCDR

VDR > 2V

DATA RETENTION MODE

tR

CE

VCC

Document #: 38-05248 Rev. ** of 13

CY62256

Switching Characteristics Over the Operating Range[5]

Parameter Description

CY62256-55 CY62256-70

UnitMin. Max. Min. Max.

READ CYCLE

tRC Read Cycle Time 55 70 ns

tAA Address to Data Valid 55 70 ns

tOHA Data Hold from Address Change 5 5 ns

tACE CE LOW to Data Valid 55 70 ns

tDOE OE LOW to Data Valid 25 35 ns

tLZOE OE LOW to Low Z[6] 5 5 ns

tHZOE OE HIGH to High Z[6, 7] 20 25 ns

tLZCE CE LOW to Low Z[6] 5 5 ns

tHZCE CE HIGH to High Z[6, 7] 20 25 ns

tPU CE LOW to Power-Up 0 0 ns

tPD CE HIGH to Power-Down 55 70 ns

WRITE CYCLE[8, 9]

tWC Write Cycle Time 55 70 ns

tSCE CE LOW to Write End 45 60 ns

tAW Address Set-Up to Write End 45 60 ns

tHA Address Hold from Write End 0 0 ns

tSA Address Set-Up to Write Start 0 0 ns

tPWE WE Pulse Width 40 50 ns

tSD Data Set-Up to Write End 25 30 ns

tHD Data Hold from Write End 0 0 ns

tHZWE WE LOW to High Z[6, 7] 20 25 ns

tLZWE WE HIGH to Low Z[6] 5 5 ns

Switching Waveforms

Notes:5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

IOL/IOH and 100-pF load capacitance.6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate

a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD

10. Device is continuously selected. OE, CE = VIL.11. WE is HIGH for read cycle.

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

tRC

tAAtOHA

Read Cycle No. 1 [10, 11]

Document #: 38-05248 Rev. ** of 13

CY62256

Notes:12. Address valid prior to or coincident with CE transition LOW.13. Data I/O is high impedance if OE = VIH.14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Switching Waveforms (continued)

50%50%

DATA VALID

tRC

tACE

tDOEtLZOE

tLZCE

tPU

DATA OUTHIGH IMPEDANCE IMPEDANCE

ICC

ISB

tHZOEtHZCE

tPD

OE

CE

HIGH

VCCSUPPLY

CURRENT

Read Cycle No. 2 [11,12]

tHDtSD

tPWEtSA

tHAtAW

tWC

DATA I/O

ADDRESS

CE

WE

OE

tHZOE

DATAIN VALIDNOTE

Write Cycle No. 1 (WE Controlled)[8,13,14]

15

tWC

tAW

tSA

tHA

tHDtSD

tSCE

WE

DATA I/O

ADDRESS

CE

DATAIN VALID

Write Cycle No. 2 (CE Controlled)[8,13,14]

Document #: 38-05248 Rev. ** of 13

CY62256

Note:15. During this period, the I/Os are in output state and input signals should not be applied.

Switching Waveforms (continued)

DATA I/O

ADDRESS

tHDtSD

tLZWE

tSA

tHAtAW

tWC

CE

WE

tHZWE

DATAIN VALID

Write Cycle No. 3 (WE Controlled, OE LOW)[9,14]

NOTE 15

Document #: 38-05248 Rev. ** of 13

CY62256

Typical DC and AC Characteristics

1.2

1.4

1.0

0.6

0.4

0.2

4.0 4.5 5.0 5.5 6.0

1.6

1.4

1.2

1.0

0.8

−55 25 125

−55 25 125

1.2

1.0

0.8

NO

RM

ALI

ZE

D t

AA

120

100

80

60

40

20

0.0 1.0 2.0 3.0 4.0

OU

TP

UT

SO

UR

CE

CU

RR

EN

T (

mA

)

SUPPLY VOLTAGE (V)

NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE

NORMALIZED ACCESS TIMEvs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

NORMALIZED SUPPLY CURRENTvs. AMBIENT TEMPERATURE


OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENTvs. OUTPUT VOLTAGE

0.0

0.8

1.4

1.1

1.0

0.9

4.0 4.5 5.0 5.5 6.0

NO

RM

ALI

ZE

D t

SUPPLY VOLTAGE (V)

NORMALIZED ACCESS TIMEvs. SUPPLY VOLTAGE

120

140

100

60

40

20

0.0 1.0 2.0 3.0 4.0

OU

TP

UT

SIN

K C

UR

RE

NT

(m

A)

0

80

OUTPUT VOLTAGE (V)

OUTPUT SINK CURRENTvs. OUTPUT VOLTAGE

0.6

0.4

0.2

0.0

NO

RM

ALI

ZE

D I

CC

NO

RM

ALI

ZE

D I

, I

CC

SB

ICC

ICC

VCC =5.0VVCC =5.0VTA =25°C

VCC =5.0VTA =25°C

ISB

TA =25°C

0.60.8

0

AA 1.3

1.2

VIN =5.0VTA =25°C

1.4

VCC =5.0VVIN =5.0V

−55 25 105

2.5

2.0

1.5

CURRENTvs. AMBIENT TEMPERATURE


1.0

0.5

0.0

-0.5

ISB

3.0

STANDBY

VCC =5.0VVIN =5.0V

I SB

2 µA

Document #: 38-05248 Rev. ** of 13

CY62256

Typical DC and AC Characteristics (continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0 1.0 2.0 3.0 4.0

NO

RM

ALI

ZE

D I

PO

SUPPLY VOLTAGE (V)

TYPICAL POWER-ON CURRENTvs. SUPPLY VOLTAGE

30.0

25.0

20.0

15.0

10.0

5.0

0 200 400 600 800

DE

LTA

t

(n

s)A

A

CAPACITANCE (pF)

TYPICAL ACCESS TIME CHANGEvs. OUTPUT LOADING

1.25

1.00

0.75

10 20 30 40

NO

RM

ALI

ZE

D I C

C

CYCLE FREQUENCY (MHz)

NORMALIZED ICC vs.CYCLETIME

0.05.0

0.01000

0.50

VCC =4.5VTA =25°C

VCC =5.0VTA =25°CVIN =0.5V

Truth Table

CE WE OE Inputs/Outputs Mode Power

H X X High Z Deselect/Power-Down Standby (ISB)

L H L Data Out Read Active (ICC)

L L X Data In Write Active (ICC)

L H H High Z Deselect, Output Disabled Active (ICC)

Document #: 38-05248 Rev. ** of 13

CY62256

Ordering Information

Speed(ns) Ordering Code

PackageName Package Type

OperatingRange

55 CY62256LL−55SNI S21 28-Lead (300-Mil) Molded SOIC Industrial

CY62256LL−55ZI Z28 28-Lead Thin Small Outline Package

70 CY62256−70SNC S21 28-Lead (300-Mil) Molded SOIC Commercial

CY62256L−70SNC S21

CY62256LL−70SNC S21

CY62256L–70SNI S21 Industrial

CY62256LL−70SNI S21

CY62256LL−70ZC Z28 28-Lead Thin Small Outline Package Commercial

CY62256LL−70ZI Z28 Industrial

CY62256−70PC P15 28-Lead (600-Mil) Molded DIP Commercial

CY62256L−70PC P15

CY62256LL−70PC P15

CY62256LL−70ZRI ZR28 28-Lead Reverse Thin Small Outline Package Industrial

Package Diagrams

51-85017-A

28-Lead (600-Mil) Molded DIP P15

Document #: 38-05248 Rev. ** of 13

CY62256

Package Diagrams (continued)

28-Lead (300-Mil) Molded SOIC S21

51-85026-A

28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28

51-85071-*G

Document #: 38-05248 Rev. ** of 13

CY62256

Package Diagrams (continued)

51-85074-*F

28-Lead Reverse Type 1 Thin Small Outline Package (8x13.4 mm) ZR28

Document #: 38-05248 Rev. ** of 13© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorizeits products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of CypressSemiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY62256

Document Title: CY62256 32K x 8 Static RAMDocument Number: 38-05248

REV. ECN NO. Issue Date Orig. of Change Description of Change

** 113454 03/06/02 MGN Change from Spec number: 38-00455 to 38-05248Remove obsolete parts from ordering info,standardize format

Document #: 38-05248 Rev. ** of 13

Cy 62256

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