CROW - safari.ethz.ch · 21 CROW-ref Problem: Refresh has high overheads. Weak rows lead to high...

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Hasan Hassan Minesh Patel Jeremie S. Kim A. Giray Yaglikci Nandita Vijaykumar Nika Mansouri Ghiasi Saugata Ghose Onur Mutlu CROW A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability Presented at ISCA 2019

Transcript of CROW - safari.ethz.ch · 21 CROW-ref Problem: Refresh has high overheads. Weak rows lead to high...

Page 1: CROW - safari.ethz.ch · 21 CROW-ref Problem: Refresh has high overheads. Weak rows lead to high refresh rate •weak row: at least one of the row’s cells cannot retain data correctly

Hasan HassanMinesh Patel Jeremie S. Kim A. Giray Yaglikci Nandita Vijaykumar

Nika Mansouri Ghiasi Saugata Ghose Onur Mutlu

CROWA Low-Cost Substrate for Improving

DRAM Performance, Energy Efficiency, and Reliability

Presented at ISCA 2019

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SummaryChallenges of DRAM scaling:

• High access latency → bottleneck for improving system performance/energy

• Refresh overhead → reduces performance and consume high energy

• Exposure to vulnerabilities (e.g., RowHammer)

Copy-Row DRAM (CROW)• Introduces copy rows into a subarray

• The benefits of a copy row:

• Efficiently duplicating data from regular row to a copy row

• Quick access to a duplicated row

• Remapping a regular row to a copy row

CROW is a flexible substrate with many use cases:• CROW-cache & CROW-ref

• Mitigating RowHammer

• We hope CROW enables many other use cases going forward

(20% speedup and consumes 22% less DRAM energy)

regular rows

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Source code available in July:github.com/CMU-SAFARI/CROW

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Outline1. DRAM Operation Basics

2. The CROW Substrate

3. Evaluation

4. Conclusion

CROW-cache: Reducing DRAM Latency

CROW-ref: Reducing DRAM Refresh

Mitigating RowHammer

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DRAM Organization

CPU

Memory Controller

DRAM Row

Sense Amplifier

Memory Bus

DRAM Cell

DRAM Subarray

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Accessing DRAM

DRAM Row

Sense Amplifier

DRAM Cell

DRAM Subarray

Activate

Precharge

Read

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Outline1. DRAM Operation Basics

2. The CROW Substrate

3. Evaluation

4. Conclusion

CROW-cache: Reducing DRAM Latency

CROW-ref: Reducing DRAM Refresh

Mitigating RowHammer

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Challenges of DRAM Scaling

DRAM

access latency

refresh overhead

exposure to vulnerabilities

1

2

3

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Our Goal

We want a substrate that enables the duplication and remapping of data within a subarray

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Memory Controller

The Components of CROW

CROW-table

DRAM Subarray

DRAMregular rows

SA SA SA SA SASA

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SA SA SA SA SASA

row

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DRAMregular

rows

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Memory Controller

CROW Operation 1: Row Copy

DRAM Subarray

ACT-c (copy)S

A

SA SA

SA SA

SA

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Row Copy: Steps

SenseAmplifier

source row:

destination row:

1 Activation of the source row

2 Charge sharing

3 Beginning of restoration

4 Activation of the destination row

5Restoration of both rows to source data

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Row Copy: Steps

SenseAmplifier

source row:

destination row:

1 Activation of the source row

2 Charge sharing

3 Beginning of restoration

4 Activation of the destination row

5Restoration of both rows to source data

Enables quickly copying a regular row into a copy row

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Memory Controller

CROW Operation 2: Two-Row Activation

DRAM Subarray

DRAM

ACT-t (two row)

regular rows

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Two-Row Activation: Steps

SenseAmplifier

1 Activation of two rows

2 Charge sharing

3 Restoration

fast

both charged or discharged

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Two-Row Activation: Steps

SenseAmplifier

1 Activation of two rows

2 Charge sharing

3 Restoration

fast

Enables fast access to data that is duplicated across a regular row and a copy row

both charged or discharged

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Outline1. DRAM Operation Basics

2. The CROW Substrate

3. Evaluation

4. Conclusion

CROW-cache: Reducing DRAM Latency

CROW-ref: Reducing DRAM Refresh

Mitigating RowHammer

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CROW-cacheProblem: High access latency

Key idea: Use copy rows to enable low-latency access to most-recently-activated regular rows in a subarray

CROW-cache combines:• row copy → copy a newly activated regular row into a copy row• two-row activation → activate the regular row and copy row

together on the next access

Reduces activation latency by 38%

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Memory Controller

CROW-cache Operationload row X

DRAM

ACT-c

ACT-t

load row X

RequestQueue

1 CROW-table miss

2 Allocate a copy row

3 Issue ACT-c (copy)

1 CROW-table hit

2 Issue ACT-t (two row)

DRAM Subarray

regular rows

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CROW-table

copy row 0 row X

[bank conflict]

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Memory Controller

CROW-cache Operation

DRAM

ACT-t

1 CROW-table miss

2 Allocate a copy row

3 Issue ACT-c

1 CROW-table hit

2 Issue ACT-t

DRAM Subarray

regular rows

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CROW-table

copy row 0 row XSecond activation of row X is faster

load row X

load row X

RequestQueue

[bank conflict]

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Outline1. DRAM Operation Basics

2. The CROW Substrate

3. Evaluation

4. Conclusion

CROW-cache: Reducing DRAM Latency

CROW-ref: Reducing DRAM Refresh

Mitigating RowHammer

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CROW-refProblem: Refresh has high overheads. Weak rows lead to high refresh rate

• weak row: at least one of the row’s cells cannot retain data correctly when refresh rate is decreased

Key idea: Safely reduce refresh rate by remapping a weak regular row to a strong copy row

CROW-ref uses:• row copy → copy a weak regular row to a strong copy row

CROW-ref eliminates more than half of the refresh requests

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CROW-ref Operation

SA SA SA SA SASA SA

SA SA

SA SA

SA

weak

strongRetention Time Profiler

strongstrong

strongstrong

1Perform retention time profiling

3 On ACT, check the CROW-table

4If remapped, activate a copy row

2Remap weak rows to strong copy rows

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CROW-ref Operation

SA SA SA SA SASA SA

SA SA

SA SA

SA

weak

strongRetention Time Profiler

strongstrong

strongstrong

1Perform retention time profiling

3 On ACT, check the CROW-table

4If remapped, activate a copy row

How many weak rows exist in a DRAM chip?

2Remap weak rows to strong copy rows

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Identifying Weak RowsWeak cells are rare [Liu+, ISCA’13]

weak cell: retention < 256ms

~1000/238 (32 GiB) failing cells

DRAM Retention Time Profiler• REAPER [Patel+, ISCA’17]

PARBOR [Khan+, DSN’16]AVATAR [Qureshi+, DSN’15]

• At system boot or during runtime

3.30E-043.30E-11

0%

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Pro

ba

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Weak rows in a subarray

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Identifying Weak RowsWeak cells are rare [Liu+, ISCA’13]

weak cell: retention < 256ms

~1000/238 (32 GiB) failing cells

DRAM Retention Time Profiler• REAPER [Patel+, ISCA’17]

PARBOR [Khan+, DSN’16]AVATAR [Qureshi+, DSN’15]

• At system boot or during runtime

3.30E-043.30E-11

0%

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1 2 4 8

Pro

ba

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Weak rows in a subarrayA few copy rows are sufficient to halve the refresh rate

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Outline1. DRAM Operation Basics

2. The CROW Substrate

3. Evaluation

4. Conclusion

CROW-cache: Reducing DRAM Latency

CROW-ref: Reducing DRAM Refresh

Mitigating RowHammer

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activate

Mitigating RowHammer

SA SA SA SA SASA

victimaggressor

victim

precharge

Key idea: remap victim rows to copy rows

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Outline1. DRAM Operation Basics

2. The CROW Substrate

3. Evaluation

4. Conclusion

CROW-cache: Reducing DRAM Latency

CROW-ref: Reducing DRAM Refresh

Mitigating RowHammer

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Methodology• Simulator

• DRAM Simulator (Ramulator [Kim+, CAL’15])https://github.com/CMU-SAFARI/ramulator

• Workloads• 44 single-core workloads

• SPEC CPU2006, TPC, STREAM, MediaBench• 160 multi-programmed four-core workloads

• By randomly choosing from single-core workloads• Execute at least 200 million representative instructions per core

• System Parameters• 1/4 core system with 8 MiB LLC• LPDDR4 main memory• 8 copy rows per 512-row subarray

Source code available in July:github.com/CMU-SAFARI/CROW

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0.86

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Spee

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pCROW-cache Results

7.1%7.5%8.2% 6.9%

* with 8 copy rows and a 64Gb DRAM chip (sensitivity in paper)

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0.86

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pCROW-cache Results

7.1%7.5%8.2% 6.9%

* with 8 copy rows a 64Gb DRAM chip (sensitivity in paper)

CROW-cache improves single-/four-core performance and energy

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1.041.051.061.071.081.09

1.11.111.121.13

single-core four-core

Spee

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pCROW-ref Results

17.2%

7.8%

7.1%

11.9%

* with 8 copy rows and a 64Gb DRAM chip (sensitivity in paper)

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Spee

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pCROW-ref Results

17.2%

7.8%

7.1%

11.9%

* with 8 copy rows a 64Gb DRAM chip (sensitivity in paper)

CROW-ref significantly reduces the performance and energy overhead of DRAM refresh

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Combining CROW-cache and CROW-ref

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Ideal CROW-cache + no refresh

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Combining CROW-cache and CROW-ref

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Ideal CROW-cache + no refresh

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CROW-(cache+ref) provides more performance and DRAM energy benefits than each mechanism alone

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Hardware Overhead

For 8 copy rows and 16 GiB DRAM:•0.5% DRAM chip area•1.6% DRAM capacity•11.3 KiB memory controller storage

CROW is a low-cost substrate

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Other Results in the Paper• Performance and energy sensitivity to:

• Number of copy-rows per subarray

• DRAM chip density

• Last-level cache capacity

• CROW-cache with prefetching

• CROW-cache compared to other in-DRAM caching mechanisms:• TL-DRAM [Lee+, HPCA’13]

• SALP [Kim+, ISCA’12]

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Outline1. DRAM Operation Basics

2. The CROW Substrate

3. Evaluation

4. Conclusion

CROW-cache: Reducing DRAM Latency

CROW-ref: Reducing DRAM Refresh

Mitigating RowHammer

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ConclusionChallenges of DRAM scaling:

• High access latency → bottleneck for improving system performance/energy

• Refresh overhead → reduces performance and consume high energy

• Exposure to vulnerabilities (e.g., RowHammer)

Copy-Row DRAM (CROW)• Introduces copy rows into a subarray

• The benefits of a copy row:

• Efficiently duplicating data from regular row to a copy row

• Quick access to a duplicated row

• Remapping a regular row to a copy row

CROW is a flexible substrate with many use cases:• CROW-cache & CROW-ref

• Mitigating RowHammer

• We hope CROW enables many other use cases going forward

(20% speedup and consumes 22% less DRAM energy)

regular rows

SA SA SA SA SASA

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der copy rows

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Source code available in July:github.com/CMU-SAFARI/CROW

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Hasan HassanMinesh Patel Jeremie S. Kim A. Giray Yaglikci Nandita Vijaykumar

Nika Mansouri Ghiasi Saugata Ghose Onur Mutlu

CROWA Low-Cost Substrate for Improving

DRAM Performance, Energy Efficiency, and Reliability

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Backup Slides

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Latency Reduction with MRA

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activate

Mitigating RowHammer

SA SA SA SA SASA

victimaggressor

victim

precharge

Key idea: remap victim rows to copy rows

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0.900.951.001.051.101.151.20

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pCROW-1 CROW-8

CROW-64 CROW-128

Ideal CROW-cache (100% Hit Rate)

CROW-cache Performance

6.6%

0.7%7.1%

single-core four-core

7.5%

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p8 Gbit 16 Gbit 32 Gbit 64 Gbit

CROW-ref Performance

7.1%

single-core

11.9%

four-coresingle-core four-core

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CROW-ref Energy Savings

17.2%

single-core four-core

7.8%

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Speedup - CROW-cache

Single-core

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Speedup - CROW-cache

Four-core

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Energy – CROW-cache

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Comparison to TL-DRAM and SALP

CROW-1

CROW-8

TL-DRAM-1

TL-DRAM-8

SALP-512

SALP-256

SALP-128

SALP-512-O

SALP-256-O

SALP-128-O

0.60.81.01.21.41.61.82.02.2

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Speedup

CROW-1CROW-8

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SALP-256-O

SALP-128-O

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Speedup

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Slide on RLTL

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52

Speedup – CROW-ref

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53

Energy – CROW-ref

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54

CROW-cache + ref

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55

CROW-table Organization

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56

tRCD vs tRAS

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57

MRA Area Overhead

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Data 0

Data 1

Cell

time

cha

rge

Sense-Amplifier

Sensing Restore

Cell

SenseAmplifier

Precharge

R/WACT PRE

Ready to AccessCharge Level

tRCD

tRAS

Ready to AccessReady to

Precharge

DRAM Charge over Time