Computer Aided System Design FPGA Lab - 台大電機系...
Transcript of Computer Aided System Design FPGA Lab - 台大電機系...
-
ComputerAidedVLSISystemDesignFPGALab
ALTERAQuartusIIWebEditionSoftware USBBlasterDriver USB FPGA
-
ALTERAQuartusIIWebEditionSoftware
1. IE ALTERAQuartusIIWebEditionSoftware
https://www.altera.com/download/software/quartusiiwe
QuartusIIWebEditionv10.1forWindows(3.0GB)
2. emailaddress CreateAccount
-
3. * emailaddress
CreateAccount
-
4. email Continue
5.
SignIn
-
6. SignIn
7.
8.
-
9. Install
10. Extracting
-
11.Extracting Next
-
12. Iagreetothetermsofthelicenseagreement Next
-
13. Next
-
14. Next
-
15. Next
-
16.
-
17. OK
-
18. Finish
QuartusII
()
-
USBBlasterDriver USB FPGA
1. (1) USB(2)
2. FPGA(3) FPGA USB
2
1
3
-
3.
4. driver
C:\altera\10.1\quartus\drivers\usbblaster
-
5.
-
6.
-
1. OpenQuartusII10.1WebEdition(32Bit)2. File>Newprojectwizard
3.Thenameoftopmodulemustbethesameasyourverilogcode!
-
4.
5.SelecttheFPGAyouaregoingtouse
Inthislab,chooseFamily:CycloneII,andforDE270chooseEP2C70F896C6
Whereyourprojectissaved
ProjectName
TopmoduleName
Alwaysthesame!
1. FindyourVerilogfile2. Addintoyourproject
3. PressNext
-
6.Pressthestartcompilation(Ctrl+L)
7.Use Pin Planner to plan the input and output in your FPGA. In otherwords,
connectyourverilogcodeandFPGAbysettingthelocationofeachI/Oaccordingto
theusermanualofFPGA.
-
DE270
Clk PIN_D16
out1[7] PIN_AE8
out1[6] PIN_AF9
out1[5] PIN_AH9
out1[4] PIN_AD10
out1[3] PIN_AF10
out1[2] PIN_AD11
out1[1] PIN_AD12
out1[0] PIN_AF12
out2[7] PIN_AG13
out2[6] PIN_AE16
out2[5] PIN_AF16
out2[4] PIN_AG16
out2[3] PIN_AE17
out2[2] PIN_AF17
out2[1] PIN_AD17
out2[0] PIN_AC17
pause PIN_AB26
rst PIN_AA23
Plantheinputandoutput
inyourFPGA
-
ExampleforDE270:
8.Afterpinplanner,anothercompilationisrequired!
-
9.Next,useProgrammerfrom"tool programmer"
-
10.YoumustfirstconnectyourFPGAandchooseHardwaresetup>USBBlaster.
11.PressStartandFPGAwillstarttowork!
1.
2.
-
12.Counteriscounting! (SW0>reset,SW1>pause)
-
ExercisesAddoneoutputportwhichlightstheLEDR0whenthecounteriscountingand
turnsofftheLEDR0whenthecounterisnotcounting.