Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency Bo Fu and Paul Ampadu...
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Transcript of Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency Bo Fu and Paul Ampadu...
Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency
Bo Fu and Paul Ampadu IEEE International Symposium on Circuits and Systems,pp.1173-1176, 27-30 May 2007
指導老師 : 魏凱城 老師 學 生 : 蕭荃泰 日 期 : 97 年 3 月 3 日
彰化師範大學積體電路設計研究所
Outline
Abstract Flip Flop Design Metrics Experimental Setup Simulation Results Conclusions
Abstract In this paper, the impact of voltage scaling on the
performance of flip-flops is analyzed.
Four representative flip-flops are compared at ultra-low voltages, for delay, energy and energy-delay-product (EDP).
Voltage scaling has become one of the most effective techniques to reduce system energy consumption.
Flip Flop Design Metrics PowerPC Master-slaver latch
0
1 0
1
0
01
1
Modified Clock CMOS (mC2MOS) Master-slave latch
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
1
Hybrid-latch Flip Flop (HLFF)
011
0
1
1
0
0
1
1
Sense-Amplifier-based Flip Flop (SAFF)
01
Q 不變
10
設 =1 0
11
10
0
1
1
0Q 改變
Timing parameters Definition of Tsetup
Experimental Setup
The simulation test bench.
Simulation Results Experiments were performed using the 90 nm
Predictive Technology Model (PTM) [11] at room temperature (27oC).
The flip-flops are optimized for minimum energy at a nominal supply voltage 1.2 V using the sizing schemes mentioned in [4].
a. Effects of Voltage Scaling on Timing Parameters
Supply voltages of various flip-flop designs failing tolatch the proper data
(a) Function failure voltages (b) Function failure in HLFF
Low-to-high Low-to-highHigh-to-low High-to-low(a) TC->Q (b) Tsetup
Timing parameters of the flip-flop as a function of the supply voltage.
(c) Worst case delay of TD->Q
Timing parameters of the flip-flop as a function of the supply voltage.
(a) Supply voltage 1.2 V (b) Supply voltage 0.3 V
High-to-low transition of HLFF with a varied TD->C time.
b. Effect of Voltage Scaling on Energy Consumption
The energy dissipation of selected flip-flop designs from 0.3 V to 1.2 V with a clock frequency of 50 MHz.
The result shows that PowerPC consumes the least energy compared to other flip-flops examined.
(a) Activity 1 (b) Activity 0.5
Energy dissipation as a function of the supply voltage fordifferent switching activities.
(c) Activity 0 (all 1) (d) Activity 0 (all 0)
Energy dissipation as a function of the supply voltage fordifferent switching activities.
c. Effect of Voltage Scaling on Energy-Delay Product
(a) Activity 1 (b) Activity 0 (all 1)
EDP as a function of supply voltage and switching activities.
EDP as a function of supply voltage and switching activities.
(c) Voltage 1.2 V (d) Voltage 0.3 V
Conclusions The performance of various flip-flops at ultra-low
voltages was analyzed in this paper.
The impact of supply voltage scaling on timing parameters of a flip-flop depends on the type of flip-flop and input transition.
For energy efficient operation at ultra-low voltages, HLFF achieves the smallest EDP when switching activity is high and a transistor based flip-flop achieves the smallest EDP at low switching activities.
THE END