Chapter 4

Combinational Logic

授課教師 : 張傳育 博士 (Chuan-Yu Chang Ph.D.)E-mail: chuanyu@yuntech.edu.twTel: (05)5342601 ext. 4337Office: EB212

2Digital Circuits

4.1 Introduction

Logic circuits for digital systems may be combinational or sequential.

A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs.

3Digital Circuits

4.2 Combinational Circuits

Logic circuits for digital system Sequential circuits

contain memory elements the outputs are a function of the current inputs and the

state of the memory elements the outputs also depend on past inputs

4Digital Circuits

A combinational circuits 2

n possible combinations of input values

Specific functions Adders, subtractors, comparators, decoders, encoders,

and multiplexers They are available in IC as MSI circuits or standard cells

CombinationalLogic Circuit

n inputvariables

m outputvariables

5Digital Circuits

4-3 Analysis Procedure

A combinational circuit make sure that it is combinational not sequential

No feedback path derive its Boolean functions (truth table) design verification a verbal explanation of its function

6Digital Circuits

4-3 Analysis Procedure

To obtain the output Boolean functions from a logic diagram Label all gate outputs that are a function of input

variables with arbitrary symbols Label the gates that are a function of input

variables and previously labeled gates with other arbitrary symbols.

Repeat the process outlined in step 2 until the outputs of the circuit are obtained.

By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables.

7Digital Circuits

Example: A straight-forward procedure

F2 = AB+AC+BCT1 = A+B+CT2 = ABCT3 = F2'T1

F1 = T3+T2

8Digital Circuits

Example: A straight-forward procedure (cont.)

F1 = T3+T2 = F2'T1+ABC = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C')(B'+C')(A+B+C)

+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B'C+AB'C'+ABC

A full-adder F1: the sum

F2: the carry

9Digital Circuits

Example: A straight-forward procedure (cont.)

To obtain the truth table directly from the logic diagram without going through the derivations of the Boolean functions:

Determine the number of input variables in the circuit. Label the outputs of selected gates with arbitrary symbols. Obtain the truth table for the outputs of those gates which

are a function of the input variables only. Proceed to obtain the truth table for the outputs of those

gates which are a function of previously defined values until the columns for all outputs are determined.

10Digital Circuits

Example: A straight-forward procedure (cont.)

The truth table

11Digital Circuits

4-4 Design Procedure

The design procedure of combinational circuits State the problem (system spec.) determine the inputs and outputs the input and output variables are assigned symbols derive the truth table derive the simplified Boolean functions draw the logic diagram and verify the correctness

12Digital Circuits

4-4 Design Procedure (cont.)

Functional description Boolean function HDL (Hardware description language)

Verilog HDL VHDL

Schematic entry Logic minimization

number of gates number of inputs to a gate propagation delay number of interconnection limitations of the driving capabilities

13Digital Circuits

Code conversion example BCD to excess-3 code

The truth table

14Digital Circuits

The maps

15Digital Circuits

Code conversion example (cont.)

The simplified functions z = D'

y = CD +C'D' x = B'C + B'D+BC'D'

w = A+BC+BD Another implementation

z = D' y = CD +C'D'= CD + (C+D)' x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)'

w = A+BC+BD

16Digital Circuits

The logic diagram

17Digital Circuits

4-5 Binary Adder-Subtractor

Half adder 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10 two input variables: x, y two output variables: C (carry), S (sum) truth table

18Digital Circuits

4-5 Binary Adder-Subtractor (cont.)

S = x'y+xy' C = xy

the flexibility for implementation S=xy S = (x+y)(x'+y') S' = xy+x'y'

S = (C+x'y')' C = xy = (x'+y')'

19Digital Circuits

20Digital Circuits

Full-Adder The arithmetic sum of three input bits three input bits

x, y: two significant bits z: the carry bit from the previous lower significant bit

Two output bits: C, S

21Digital Circuits

22Digital Circuits

S = x'y'z+x'yz'+ xy'z'+xyz C = xy + xz + yz

S = z (xy)= z'(xy'+x'y)+z(xy'+x'y)'

= z'xy'+z'x'y+z((x'+y)(x+y'))= xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy

= xy'z+x'yz+ xy

23Digital Circuits

Binary adder

24Digital Circuits

Carry propagation

Carry propagation when the correct outputs are available the critical path counts (the worst case) (A1,B1,C1) > C2 > C3 > C4 > (C5,S4) > 8 gate levels

25Digital Circuits

Carry propagation (cont.)

Reduce the carry propagation delay employ faster gates look-ahead carry (more complex mechanism, yet

faster)

26Digital Circuits

Carry propagation (cont.)

由全加器推導 Si= Ai’Bi’Ci+Ai’BiCi’+AiBi’Ci’+AiBiCi

= (Ai’Bi’+AiBi)Ci+(Ai’Bi+AiBi’)Ci’

Ci+1= AiBiCi’+AiBiCi+Ai’BiCi+AiBi’Ci

=AiBi (Ci’+Ci) +(Ai’Bi+AiBi’)Ci

令 carry propagate: Pi = (Ai’Bi+AiBi’)= AiBi

carry generate: Gi = AiBi

則 sum: Si = PiCi

carry: Ci+1 = Gi+PiCi C1 = G0+P0C0

C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0

C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

27Digital Circuits

Logic diagram

28Digital Circuits

4-bit carry-look ahead adder propagation delay

29Digital Circuits

Binary subtractor A-B = A+(2’s complement of B) 4-bit Adder-subtractor

M=0, A+B; M=1, A+B’+1

30Digital Circuits

Overflow The storage is limited Add two positive numbers and obtain a negative number Add two negative numbers and obtain a positive number In binary adder-subtractor circuit:

V = 0, no overflow; V = 1, overflow Observing the carry into the sign bit position and the carry

out of the sign bit position. If these two carries are not equal, an overflow has occurred. XOR

Example:

31Digital Circuits

4-6 Decimal Adder

Add two BCD's 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out

Design approaches A truth table with 29 entries Use binary full Adders

the sum <= 9 + 9 + 1 = 19 binary to BCD

32Digital Circuits

BCD Adder: The truth table

33Digital Circuits

BCD Adder

Modifications are needed if the sum > 9 C = 1

K = 1 Z8Z4 = 1

Z8Z2 = 1

modification: (10)d or +6

C = K +Z8Z4 + Z8Z2

34Digital Circuits

Block diagram

35Digital Circuits

Binary Multiplier Partial products

– AND operations

Fig. 4.15 Two-bit by two-bit binary multiplier.

36Digital Circuits

For J multiplier bits and K multiplicand bits, we need (J*K) AND gates and (J-1) K bit adders to produce a product of J+K bits.

Fig. 4.16 Four-bit by three-bit binary multiplier.

4-bit by 3-bit binary multiplier

37Digital Circuits

4-8 Magnitude Comparator

A magnitude comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitudes. outputs: A>B, A=B, A<B

Design Approaches the truth table

22n

entries - too cumbersome for large n use inherent regularity of the problem

reduce design efforts reduce human errors

38Digital Circuits

Magnitude Comparator (cont.)

Algorithm -> logic Consider two numbers: A = A3A2A1A0 ; B = B3B2B1B0

A=B if A3=B3, A2=B2, A1=B1and A0=B0

equality: xi= AiBi+Ai'Bi'

(A=B) = x3x2x1x0

從最大有效位元開始往右依序比較，直到不相等的位元

(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'

(A>B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0

Implementation xi = (AiBi'+Ai'Bi)'

39Digital Circuits

Fig. 4.17Four-bit magnitude comparator.

XNOR

40Digital Circuits

4-9 Decoder A n-to-m decoder

a binary code of n bits = 2n distinct information

n input variables; up to 2n output lines

only one output can be active (high) at any time

41Digital Circuits

An implementation

Fig. 4.18 Three-to-eight-line decoder.

’

42Digital Circuits

Decoder (cont.)

Combinational logic implementation each output = a minterm use a decoder and an external OR gate to

implement any Boolean function of n input variables

43Digital Circuits

Combination Logic Implementation

each output = a minterm use a decoder and an external OR gate to

implement any Boolean function of n input variables

A full-adder S(x,y,z)=(1,2,4,7)

C(x,y,z)= (3,5,6,7)

Fig. 4.21 Implementation of a full adder with a decoder

44Digital Circuits

Combination Logic Implementation

two possible approaches using decoder OR (minterms of F): k inputs NOR (minterms of F'): 2

n k inputs

In general, it is not a practical implementation

45Digital Circuits

Expansion two 3-to-8 decoder: a 4-to-16 decoder

a 5-to-32 decoder?

Fig. 4.20 4 16 decoder constructed with two 3 8 decoders

46Digital Circuits

4-10 Encoders The inverse function of

a decoder

1 3 5 7

2 3 6 7

4 5 6 7

z D D D D

y D D D D

x D D D D

The encoder can be implemented with three OR gates.

47Digital Circuits

An implementation

limitations illegal input: e.g. D3=D6=1 the output = 111 (¹3 and ¹6) 第三版內容，參考用 !

48Digital Circuits

Priority Encoder resolve the ambiguity of illegal inputs only one of the input is encoded

D3 has the highest priority D0 has the lowest priority X: don't-care conditions V: valid output indicator

49Digital Circuits

■ The maps for simplifying outputs x and y

Fig. 4.22 Maps for a priority encoder

1

50Digital Circuits

■ Implementation of priority

Fig. 4.23 Four-input priority encoder

2 3

3 1 2

0 1 2 3

x D D

y D D D

V D D D D

51Digital Circuits

4-11 Multiplexers Select binary information from one of many input

lines and direct it to a single output line 2

n input lines, n selection lines and one output line

e.g.: 2-to-1-line multiplexer

Fig. 4.24 Two-to-one-line multiplexer

52Digital Circuits

4-to-1-line multiplexer

Fig. 4.25 Four-to-one-line multiplexer

Decoder

53Digital Circuits

Multiplexers (cont.)

Note n-to- 2

n decoder

add the 2n input lines to each AND gate

OR(all AND gates) an enable input (an option)

54Digital Circuits

Fig. 4.26 Quadruple two-to-one-line multiplexer

55Digital Circuits

Boolean function implementation

MUX: a decoder + an OR gate 2

n-to-1 MUX can implement any Boolean function

of n input variable

a better solution: implement any Boolean function of n+1 input variable

n of these variables: the selection lines the remaining variable: the inputs

56Digital Circuits

an example: F(x,y,z) = (1,2,6,7)

Fig. 4.27 Implementing a Boolean function with a multiplexer

57Digital Circuits

Boolean Function Implementation

Procedure: Assign an ordering sequence of the input variable The rightmost variable (D) will be used for the input

lines Assign the remaining n-1 variables to the selection

lines w.r.t. their corresponding sequence Construct the truth table Consider a pair of consecutive minterms starting

from m0

Determine the input lines

58Digital Circuits

Fig. 4.28 Implementing a four-input function with a multiplexer

Example: F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

59Digital Circuits

Three-state gates

A multiplexer can be constructed with three-state gates

Output state: 0, 1, and high-impedance (open ckts)

Fig. 4.29 Graphic symbol for a three-state buffer

60Digital Circuits

Example: Four-to-one-line multiplexer

Fig. 4.30 Multiplexer with three-state gates

61Digital Circuits

Demultiplexers a decoder with an enable input receive information on a single line and transmits it

on one of 2n possible output lines

Fig. 4.19 Two-to-four-line decoder with enable input

0

62Digital Circuits

Demultiplexers (cont.)

Decoder/demultiplexers

第三版內容，參考用 !

63Digital Circuits

4-12 HDL Models of Combinational Circuits

▓ Modeling Styles:

64Digital Circuits

Gate-level Modeling

▓ The four-valued logic truth tables for the and, or, xor, and not primitives

65Digital Circuits

Gate-level Modeling

Example:

output [0: 3] D;wire [7: 0] SUM;

1. The first statement declares an output vector D with four bits, 0 through 3.

2. The second declares a wire vector SUM with eight bits numbered 7 through 0.

66Digital Circuits

HDL Example 4-1

■ Two-to-one-line decoder

67Digital Circuits

HDL Example 4-2

■ Four-bit adder: bottom-up hierarchical description

68Digital Circuits

HDL Example 4-2 (continued)

69Digital Circuits

Three-State Gates

■ Statement:

gate name (output, input, control);

Fig. 4.31 Three-state gates

70Digital Circuits

Three-State Gates

■ Examples of gate instantiation

71Digital Circuits

Fig. 4.32 Two-to-one-line multiplexer with three-state buffers

72Digital Circuits

Dataflow Modeling

■ Verilog HDL operators

Example:

assign Y = (A & S) | (B & ~S)

73Digital Circuits

HDL Example 4.3

Dataflow description of a 2-to-4-line decoder

74Digital Circuits

HDL Example 4-4

Dataflow description of 4-bit adder

75Digital Circuits

HDL Example 4-5

Dataflow description of 4-bit magnitude comparator

76Digital Circuits

HDL Example 4-6

Dataflow description of a 2-to-1-line multiplexer

Conditional operator (?:)

Condition ? True-expression : false-expression

Example: continuous assignment

assign OUT = select ? A : B

77Digital Circuits

Behavioral Modeling

if statement:if (select) OUT = A;

Behavioral description of a 2-to-1-line multiplexer

HDL Example 4-7

78Digital Circuits

HDL Example 4-8

Behavioral description of a 4-to-1-line multiplexer

79Digital Circuits

Writing a Simple Test Bench

initial block

Three-bit truth table

80Digital Circuits

Writing a Simple Test Bench

Interaction between stimulus and design modules

81Digital Circuits

Writing a Simple Test Bench

Stimulus module

System tasks for display

82Digital Circuits

Syntax for $dispaly, $write, and $monitor:

Example:

Example:

83Digital Circuits

HDL Example 4-9

Stimulus module

84Digital Circuits

HDL Example 4-9 (Continued)

85Digital Circuits

HDL Example 4-10

Gate-level description of a full adder

86Digital Circuits

HDL Example 4-10 (Continued)