HUAWEI TECHNOLOGIES CO., LTD.

47pt

30pt

反白

:

FrutigerNext LT Medium

: Arial

47pt

黑体

28pt

反白

细黑体

IEEE 802.3bs 400 GbE Task Force

2014/7/9

Tongtong Wang, Xinyuan Wang, Wenbin Yang

BER/FLR Calculation Results for Multiplexing in PMA

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

Background

Page 2

MAC/RS

400G PCS

The same color

lanes from sub-

FECs distribute to

different Mux/Demux

group.

PMD

Medium

MDI

2nd

stage PMA[16:4/8]

or PMA[8:4] in module

1st stage

PMA[16:16] in PCS

Optical Module

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

Each bit mux block based on 4/2 electrical lanes from different sub-FEC

Bit muxBit mux Bit muxBit mux Bit mux Bit muxBit mux Bit mux

Based on evaluation method presented in May, (wang_t_3bs_01_0514), FEC

performance with different burst error factors are explored; BERin requirements are listed for

reference.

KR4/KP4 FEC performance with all muxing methods are explored for comparison.

Have minor updates on calculation method.

Four muxing methods under investigation:

Orthogonal symbol mux

Orthogonal bit mux

Non-orthogonal symbol mux

Non-orthogonal bit mux

Analysis of reusing gearbox for 400GbE and

4x100GbE, from BER performance perspective.

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

Updates in Calculation

For FEC incorporated 400GbE, FLR(frame loss rate) is more

practical in evaluating MTTFPA performance. So we also use FLR

equations from BER,

http://www.ieee802.org/3/400GSG/public/adhoc/logic/jun26_13/anslow_01_0613_logic.pdf

Update calculation programs

Use SERin instead of BERin as function is based on symbols as well

Page 3

1 1 1 1

* ( 1)* ( ) * ( )* ( )* ( ) * ( )* ( )* ( )* ( ) ... * ( )* ( )1 2 3

t t t i n

post

i i j i t

n n n nBER M t W E G i M t i W E G i G j M t i W E G i W E

i

Probability of having a single burst error longer than t+1 symbols

Probability of having two burst error whose total length is longer than t+1 symbols

Probability of having three burst error whose total length is longer than t+1 symbols

Probability of having more than

t+1 separate burst errors

i

n

nC

i

Or approximately

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

BER Evaluation (1)

Page 4

RS FEC b mux 2:1

FOM symbol mux FOM bit mux Non-FOM symbol mux Non-FOM bit mux

RS(528,514) b=0.1 3.75E-05 3.75E-05 3.56E-05 1.42E-05

b=0.5 3.75E-05 2.19E-05 2.07E-05 2.38E-06

RS(544,514) b=0.1 3.09E-04 3.09E-04 3.09E-04 2.23E-04

b=0.5 3.09E-04 2.93E-04 2.63E-04 8.45E-05

BERin requirements for 2:1 mux are listed, assuming rllmax = 4bits

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

BER Evaluation (2)

Page 5

RS FEC b mux 2:1

FOM symbol mux FOM bit mux Non-FOM symbol mux Non-FOM bit mux

RS(528,514) b=0.1 3.75E-05 3.75E-05 3.56E-05 1.42E-05

b=0.5 3.75E-05 1.86E-05 1.58E-05 1.25E-06

RS(544,514) b=0.1 3.09E-04 3.09E-04 3.09E-04 2.23E-04

b=0.5 3.09E-04 2.77E-04 2.23E-04 6.44E-05

BERin requirements for 2:1 mux are listed, assuming rllmax = 17bits

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

BER Evaluation (3)

Page 6

RS FEC b mux 4:1

FOM Symbol mux FOM bit mux Non-FOM symbol mux Non-FOM bit mux

RS(528,514) b=0.1 3.75E-05 3.75E-05 3.56E-05 4.10E-06

b=0.5 3.75E-05 3.56E-05 1.58E-05 2.42E-08

RS(544,514) b=0.1 3.09E-04 3.09E-04 2.93E-04 1.70E-04

b=0.5 3.09E-04 3.09E-04 2.23E-04 1.14E-05

BERin requirements for 4:1 mux are listed, assuming rllmax = 17bits

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

Effect of Parameters

b: “Prob of continuous error after a initial error bit”

Smaller value of b, less probability for burst errors

Rllmax : “maximum burst error length”

Larger rllmax increases probability for burst errors

Example with FOM bit mux 2:1 With different value of b and rllmax

Page 7

FOM bitmux with b=0.5/0.1, rll=17/4

For RSFEC(528,514)

FOM bitmux with b=0.5/0.1, rll=17/4

For RSFEC(544,514)

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

PMD

MAC/RS

400G PCS

Medium

MDI

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

Each bit mux block based on 4/2 electrical lanes from different sub-FEC

Bit muxBit mux Bit muxBit mux Bit mux Bit muxBit mux Bit mux

MDI

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

Each bit mux block based on 4/2 electrical lanes from one sub-FEC

Bit muxBit mux Bit muxBit mux Bit mux Bit muxBit mux Bit mux

802.3ba

PCS

802.3ba

PCS

802.3ba

PCS

802.3ba

PCS

802.3ba

MAC/RS

802.3ba

MAC/RS

802.3ba

MAC/RS

802.3ba

MAC/RS

100GbE

PMD

100GbE

PMD

100GbE

PMD

100GbE

PMD

Two 50Gbps Optical Link

Bit Demux

1:2

00.200.3

00.500.4

80.080.1

80.380.2

40.0

40.240.1

80.480.5

40.3

40.540.4

120.0120.1

120.3120.2

00.100.0

120.5120.4

00.2

00.3

00.5

00.4

80.1

80.3

80.240.3

40.2

80.4

80.5

40.4

40.6

40.5

120.0

120.1

120.3

120.2

00.1

00.0

120.5

120.4

00.2

00.3

00.5

00.4

80.1

80.3

80.2

40.1

40.3

40.2

80.4

80.5

40.4

40.6

40.5

120.0

120.1

120.3

120.2

00.1

00.0

120.5

120.4

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

Bit Mux

2:1

00.200.3

00.500.4

80.080.1

80.380.2

40.0

40.240.1

80.480.5

40.3

40.540.4

120.0120.1

120.3120.2

00.100.0

120.5120.4

Egress PCS/PMA

FEC0 FEC1 FEC2 FEC3

4X25Gbps FEC

symbol lanes

from 4 Sub-FECs

TX:CDAUI-16

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

Ingress PCS/PMA

FEC0 FEC1 FEC2 FEC3

AM lock

Alignment and Reorder

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

RX:CDAUI-16

4X25Gbps FEC symbol

lanes to 4 Sub-FECs

40.780.6

80.6

Two 50Gbps Optical Link

Bit Demux

1:2

00.200.3

00.500.4

80.080.1

80.380.2

40.0

40.240.1

80.480.5

40.3

40.540.4

120.0120.1

120.3120.2

00.100.0

120.5120.4

00.2

00.3

00.5

00.4

80.1

80.3

80.240.3

40.2

80.4

80.5

40.4

40.6

40.5

120.0

120.1

120.3

120.2

00.1

00.0

120.5

120.4

00.2

00.3

00.5

00.4

80.1

80.3

80.2

40.1

40.3

40.2

80.4

80.5

40.4

40.6

40.5

120.0

120.1

120.3

120.2

00.1

00.0

120.5

120.4

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

Bit Mux

2:1

00.200.3

00.500.4

80.080.1

80.380.2

40.0

40.240.1

80.480.5

40.3

40.540.4

120.0120.1

120.3120.2

00.100.0

120.5120.4

Egress PCS/PMA

FEC0 FEC1 FEC2 FEC3

4X25Gbps FEC

symbol lanes

from 4 Sub-FECs

TX:CDAUI-16

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

Ingress PCS/PMA

FEC0 FEC1 FEC2 FEC3

AM lock

Alignment and Reorder

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

RX:CDAUI-16

4X25Gbps FEC symbol

lanes to 4 Sub-FECs

40.780.6

80.6

Two 50Gbps Optical Link

Bit Demux

1:2

00.200.3

00.500.4

80.080.1

80.380.2

40.0

40.240.1

80.480.5

40.3

40.540.4

120.0120.1

120.3120.2

00.100.0

120.5120.4

00.2

00.3

00.5

00.4

80.1

80.3

80.240.3

40.2

80.4

80.5

40.4

40.6

40.5

120.0

120.1

120.3

120.2

00.1

00.0

120.5

120.4

00.2

00.3

00.5

00.4

80.1

80.3

80.2

40.1

40.3

40.2

80.4

80.5

40.4

40.6

40.5

120.0

120.1

120.3

120.2

00.1

00.0

120.5

120.4

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

Bit Mux

2:1

00.200.3

00.500.4

80.080.1

80.380.2

40.0

40.240.1

80.480.5

40.3

40.540.4

120.0120.1

120.3120.2

00.100.0

120.5120.4

Egress PCS/PMA

FEC0 FEC1 FEC2 FEC3

4X25Gbps FEC

symbol lanes

from 4 Sub-FECs

TX:CDAUI-16

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

Ingress PCS/PMA

FEC0 FEC1 FEC2 FEC3

AM lock

Alignment and Reorder

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

RX:CDAUI-16

4X25Gbps FEC symbol

lanes to 4 Sub-FECs

40.780.6

80.6

Two 50Gbps Optical Link

Bit Demux

1:2

00.200.3

00.500.4

80.080.1

80.380.2

40.0

40.240.1

80.480.5

40.3

40.540.4

120.0120.1

120.3120.2

00.100.0

120.5120.4

00.2

00.3

00.5

00.4

80.1

80.3

80.240.3

40.2

80.4

80.5

40.4

40.6

40.5

120.0

120.1

120.3

120.2

00.1

00.0

120.5

120.4

00.2

00.3

00.5

00.4

80.1

80.3

80.2

40.1

40.3

40.2

80.4

80.5

40.4

40.6

40.5

120.0

120.1

120.3

120.2

00.1

00.0

120.5

120.4

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

Bit Mux

2:1

00.200.3

00.500.4

80.080.1

80.380.2

40.0

40.240.1

80.480.5

40.3

40.540.4

120.0120.1

120.3120.2

00.100.0

120.5120.4

Egress PCS/PMA

FEC0 FEC1 FEC2 FEC3

4X25Gbps FEC

symbol lanes

from 4 Sub-FECs

TX:CDAUI-16

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

Ingress PCS/PMA

FEC0 FEC1 FEC2 FEC3

AM lock

Alignment and Reorder

00.300.2

00.000.1

80.580.4

80.280.3

40.5

40.340.4

80.180.0

40.2

40.040.1

120.5120.4

120.2120.3

00.400.5

120.0120.1

RX:CDAUI-16

4X25Gbps FEC symbol

lanes to 4 Sub-FECs

40.780.6

80.6

Two 50Gbps Optical Link

Bit Demux

1:2

00.200.3

00.500.4

02.002.1

02.302.2

01.0

01.201.1

02.402.5

01.3

01.501.4

03.003.1

03.303.2

00.100.0

03.503.4

00.2

00.3

00.5

00.4

02.1

02.3

02.201.3

01.2

02.4

02.5

01.4

01.6

01.5

03.0

03.1

03.3

03.2

00.1

00.0

03.5

03.4

00.2

00.3

00.5

00.4

02.1

02.3

02.2

01.1

01.3

01.2

02.4

02.5

01.4

01.6

01.5

03.0

03.1

03.3

03.2

00.1

00.0

03.5

03.4

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

Bit Mux

2:1

00.200.3

00.500.4

02.002.1

02.302.2

01.0

01.201.1

02.402.5

01.3

01.501.4

03.003.1

03.303.2

00.100.0

03.503.4

Egress PCS/PMA

FEC0 FEC1 FEC2 FEC3

4X25Gbps FEC

symbol lanes from

ONE Sub-FEC

TX:CDAUI-16

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

Ingress PCS/PMA

FEC0 FEC1 FEC2 FEC3

AM lock

Alignment and Reorder

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

RX:CDAUI-16

4X25Gbps FEC symbol

lanes to ONE Sub-FEC

01.702.6

02.6

Two 50Gbps Optical Link

Bit Demux

1:2

00.200.3

00.500.4

02.002.1

02.302.2

01.0

01.201.1

02.402.5

01.3

01.501.4

03.003.1

03.303.2

00.100.0

03.503.4

00.2

00.3

00.5

00.4

02.1

02.3

02.201.3

01.2

02.4

02.5

01.4

01.6

01.5

03.0

03.1

03.3

03.2

00.1

00.0

03.5

03.4

00.2

00.3

00.5

00.4

02.1

02.3

02.2

01.1

01.3

01.2

02.4

02.5

01.4

01.6

01.5

03.0

03.1

03.3

03.2

00.1

00.0

03.5

03.4

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

Bit Mux

2:1

00.200.3

00.500.4

02.002.1

02.302.2

01.0

01.201.1

02.402.5

01.3

01.501.4

03.003.1

03.303.2

00.100.0

03.503.4

Egress PCS/PMA

FEC0 FEC1 FEC2 FEC3

4X25Gbps FEC

symbol lanes from

ONE Sub-FEC

TX:CDAUI-16

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

Ingress PCS/PMA

FEC0 FEC1 FEC2 FEC3

AM lock

Alignment and Reorder

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

RX:CDAUI-16

4X25Gbps FEC symbol

lanes to ONE Sub-FEC

01.702.6

02.6

Two 50Gbps Optical Link

Bit Demux

1:2

00.200.3

00.500.4

02.002.1

02.302.2

01.0

01.201.1

02.402.5

01.3

01.501.4

03.003.1

03.303.2

00.100.0

03.503.4

00.2

00.3

00.5

00.4

02.1

02.3

02.201.3

01.2

02.4

02.5

01.4

01.6

01.5

03.0

03.1

03.3

03.2

00.1

00.0

03.5

03.4

00.2

00.3

00.5

00.4

02.1

02.3

02.2

01.1

01.3

01.2

02.4

02.5

01.4

01.6

01.5

03.0

03.1

03.3

03.2

00.1

00.0

03.5

03.4

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

Bit Mux

2:1

00.200.3

00.500.4

02.002.1

02.302.2

01.0

01.201.1

02.402.5

01.3

01.501.4

03.003.1

03.303.2

00.100.0

03.503.4

Egress PCS/PMA

FEC0 FEC1 FEC2 FEC3

4X25Gbps FEC

symbol lanes from

ONE Sub-FEC

TX:CDAUI-16

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

Ingress PCS/PMA

FEC0 FEC1 FEC2 FEC3

AM lock

Alignment and Reorder

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

RX:CDAUI-16

4X25Gbps FEC symbol

lanes to ONE Sub-FEC

01.702.6

02.6

Two 50Gbps Optical Link

Bit Demux

1:2

00.200.3

00.500.4

02.002.1

02.302.2

01.0

01.201.1

02.402.5

01.3

01.501.4

03.003.1

03.303.2

00.100.0

03.503.4

00.2

00.3

00.5

00.4

02.1

02.3

02.201.3

01.2

02.4

02.5

01.4

01.6

01.5

03.0

03.1

03.3

03.2

00.1

00.0

03.5

03.4

00.2

00.3

00.5

00.4

02.1

02.3

02.2

01.1

01.3

01.2

02.4

02.5

01.4

01.6

01.5

03.0

03.1

03.3

03.2

00.1

00.0

03.5

03.4

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

Bit Mux

2:1

00.200.3

00.500.4

02.002.1

02.302.2

01.0

01.201.1

02.402.5

01.3

01.501.4

03.003.1

03.303.2

00.100.0

03.503.4

Egress PCS/PMA

FEC0 FEC1 FEC2 FEC3

4X25Gbps FEC

symbol lanes from

ONE Sub-FEC

TX:CDAUI-16

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

Ingress PCS/PMA

FEC0 FEC1 FEC2 FEC3

AM lock

Alignment and Reorder

00.300.2

00.000.1

02.502.4

02.202.3

01.5

01.301.4

02.102.0

01.2

01.001.1

03.503.4

03.203.3

00.400.5

03.003.1

RX:CDAUI-16

4X25Gbps FEC symbol

lanes to ONE Sub-FEC

01.702.6

02.6

1X400GbE :

16X25G CDAUI

with 8X50G PMD

4X100GbE :

4X(4X25G) CDAUI

with 2X50G PMD

Reuse compatible gearbox for

400GbE and 4x100GbE

Four groups of FOM mux

in 400GbE.

Every 100GbE has mux

within itself.

MTTFPA Performance may be

different for 400GbE and

100GbE, by using compatible

gearbox.

How much difference?

Whether it is acceptable

for MTTFPA requirement

for both 400GbE/100GbE?

Compatible Gearbox - 1x400GbE vs. 4x100GbE

Page 8

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

Performance Difference - 1x400GbE vs. 4x100GbE

While 400GbE has four parallel 100GBase-KR4/KP4 RSFEC and FOM mux

options, if every individual 100GbE reuse one RSFEC encoder/decoder with

only non-FOM mux options, what is the performance for 100GbE?

Mux options:

Bit mux

To reach BERpost = 1e-13 in 400GbE, SNR = 12.2dB,

On each 100GbE,

BERpost = 1e-10 (b=0.5, rll=4);

= 5e-11 (b=0.1, rll=4)

*MTTFPA = 108 ~ 1010 years.

Symbol mux

To reach BERpost = 1e-13 in 400GbE, SNR=11.8dB,

On each 100GbE,

BERpost = 1e-12 (b=0.5, rll=4);

= 1e-13 (b=0.1, rll=4)

*MTTFPA = 1011 ~ 1013 years.

Page 9

*refer to http://www.ieee802.org/3/bj/public/jan12/cideciyan_01_0112.pdf

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

Conclusions

By using 100GBASE-KR4 RS(528,514) and FOM bit mux 2:1, BERin should be

1.9e-5 to satisfy BERpost = 1e-13 objective in 400GbE, with coding gain of

5dB;

By using 100GBASE-KP4 RS(544,514) and FOM bit mux 2:1, It requires 2.8e-4

to meet BERpost = 1e-13 objective in 400GbE, with coding gain of 6.5dB;

Supporting 400GbE and 4x100GbE compatible gearbox is possible with

bitmux option, either accepting a certain degradation of performance

according to the PMD features or we can put constraints on error

propagation factors to keep MTTFPA.

Page 10

Thank you

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

BER Evaluation (2:1 mux ,rllmax=2 bits)

Page 12

RS528,514 b=0.1

BERpost FLR mux 2:1

FOM Symmux

FOM bitmux

Non-FOM sym

Non-FOM bit

1.00E-12 6.20E-10 5.19E-05 5.19E-05 4.92E-05 2.71E-05

1.00E-13 6.20E-11 3.75E-05 3.75E-05 3.56E-05 1.67E-05

1.00E-15 6.20E-13 2.07E-05 2.07E-05 1.86E-05 6.31E-06

RS528,514 b=0.5

BERpost FLR mux 2:1

FOM Symmux

FOM bitmux

Non-FOM sym

Non-FOM bit

1.00E-12 6.20E-10 5.19E-05 5.19E-05 4.92E-05 1.34E-05

1.00E-13 6.20E-11 3.75E-05 3.75E-05 3.37E-05 7.84E-06

1.00E-15 6.20E-13 2.07E-05 2.07E-05 1.58E-05 2.52E-06

RS544,514 b=0.1

BERpost FLR mux 2:1

FOM Symmux

FOM bitmux

Non-FOM sym

Non-FOM bit

1.00E-12 6.20E-10 3.63E-04 3.63E-04 3.63E-04 2.93E-04

1.00E-13 6.20E-11 3.09E-04 3.09E-04 3.09E-04 2.36E-04

1.00E-15 6.20E-13 2.23E-04 2.23E-04 2.23E-04 1.53E-04

RS544,514 b=0.5

BERpost FLR mux 2:1

FOM Symmux

FOM bitmux

Non-FOM sym

Non-FOM bit

1.00E-12 6.20E-10 3.63E-04 3.63E-04 3.63E-04 2.23E-04

1.00E-13 6.20E-11 3.09E-04 3.09E-04 3.09E-04 1.61E-04

1.00E-15 6.20E-13 2.23E-04 2.23E-04 2.23E-04 9.41E-05

HUAWEI TECHNOLOGIES CO., LTD.

35pt

32pt

) :18pt

BER Evaluation (2:1 mux ,rllmax=8 bits)

Page 13

RS528,514 b=0.1

BERpost FLR No mux mux 2:1

Random Err

Burst Err FOM Symmux

FOM bitmux

Non-FOM sym

Non-FOM bit

1E-12 6.2E-10 5.19E-05 4.92E-05 5.19E-05 5.19E-05 4.92E-05 2.31E-05

1E-13 6.2E-11 3.75E-05 3.56E-05 3.75E-05 3.75E-05 3.56E-05 1.42E-05

1E-15 6.2E-13 2.07E-05 1.76E-05 2.07E-05 2.07E-05 1.76E-05 4.33E-06

RS528,514 b=0.5

BERpost FLR No mux mux 2:1

Random Err

Burst Err FOM Symmux

FOM bitmux

Non-FOM sym

Non-FOM bit

1.00E-12 6.20E-10 5.19E-05 2.57E-05 5.19E-05 3.19E-05 2.57E-05 3.13E-06

1.00E-13 6.20E-11 3.75E-05 1.58E-05 3.75E-05 1.96E-05 1.58E-05 1.39E-06

1.00E-15 6.20E-13 2.07E-05 5.98E-06 2.07E-05 6.67E-06 5.98E-06 1.99E-07

RS544,514 b=0.1

BERpost FLR No mux mux 2:1

Random Err

Burst Err FOM Symmux

FOM bitmux

Non-FOM sym

Non-FOM bit

1.00E-12 6.20E-10 3.63E-04 3.44E-04 3.63E-04 3.63E-04 3.44E-04 2.77E-04

1.00E-13 6.20E-11 3.09E-04 3.08E-04 3.09E-04 3.09E-04 3.08E-04 2.23E-04

1.00E-15 6.20E-13 2.23E-04 2.23E-04 2.23E-04 2.23E-04 2.23E-04 1.37E-04

RS544,514 b=0.5

BERpost FLR No mux mux 2:1

Random Err

Burst Err FOM Symmux

FOM bitmux

Non-FOM sym

Non-FOM bit

1.00E-12 6.20E-10 3.63E-04 2.77E-04 3.63E-04 3.44E-04 2.77E-04 9.41E-05

1.00E-13 6.20E-11 3.09E-04 2.23E-04 3.09E-04 2.77E-04 2.23E-04 6.45E-05

1.00E-15 6.20E-13 2.23E-04 1.50E-04 2.23E-04 1.80E-04 1.45E-04 3.19E-05