Behavioral Descriptions

Instructors: Fu-Chiung Cheng

(鄭福炯 )Associate Professor

Computer Science & EngineeringTatung University

Outline

• Process Statements• Assertion statements• Sequential statement

Behavioral Description Basics

Most hardware characteristics can be described by the methods and techniques presented in the previous chapters (I.e. Structural and Dataflow descriptions)

Hardware implementation can be also describe at behavioral level

VHDL– Process statements

Process Statement

A simple signal assignment in the statement part of an architecture is a process

A process is always active and executing concurrently with other processes within the same architecture.

A process is a concurrent statement, enclosing sequential statements

A process contains (see Fig 9.1 on page 332)– Declaration part– Statement part

Process Statement: declarative part

Declarative part contains only variables, file and constants (no signals)

Signal declared in the the declarative part of an architecture can be used inside a process

– only means of communication between two processes

Initialization of objects declared in a process is done only once at the beginning of a simulation time

These objects are alive for the entire simulation time Note that initialization of a subprogram are preformed

each time the subprogram is called

Process Statement: statement part

The statement part of a process is – sequential (use only sequential constructs)– always active

Sequential statemetns– Selection and assignment statements– If, loop or case statements

Execution: (see Fig 9.2 on page 333)– executes in zero real and delta time– repeats itself forever– Unless a sequential body is suspended

Process Statement: statement part

ARCHITECTURE sequentiality_demo OF partial_process ISBEGINPROCESSBEGIN

...x <= a;y <= b;...

END PROCESS;END sequentiality_demo;

• First: a is scheduled for x• Next: b is scheduled for y• x and y receive values at the

same time• Both assignments occur a

delta later• Zero time between both

scheduling

Process Statement: statement part

ARCHITECTURE execution_time_demo OF partial_process ISBEGINPROCESSBEGIN

...x <= a AFTER 10 NS;y <= b AFTER 6 NS;...

END PROCESS;END execution_time_demo;

• First: a is scheduled for x• Next: b is scheduled for y• y receives b sooner than x receiving a

Process Statement: statement part

PROCESSBEGIN

...x <= '1';IF x = '1' THEN

Perform_action_1ELSE

Perform_action_2END IF;...

END PROCESS;

• Note that x is a signal• Assume x is initially '0'• Assignment of '1' to x

takes a delta time• Which Action will be taken?

Ans: Action_2

Process Statement: statement part

PROCESSvariable x:BIT:=0;

BEGIN...x := '1';IF x = '1' THEN

Perform_action_1ELSE

Perform_action_2END IF;...

END PROCESS;

• Note that x is a variable• Assume x is initially '0'• Assignment of '1' to x • Which Action will be taken?

Ans: Action_1

Sensitivity List

A process is always active and executes at all time if not suspended

Sensitivity list : a mechanism for suspending and subsequently conditional activating a process

Sensitivity List

Syntax:

Process (sensitivity_list)

-- declarative part

Begin

-- statement part

end

Sensitivity List(example)

ARCHITECTURE … ARCHITECTURE …BEGIN BEGIN

… …a <= b; PROCESS (b)… …c <= d; a <= b;… END PROCESS;

END …; … c <= d; …END …;

Process Statement:

Process is a concurrent statement Signal assignment is a concurrent statement Process sensitivity plays the role of RHS

activation Any signal assignment can be expressed by a

process statement

Positive-edge-trigger D Flip-flop

See Fig 9.7 on page 336 Asynchronous set signal

– Set dff to one

Asynchronous reset signal– Clear dff to zero

Clock = 1 and clock’event– Dff = d;

ENTITY d_sr_flipflop ISGENERIC (sq_delay, rq_delay, cq_delay : TIME := 6 NS);PORT (d, set, rst, clk : IN BIT; q, qb : OUT BIT);

END d_sr_flipflop;ARCHITECTURE behavioral OF d_sr_flipflop IS

SIGNAL state : BIT := '0';BEGIN

dff: PROCESS (rst, set, clk) -- dff is sensitive to (rst, set, clk)BEGIN

IF set = '1' THENstate <= '1' AFTER sq_delay;

ELSIF rst = '1' THENstate <= '0' AFTER rq_delay;

ELSIF clk = '1' AND clk'EVENT THENstate <= d AFTER cq_delay;

END IF;END PROCESS dff;q <= state;qb <= NOT state;

END behavioral;

ARCHITECTURE average_delay_behavioral OF d_sr_flipflop IS

BEGIN

dff: PROCESS (rst, set, clk)

VARIABLE state : BIT := '0'; -- use variable

BEGIN -- eliminates the delta delay

IF set = '1' THEN

state := '1';

ELSIF rst = '1' THEN

state := '0';

ELSIF clk = '1' AND clk'EVENT THEN

state := d;

END IF;

q <= state AFTER (sq_delay + rq_delay + cq_delay) /3;

qb <= NOT state AFTER (sq_delay + rq_delay + cq_delay) /3;

END PROCESS dff;

END average_delay_behavioral;

Positive-edge-trigger D Flip-flop using state-delay record

More readableTYPE bit_time IS RECORD

state : BIT; delay : TIME;

END RECORD;

Assignment to variables are done in zero time without the delta delay

ARCHITECTURE behavioral OF d_sr_flipflop ISBEGIN

dff: PROCESS (rst, set, clk)TYPE bit_time IS RECORDstate : BIT; delay : TIME;END RECORD;VARIABLE sd : bit_time := ('0', 0 NS);

BEGINIF set = '1' THEN

sd := ('1', sq_delay);ELSIF rst = '1' THEN

sd := ('0', rq_delay);ELSIF clk = '1' AND clk'EVENT THEN

sd := (d, cq_delay);END IF;q <= sd.state AFTER sd.delay;qb <= NOT sd.state AFTER sd.delay;

END PROCESS dff;END behavioral;

Postponed process

Non-postponed processes are activated at each delta time if the signals in the sensitivity list is changed.

Postponed processes activate a process statement only one per real-time

Syntax:– Concurrent1 : POSTPONED a<=b and C or d;

See Fig 9.13 on page 342

Behavioral flow control constructs

Flow control constructs: if, loop, exit, nextlong_runing : LOOP

. . .IF x = 25 THEN EXIT; -- exit when x = 25;END IF;. . .

END LOOP long_runing;

NEXT loop_label WHEN condition; EXIT WHEN condition;