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ACPL-P346/W346Isolated Power MOSFET Gate Driver Evaluation Board

User's Manual

Quick StartVisual inspection is needed to ensure that the evaluation board is received in good condition.

All part reerences are designated with sux a and b to indicate the lower and the upper inverter arms, respectively. I

part reerences are made without suxes, then they are valid or both upper and lower inverter arms (except R6, which

is shared).

Figure 1 shows the deault connections o the evaluation board:

1. Q1 and Q2 are not mounted. Actual Power MOSFET can be mounted at either Q1 (or TO-220 package) or Q2 (or TO-

247 package) or connected to the driver board through short wire connections rom the holes provided at Q1 or Q2.

2. D4 and R7 are not mounted (on solder side). A 12 V Zener diode ootprint at D4 is provided to allow or a single DC

power supply o 15 V ~25 V to be applied across VCC2 and VEE i needed. A virtual ground VE (at Source pin o Q1 or

Q2) can then be generated and it acts as the reerence point at the source pin o each power MOSFET. VCC2 will then

stay at 12 V above the virtual ground VE. R7 is needed to generate the bias current across D4.

3. S2 and S3 jumpers are shorted by deault to connect VE to VEE, assuming that a negative supply is not needed. Note:

I a negative supply is needed, then S2 and S3 jumpers must be removed.

4. Bootstrap diode D3b and resistor R6 are connected by deault. These two components are provided to help generate

VCC2b supply through bootstrapping assuming that VCC2a supply is available. Note: Bootstrapping supply works

only when Q1 or Q2 are mounted in a hal-bridge conguration and turned on and o through proper PWM driving

signals.

5. S1 is shorted by deault to ground the IN- (or LED-, the cathode o LED) pin when VCC1 is supplied. This short can be

removed i IN- cannot be grounded.

6. Upper and lower arms o the inverter will have common VCC1 (and GND1), a provision is made to allow VCC1 to be

connected by solder between upper and lower inverter PCB portions (and GND1 on the solder side).

7. Provisions are also made to allow VCC2 (and VEE) to be generated rom VCC1 through a DC/DC converter at IC2. Whenthis DC/DC converter is used, S2, S3 (and R6) should be disconnected.

Figure 1. Actual ACPL-P346/W346 evaluation board showing deault connections

VCC1aandVCC1b(shorted)

GNDaandGNDbon

solderside(alsoshorted)

S1 (shorted) S2 (shorted) S3 on solder side (also shorted)

R6

mounted(shorted)

VCC1b

VCC1a

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Once inspection is done, the evaluation board can be powered up in ve simple steps. Figure 2 shows you how to test

the top or the bottom hal-bridge inverter arms in simulation mode without the need or an actual power MOSFET.

Testing both arms o the hal-bridge inverter driver (without a power MOSFET)

1. Solder a 10 nF capacitor across the gate and emitter terminals o Q1 or Q2. This is to simulate actual gate capacitance

o a power MOSFET.

2. Connect a +5 V DC supply (DC supply 1) across the +5V and GND terminals o CON1.

3. Connect another DC supply (DC Supply 2 with voltage range rom 12 V ~ 20 V) across VCC2 (pin 7 o IC2) and VEE (pin5 o IC2) terminals o IC2a, respectively. This can be non-isolated or testing purposes.

4. Connect drive signals:

a. A 10 kHz 5 V DC pulse (at slightly < 50% duty) rom a dual-output signal generator across IN1+ and IN1- pins o

CON1a to simulate microcontroller output to drive the lower arm o the hal-bridge Inverter.

b. Another 10 kHz 5V DC pulse (at 180 out o phase to the signal in 4a) rom the dual-output signal generator across

IN2+ and IN2- pins o CON1b to simulate microcontroller output to drive the upper arm o the hal-bridge inverter.

5. Use a multi-channel digital oscilloscope to capture the waveorms at the ollowing points:

a. LED signal at the IN1+ pin with reerence to (w.r.t.) GND.

b. LED signal at the IN2+ pin w.r.t. GND.

Note: The VCC2b supply o voltage close to VCC2a should then be successully generated through the built-in bootstrap

components D3b and R6.

c. VGa representing the output voltage o ACPL-P346/W346 (IC1a) at the gate pin o Q1a (or Q2a) w.r.t. VEa.

d. VGb (through an isolated probe) representing the output voltage o ACPL-P346/W346 (IC1b) at the gate pin o Q1b

(or Q2b) w.r.t. VEB.

10nF

In1+

In1-

SignalInput

+5V

Gnd

D

CSupply1

12~20 V

+-

10nF

VCC2b

+-

In2+

In2-

SignalInput

5a

5b

5c

5d

VEa

VEb

DC Supply 2

1

2

4a

3

1

4b

Figure 2. Simple Simulation Test Setup o Evaluation Board

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Schematics

Figure 3 shows the schematics o the evaluation board:

NM

1 ACPL-P346

NM

NM

NM

NM

VCC2b

VEEb

3 4

5

6

1

VCC2a

VEEa

3 4

5

6

249R

130R

249R

130R

4R7 1W

4R7 1W

LEDa+

LEDa-

VCC1a

GNDa

LEDb+

LEDb-

VCC1b

GNDb

0.1F

0.1F

SS32

SS32

BYM26F

10F Ta

R05P212D/R8

1

25

6

7

1

2 5

6

7

10F Ta

10F Ta

TP2b

TP3b

TP4b

TP1b

TP2a

TP3a

TP4a

TP1a

S1a

S2a

S1b

S2b

CON1a

CON1b

IC1a

IC1b

IC2a

IC2b

R1a

R2a

R3a

R4a

R5a

R6

C1a

C2a

C3a

D1a

D2a

R1b

R2b

R3b

R4b

R5b

C1b

C2b

C3b

D1bD2b

D3b

VEa

VEb

BYM26FD3a

10F Ta

D4b

R7b

NM

NM

D4a

R7a

NM

NM

NMTO220/TO247

G

D

S Q1b/Q2b

NMTO220/TO247

G

D

S Q1a/Q2a

S3b

S3a

ACPL-P346

VCC2b

VEEb

VCC2a

VEEa

4R71W

SMBJ11CA

SMBJ11CA

Figure 3. Schematics o ACPL-P346/W346 evaluation board

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Practical connections o the evaluation board using a power MOSFET or an actual inverter test

1. Solder actual power MOSFETs at Q1 (or Q2) or the top and bottom arms o the hal-bridge inverter isolated drivers.

2. Connect a +5V DC isolated supply1 across +5V and GND terminals o CON1 or both arms o the isolated drivers.

3. Connect another isolated DC supply2 (voltage range rom 12 V ~ 20 V) across VCC2a and VEEa at pin 7 and pin 5 o IC2a

respectively or the bottom arm.

4. Connect the signal output (meant to drive the bottom arm o the hal-bridge inverter) rom the microcontroller to

Signal Input 1 across pin IN1+ and IN1- o CON1a o the bottom inverter arm isolated driver.5. Connect the signal output (meant to drive the top arm o the hal-bridge inverter) rom the microcontroller to Signal

Input 2 across pin IN2+ and IN2- o CON1b o the top inverter arm isolated driver. Note: Signal Input 2 should be

180 out o phase w.r.t. Signal Input 1. Check that VCC2b (voltage close to VCC2a) is generated through the bootstrap

components D3b and R6.

6. Use a multi-channel digital oscilloscope to capture the waveorms at the ollowing points:

a. LED signal at IN1+ pin w.r.t. GND or the bottom arm.

b. LED signal at IN2+ pin w.r.t. GND or the top arm.

c. Vga or the gate driving voltage o Q1a (or Q2a) w.r.t. VEa o the bottom inverter arm (dierential probe needed).

d. Vgb or the gate driving voltage o Q1b (or Q2b) w.r.t. VEb o the top inverter arm (dierential probe needed).

7. Connect a power cable rom the output pin (marked Load) to the inverter load.

8. Connect the high voltage cables rom the top arm power MOSFET drain pin to HVDC+ and rom the bottom arm

power MOSFET source pin to HVDC-, respectively, as shown. (Note: It is recommended that you enable the current-

limiting unction o the HV power source supplying the high voltage DC bus voltage during this test to protect the

inverter and its driver circuitries).

Microcontroller

IN1+

IN1-Signal Input 1

+5V

GND

DCSupply1

IN2+

IN2-Signal Input 2

Power MOSFETmounted

1

1

2

3

12~20 V

+

DC Supply2

4

5

12~20V

+5

6a

6b

6c

6d

Load

7

HVDC+

HVDC

8

8

Power MOSFETmounted

Figure 4. Connection o evaluation board in actual applications

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Application Circuit Description

The ACPL-P346/ACPL-W346 is an isolated gate driver that provides 2.5 A output current. The voltage and high peak

output current supplied by this optocoupler make it ideally suited or direct driving o MOSFET with ratings up to 1000

V/100 W. It is also designed to drive dierent sizes o buer stage that will make the class o power MOSFET scalable.

ACPL-P346 (and ACPL-W346) provides a single isolation solution suitable or both low and high power ratings o motor

control and inverter applications.

Each o the ACPL-P346/ACPL-W346 evaluation boards, as shown in Figure 5, accommodates two ACPL-P346/ACPL-W346ICs. Thereore, each board is enough to drive the top and the bottom arms o the hal-bridge inverter. It allows the de-

signer to easily test the perormance o a gate driver in an actual application under real-lie operating conditions. Opera-

tion o the evaluation board requires merely the inclusion o a common 5 V DC isolated Supply1 on the input side and

an isolated DC Supply2 (range rom 12 V ~ 20 V) or the bottom arm o the inverter power MOSFET, while the DC supply

needed or the top arm is easily generated through bootstrapping included in the evaluation board.

Note: As can be seen on the board, the isolation circuitry (at the ar let) is easily contained within a small area while

maintaining adequate spacing or good voltage isolation and easy assembly.

Figure 5. Top and bottom views o ACPL-P346/W346 evaluation board

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Using the Board

It is easy to prepare the evaluation board or use. You just need to solder cables or DC supplies, have proper cables or

HVDC+/HVDC- high voltage bus, and load connections. The evaluation board has a deault connection as shown in

Table 1 when it is shipped to the customer. We oer several power supply schemes rom which you can choose.

Power Supply Schemes

The evaluation board is built with DC supply fexibility in mind; choose a power supply scheme rom the seven available.Table 1 shows all the possible power supply schemes that work or the evaluation board. A description o each scheme

is given; you are encouraged to explore each scheme and decide which one works best or your needs:

1. Scheme 1 is the simplest and possibly the cheapest scheme. A +5 V isolated DC supply is supplied externally to

power the low voltage Vcc1 circuit. Another external supply (+12 V~20 V or Vcc2a) is needed or the gate driver driving

the power MOSFET at the bottom inverter arm. Vcc2b supply is obtained rom Vcc2a by bootstrapping. For this to

work, the bootstrap components D3b and R6 must be connected, all S2 jumpers must be shorted so that no negative

supply o Vee is allowed, and the Signal Input 2 is at 180 out o phase to Signal Input 1. All S2 jumpers are shorted to

connect Vee to Ve so that there are no negative supplies. S3 jumpers are shorted by deault but this has no eect on

actual operation o the board. Contact Avago Technologies i bootstrapping operation works are required.

2. Scheme 2 is similar to Scheme 1: it has Vcc1 and Vcc2a supplies. However, as the power MOSFET used gets bigger,

so does the driving power. Because a bootstrapped power supply can only handle a lower driving power, it is not

suitable or use when Qg o power MOSFET rises above 200 nanocoulombs (nC). A third external supply (+12 V~ 20V or Vcc2b) will be needed.

3. Scheme 3 is similar to Scheme 2 in that it uses three external supplies at Vcc1, Vcc2a and Vcc2b. Scheme 3, however, has

the advantage o getting negative supplies or Vee (or Veea and Veeb) by introducing a 12 V Zener diode at D4 and R7

o around 1 k to provide proper biasing current at D4. For this scheme to work, both the S2 and S3 jumpers must be

open while the external supplies (+15 V ~ 24 V) on the high voltage driver side are to be connected across Vcc2 and Vee

pins only, not the Ve pin. As the external supply changes rom +15 V to +24 V, Vcc2 will stay at +12V, but Vee changes

rom -3 V to -12 V, all w.r.t. virtual ground at Ve.

4. Scheme 4 is another simple scheme; an alternative to Scheme 1. Here, only one external supply or Vcc1 is needed.

Vcc2a is obtained by a lower power DC/DC converter at IC2a, with Vcc1 as Vin and +12 V output at Vcc2a w.r.t. Vea. Vcc2b

supply is obtained rom Vcc2a by bootstrapping. For this to work, the bootstrap components D3b and R6 must be

connected, all S2 jumpers must be shorted so that no negative supply o Vee is allowed, and the Signal Input 2 should

be 180

out o phase to Signal input 1. S2 is shorted to connect Vee to Ve so that there is no negative supply. S3jumpers are shorted by deault but this has no eect on actual operation o the board.

5. Scheme 5 is similar to Scheme 4: it has Vcc1 and a DC/DC converter or Vcc2a. However, as the power MOSFET used

gets bigger, so does the driving power. Because a bootstrapped power supply can only handle a lower driving power,

it is not suitable or use when Qg o power MOSFET rises above 200 nanocoulombs (nC). A second DC/DC converter at

IC2b with Vcc1 as Vin and +12 V output at Vcc2b w.r.t .Veb. All S2 jumpers are shorted to connect Vee to Ve so that there

are no negative supplies. S3 jumpers are shorted by deault but this has no eect on actual operation o the board.

6. Scheme 6 is similar to Scheme 5 with the use o Vcc1 and two DC/DC converters. Each DC/DC converter, however, has

dual outputs set at 12 V to allow or the availability o negative Vee (at Veea and Veeb). Thereore, all S2 jumpers must

be open, while all S3 jumpers must be shorted.

7. Use Scheme 7 i dual-output 12 V DC/DC converters are not available or dual-output 9 V DC/DC converters are

preerred. 12 V Vcc2 can still be obtained using 9 V DC/DC converters by introducing a 12V Zener diode at D4 and R7

o around 1k to provide proper biasing current at D4. For this scheme to work, both the S2 and S3 jumpers must beopen. As the total voltage across Vcc2 w.r.t. Vee stays at 18V (=9V+9V), Vcc2 o 12 V will be obtained through the 12 V

D4 Zener diode, and -6V at Vee, all w.r.t. virtual ground at Ve.

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Table 1. Power Supply Schemes

Vcc1 Vcc2a Veea S2a S3a

D4a/

R7a Vcc2b Veeb S2b S3b

D4b/

R7b Remarks

1 +5 V

External

+12V~20V

External

0 V s/c s/c NM Bootstrapped

rom Vcc2a

(+12V~20V)

0 V s/c s/c NM Deault (simplest)

- Two external supplies needed

or Vcc1 and Vcc2a

2 +5 V

External

+12V~20V

External

0 V s/c s/c NM +12V~20V

External

0 V s/c s/c NM Higher Power

- Three external supplies neededor Vcc1, Vcc2a and Vcc2b

3 +5 V

External+15V~24V External open open 12V/

1k+15V~24V External open open 12V/1k Vee available

- Three external supplies needed

or Vcc1, Vcc2a and Vcc2b- Virtual gnds Vea and Veb

generated through D4 and R7

12V -3V~-12V 12V -3V~-12V

4 +5 V

ExternalDC/DC

(=Vcc1/+12V)

0 V s/c s/c NM Bootstrapped

rom Vcc2a

(+12V)

0 V s/c s/c NM Cheap

- One single output DC/DC

converter or Vcc2a

- Only one external supply is

needed (Vcc1)

5 +5 V

ExternalDC/DC

(=Vcc1/+12V)

0V s/c s/c NM DC/DC

(=Vcc1/+12V)

0 V s/c s/c NM Higher Power

- Two single output DC/DC

converters or Vcc2a and Vcc2b- Only one external supply is

needed (Vcc1)

6 +5 V

ExternalDC/DC (=Vcc1/12V) open s/c NM DC/DC (=Vcc1/12V) open s/c NM Vee available

- Two dual output DC/DC

converters or Vcc2a,Vcc2b, Veea

and Veeb

- Only one external supply is

needed (Vcc1)

+12V -12V +12V -12V

7 +5 V

ExternalDC/DC (=Vcc1/9V) open open 12V/

1kDC/DC (=Vcc1/9V) open open 12V/1k Vee available

- Dual output DC/DC converters

or Vcc2a and Vcc2b- only 1 external supply is

needed (Vcc1)

- Virtual gnds Vea and Veb

generated through D4 and R7

+12V -6V +12V -6V

Note: As TVS D2 voltage is selected at a breakdown voltage o 12.2 V, it is not advised to set both Vcc2 and Vee voltage at a voltage beyond 12 V.

To use a voltage higher than 12 V, please replace D2 with a bigger clamping voltage.

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Figure 7. Turn-of and Turn-on Gate waveorms o Q1a and Q1b

Figure 6. Input LED signal and Power MOSFET Gate Voltage Waveorms

Figure 6 also shows that, once a bootstrap supply is adopted, the amplitude o the output voltage at the top inverter arm

will be slightly smaller than that o the bottom inverter arm, at 180 out o phase. (IN1+ is set at 49% duty ratio, while

IN2+ (not shown) is also set with 49% duty ratio, plus a turn-on delay o 100 ns with respect to IN1+).

Figure 7 shows the turn-o signal o IN1+, the turn-o signal at gate o Q1a, and the turn-on signal at gate o Q1b.

Output Measurement

A sample o input LED and various output waveorms are captured and shown in Figure 6. The deault setup connection

is adopted, except with Q1a and Q1b power MOSFETs are mounted. The power MOSFETs used have a gate capacitance

equivalent to 10 nF.

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For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.

Data subject to change. Copyright 2005-2013 Avago Technologies. All rights reserved.

AV02-4051EN - May 2, 2013

As can be seen rom Figure 7 and Figure 8, the turn-o speed o the power MOSFET will be slow, due to the capacitive

eects o D2 and the gate capacitance o Q1. To improve the turn-o speed, the board is provided with a diode resis-

tor pair ootprints at D1 and R5 (not mounted NM) to increase the gate current during turn-o. Another way to urther

improve the turn-on and turn-o speed is by reducing the gate resistance o R4, but make sure the gate drive current is

not more than 2.5 A.

Figure 8 shows the turn-on signal o IN1+, the turn-on signal at gate o Q1a and the turn-o signal at gate o Q1b.

Figure 8. Turn-on and Turn-of Gate waveorms o Q1a and Q1b