asic va vlsi
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Transcript of asic va vlsi
THIT K VI MCH VLSI ASICp dng cho ngnh K thut My tnh Ti liu tham kho: - ASIC lp trnh c, Tng Vn On, NXB Thng K, 2004 - Thit k h thng VLSI, inh S Hin, NXB HQG TPHCM
- The VLSI Handbook, Wai Kai Chen
Bin son: BM: Web:Thi nguyn 08/2008
Nguyn Vn Huy KTMT H KTCN Thi Nguyn http://ktmtcn.tkSlide 1
Thit k vi mch VLSI - ASIC - FPGA
Chng 1 TNG QUAN1.1. Tm hiu v VLSI 1.2. L do VLSI c chn v pht trin 1.3. ASIC l g? 1.4. FPGA l g? 1.5. Nguyn l lp trnh cho vi mch 1.6. So snh vi lp trnh phn mm
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Thit k vi mch VLSI - ASIC - FPGA
Slide 2
1.1. Tm hiu v VLSISSI (Small Scale Integration Mch tch hp c nh) 1970
Trn mch ch c th cha c t 1 n 10 cng logic (NAND, NOR, .v.v.) Ch yu p dng cho cc bi ton nh nh thit k cc my tnh in t cm tay.
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Thit k vi mch VLSI - ASIC - FPGA
Slide 3
1.1. Tm hiu v VLSI
VD My tnh cm tay Hnh 1.1 Kch thc chip ln nhng chc nng nh
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Slide 4
1.1. Tm hiu v VLSIMSI (Medium Scale Integration Mch tch hp c trung bnh).
Ngoi vic tch hp cc cng logic, cc mch cn c m rng tch hp thm cc b m v cc chc nng logic tng ng .
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Slide 5
1.1. Tm hiu v VLSILSI (Large Scale Integration Mch tch hp c ln)
c tch hp vi nhiu chc nng logic hn, thm ch c c b vi x l hon chnh trong mt chip.
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Slide 6
1.1. Tm hiu v VLSI
V d chip iu khin mn hnh LCD Hnh 1.2 Kch thc IC gim nhng chc nng ln
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Slide 7
1.1. Tm hiu v VLSIVLSI(verry large scale integation)
Mi th u c trong mt chp. c cc b x l 64 bt, cc b s hc du phy ng. Trn mt triu transistor ch trn mt ming Silic
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Slide 8
1.1. Tm hiu v VLSI
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1.1. Tm hiu v VLSI
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1.2. L do VLSI c chn v pht trinTrc y, khi mun thit k mt h thng mch, chng ta phi thit k t nhng IC chun thit k sn s dng cng ngh TTL (Transistor Transistor Logic).
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Slide 11
Hnh 1.3 Mt v d v 1 mch c thit k trn cc IC chun TTLThi nguyn 08/2008 Thit k vi mch VLSI - ASIC - FPGA
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1.2. L do VLSI c chn v pht trinKhi cng ngh CMOS ra i, hng triu transistor c th cha trong mt ming silic nh Cc k s bt u nhn ra li ch ca vic thit k mt IC p ng yu cu c th cho mt h thng thay v phi thit k chng t cc IC chun ring bit.
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Slide 13
1.2. L do VLSI c chn v pht trinCc k s s phn tch v thit ra mt IC duy nht gii bi ton , khng cn s chp ni ca nhiu IC khc nhau, gim kh nng li, gim thi gian ch gia cc IC, gi thnh h.
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Slide 14
1.3. ASIC l g?ASIC vit tt ca: Application-Specific Integrated Circuit L mt IC c thit cho mt mc ch hoc mt h thng c th (Full custom IC ) Thc cht l mt di cc transistor MOS cha c kt ni. Vic kt ni to thnh mch c th phc thuc vo ngi s dngThi nguyn 08/2008 Thit k vi mch VLSI - ASIC - FPGA
Slide 15
1.4. FPGA l g?FPGA l tp hp cc cell logic lp trnh c ni vi nhau bng ma trn chuyn mch lp trnh c. tr thnh mt mch c th, ma trn chuyn mch s c lp trnh nh tuyn cc tn hiu gia cc khi logic
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Slide 16
1.4. FPGA l g?Cu trc ca FPGA
Cc khi logic c bn lp trnh c (logic block) H thng mch lin kt lp trnh c Khi vo/ra (IO Pads) Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...
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Slide 17
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1.4. FPGA l g?So snh FPGA vi ASIC
Xt cng mt ng dng th thit k trn ASIC t c mc ti u hn thit k trn FPGA FPGA hn ch trong cc tc v c bit FPGA c kh nng ti lp trnh n gin, thit k ng dng d dng nn chi ph v thi gian sn xut gim.
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Slide 21
1.4. FPGA l g?Cc chip FPGA v ASIC cng vi cc gi phn mm thit k mch thng c cc cng ty thit k sn cho ngi s dng nh Xilinx, Altera. Cc gi phn mm ny tch hp y quy trnh t bt u n ra sn phm, mi thao tc hon ton trong sut vi ngi s dngThi nguyn 08/2008 Thit k vi mch VLSI - ASIC - FPGA
Slide 22
tng
Thit k
M phng Chy th
Lp trnh ln mch
Phn mm thit k ASIC/FPGA
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Slide 23
1.4. FPGA l g?ng dng:
X l tn hiu s, hng khng, v tr, quc phng, tin thit k mu ASIC (ASIC prototyping), nhn dng nh, nhn dng ting ni, mt m hc, m hnh phn cng my tnh...
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Slide 24
1.4. FPGA l g?ng dng:
Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt lp nhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh Ngoi ra nh mt cng logic ln FPGA c ng dng cho nhng bi ton i hi khi lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc.Thit k vi mch VLSI - ASIC - FPGA
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1.5. NL lp trnh cho vi mchTo cc kt ni hp l gia cc Cell logic hoc gia cc transistor tch hp sn to thnh mch c chc nng theo yu cu.
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1.5. NL lp trnh cho vi mchC hai cng ngh to lin kt:
1 l tt cc cell hoc transistor c lin kt y vi nhau, khi c lp trnh h thng s ph b cc mi lin kt ch gi li cc lin kt thuc v mch. 2 l tt c cc cell hoc transistor cha c lin kt, h thng lp trnh s to lin kt gia cc cell to thnh mch.
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1.6. So snh lp trnh vi mch v lp trnh phn mmTho lun so snh.
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Chng 2: Cng ngh CMOSComplementary Metal Oxide Silicon (oxit kim loi b) L mt loi vi mch tch hp cao nhng li tiu tn t nng lng.
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Chng 2: Cng ngh CMOS"complementary" ("b"), v cc vi mch CMOS s dng c hai loi tranzito PMOS v NMOS v. Ti mi thi im ch c mt loi tranzitor trng thi ng (ON).
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Chng 2: Cng ngh CMOSCu trc ca p-mos v n-mos
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2.1. Chun mch Transistor MOS
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2.2. Logic CMOSCng o:
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2.2. Logic CMOSNguyn tc ghep cng CMOS
Nguyn tc mc song song cho logic OR Nguyn tc mc ni tip cho logic ANDVit hm cho F (dng ba cacno nhm phn t 1) Vit hm cho F (dng ba cacno nhm phn t 0, hoc ly o ca F)Thit k vi mch VLSI - ASIC - FPGA
Nguyn tc thit k mch CMOS
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Slide 34
2.2. Logic CMOSThit k cng AND hai u voa F = a.b
b
fF = a.b {dng mch ni tip} F = a + b {dng mch song song}
0 0
1 0
0
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0
1Slide 35
2.2. Logic CMOSThit k cng AND hai u voVDD a
b
F = a.b b VSS
a
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Slide 36
2.2. Logic CMOSCng NAND 2 u vo:
a
F = a.bb
Xy dng: Bng chn l S mch:
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Slide 37
2.2. Logic CMOSCng OR 2 u vo:
ab
F= a+b
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Slide 38
2.2. Logic CMOSCng NOR 2 u vo:
a
F= a+b
Xy dng: Bng chn l S mch:
b
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Slide 39
2.2. Logic CMOSBi tp
Thit k mch thc hin hm logic sau s dng phn t c bn CMOS F = a.b.c // phn t and 3 u vo F = a + b + c // phn t or 3 u vo F = a.b.c + a.d + e
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2.2. Logic CMOSMch cht:
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2.2. Logic CMOSFlip-Flop:
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2.2. Cng truyn CMOSCng truyn:
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2.2. Cng truyn CMOSB ghp knh CMOS 2 u vo:
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Slide 44
2.2. Cng truyn CMOSB ghp knh CMOS 2 u vo:
MUX l phn t c bn to ra cc khi logic trong thit k cho ASIC MUX cn c dng thit k ra cc phn t logic c bn v cc mch logic. (s c chi tit chng 4)
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Slide 45
Chng 3: Cc ASIC lp trnh c
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Lin kt lp trnh cASIC/FPGA c cu to t cc phn t hoc cc khi logic c bn. Cc khi ny c lin kt vi nhau mt cch ton din, tc l mi tip im u c lin kt vi nhau Cc lin kt ny s tr nn dn khi khi c lp trnh, gi l antifuse phn cu trThi nguyn 08/2008 Thit k vi mch VLSI - ASIC - FPGA
Slide 47
3.1. Phn cu tr (antifuse)Tri ngc vi cu tr, phn cu tr c in tr rt ln, tng ng vi mt mch h.I=>0 R>>>
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3.1. Phn cu tr (antifuse)Khi c 1 dng in lp trnh khong 5mA chy qua, phn cu tr s tr ln dn inI=5mA R
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Slide 50
3.2. RAM tnhSRAM c th c tao ra bng vic lp trnh ASIC to ra cc phn t nh nh sau:Q READ or WRITE DATA Q
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Slide 51
3.3. Cng ngh EPROM v EEPROMCu trc 1 cell EPROMGate 2 GND +Vpp=12V Gate 1
Vi in p lp trnh >12V Vpp p vo drain, cc in t s nhy ln Gate1Thi nguyn 08/2008
Source
Drain
electrons
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Slide 52
3.3. Cng ngh EPROM v EEPROMCu trc 1 cell EPROMGate 2 GND +Vpp=12V Gate 1
Khi cc in t b by Gate1, transistor tr ln khng dn. Cell EPROM c lp trnhThi nguyn 08/2008
Source
Drain
No channel
Thit k vi mch VLSI - ASIC - FPGA
Slide 53
3.3. Cng ngh EPROM v EEPROMCu trc 1 cell EPROMGate 2 GND +Vpp=12V Gate 1
Khi cc in t b by Gate1, transistor tr ln khng dn. Cell EPROM c lp trnhThi nguyn 08/2008
Source
Drain
No channel
Thit k vi mch VLSI - ASIC - FPGA
Slide 54
3.3. Cng ngh EPROM v EEPROMCu trc 1 cell EPROMnh sng cc tm Gate 2 GND +Vpp=12V Gate 1
Khi tc ng bi nh sng cc tm, cc in t li tr v nn => transistor tr nn dn EPROM b xaThi nguyn 08/2008
Source
Drain
Thit k vi mch VLSI - ASIC - FPGA
Slide 55
3.3. Cng ngh EPROM v EEPROM
EEPROM cng tng t EPROM ch khc l thay v dng nh sng cc tm xa chip( tc y cc in cc v v tr nn) th loi ny cng c th dng in xa.
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Slide 56
Chng 4 Cell logic ca cc ASIC lp trnh c
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Slide 57
Dn nhpCc ASIC hoc cc FPGA u cu to t cc cell logic c bn, c b tr lin tip trn chip. C 3 loi cell c s dng:
Cell da trn b ghp knh Cell da vo bng tm kim Cell da vo mch logic di lp trnh c
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Slide 58
4.1. ACT ca Actel
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Slide 59
4.1.1. Module logic ca ACT 1Cc cell logic c bn trong h FPGA ACT ca Actel gi l cc cc module logic LM. H ACT 1 ch s dng mt loi LM
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Slide 60
4.1.1. Module logic ca ACT 1
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Slide 61
4.1.1. Module logic ca ACT 1Cc hm logic s c xy dng thng qua vic kt ni cc tn hiu logic n mt s hoc tt c cc ng vo ca cc module logic. Cc ng cn li s c ni vi VDD hoc GND.
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Slide 62
4.1.1. Module logic ca ACT 1V d mt hm logic c xy dng t 1 cell logic:
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4.1.2. /L khai trin Shannon tng ca nh l ny bt ngun t hm logic ca b ghp knh 2 u vo:F= S.A + S.BB 0 F A 1
S
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Slide 64
4.1.2. /L khai trin ShannonPht biu:Mi hm logic F c th c trin khai theo bin A nh sau: F = A.F(A=1) + A.F(A=0) Trong :
F(A=1) l biu din ca F vi A=1 F(A=0) l biu din ca F vi A=0
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4.1.2. /L khai trin ShannonVi d: F = A.B + A.B.C + A.B.C = A.(B.C) + A.(B + B.C) Vy mc ch l mi hm F cn phi chuyn v dng F = A.F(A=1) + A.F(A=0). Nhm s dng phn t MUX
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Slide 66
4.1.2. /L khai trin ShannonVi d thit k mch s dng ACT 1 cho hm sau: F = A.B + (B.C) + D
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Slide 67
4.1.3. To hm t ACT1S dng ACT1 to ra cc phn t logic c bn v cc hm logic thng dng
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4.1.3. To hm t ACT1Bi tp:1. Thit mch cho cc hm sau s dng ACT1 F1 = a.b.c.d F2 = a+b+c+d F3 = F3 2. Thit k b cng 4 bit s dng ACT1 3. p dng nh l shannon vo MUX gii bi 1 4. Thit mch thc hin hm sau:F = a + b + a.d + b.d
5. Thit k mch gii m ti a ch 314hThi nguyn 08/2008 Thit k vi mch VLSI - ASIC - FPGA
Slide 69
4.1.4 ACT 2 v ACT 3(a) The C-Module for combinational logic. (b) The ACT 2 SModule (c) The ACT 3 SModule. (d) The equivalent circuit (without buffering) of the SE (sequential element). (e) The sequential element configured as a positive-edge triggered D flip-flop.
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Slide 70
4.2 Xilinx LCA
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4.2.1 XC3000 CLBDa vo cc MUX lp trnh c F/G c th dc ni ti X/Y.
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Slide 72
4.2.1 XC3000 CLBBng tm kim (LUT Look up table) lp trnh c.
Xt hm F = a.b + c c bng trn l nh sau: a bGM
F
Fc
00 01 10 11 0 0 0 1
0GM
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1
1
1
1
Vi mi t hp u vo a,b,c bt k c c gii m tng ng ti mt trong LUT xc nh gi tr ca hm
Thit k vi mch VLSI - ASIC - FPGA
Slide 73
4.2.1 XC3000 CLB01 000 001 010
a
bc
0
GM
F
1
111
Look up table (EPROM)Thit k vi mch VLSI - ASIC - FPGA
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4.2.2 XC4000 Logic Block
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4.3 Altera MAXPhn t chnh ca Altera MAX l cc mng cng lp trnh c Thc cht l dy cc phn t not, and, or c tch hp vi s lng ln v mt IC, v cc hm logic c lp trnh bng vic lin kt cc phn t logic
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4.4 Altera MAX
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Slide 78
Pht trin mt ng dng bng vi mch lp trnh c
Bi ton bm nc Bi ton my git
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