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Reg. No. :

M.E. DEGREE EXAMINATION, JUNE 2010

Elective

VLSI Design

VL9261 ASIC DESIGN

(Common to M.E. Applied Electronics)

(Regulation 2009)

Time : Three hours Maximum : 100 Marks

Answer ALL QuestionsPART A (10 2 = 20 Marks)

1. What are the different types of gate array based ASICs?2. Draw a circuit for a positive-enabled latch using transmission gates.3. List out the drawbacks of SRAM programming technology.4. What is metastability?5. Distinguish between hard macro and soft macro.6. What is back annotation?7. List out the objective of BIST.8. Define fault propagation.9. Mention the objective of global routing.10. What are major problems with LVS check?

PART B (5 16 = 80 Marks)

11. (a) (i) Design a 4 bit carry look ahead adder. (6)(ii) Discuss the working of Wallace tree multiplication algorithm. (6)

(iii) Perform ( ) ( )24 using Booths algorithm. (4)

Or

(b) (i) Explain various types of programmable logic devices. (8)

(ii) Discuss the various steps involved in ASIC design flow with a neat

flowchart. (8)

12. (a) (i) Discuss in detail the Actel ACT logic module. (10)(ii) Consider the function ( ) ( ) DCBBAF ++= . Use Shannons

expansion theorem to expand F with respect to B :

21 FBFBF += . (6)

Or

Question Paper Code:J7797

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(b) (i) Draw the transfer characteristics of an inverting buffer with a veryhigh gain that has a switching threshold of 2.2 V and 300 mV

hysteresis. If the center of the hysteresis shifts by 0.3 V and +0.4 V

and the hysteresis varies from 260 mV to 350 mV calculate ( )minIHV

and ( )maxILV . (8)

(ii) Write short notes on metal-metal antifuse. (8)

13. (a) (i) Compare Actel ACT1, Actel ACT2 and Xilinx (XC 3000)programmable ASIC inter connect. (10)

(ii) Write a note on low level programmable languages. (6)

Or

(b) (i) Explain in detail the Alteras MAX 9000 interconnect scheme and

altera FLEX interconnect scheme. (10)

(ii) Create a vectored instance of eight inverters inv0 through

inv7. Write a netlist in internal and EDIF form and explain the

contents. (6)

14. (a) (i) Explain in detail the Boundary scan test. (10)(ii) Explain any two algorithms used for fault simulation. (6)

Or

(b) (i) Explain steps involved in a PODEM algorithm with a suitable

example. (8)

(ii) Explain in detail any two BIST architectures. (8)

15. (a) (i) Explain in detail the min-cut placement and eigenvalue placementalgorithms. (10)

(ii) Explain the steps involved in left edge algorithm for a two layer

channel routing. (6)

Or

(b) (i) Write a detailed note on clock routing and power routing. (10)

(ii) Distinguish between global routing and detailed routing. (6)

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