An HCI-Healing 60GHz CMOS Transceiver · 2015-03-08 · 19.5: An HCI-Healing 60-GHz CMOS...
Transcript of An HCI-Healing 60GHz CMOS Transceiver · 2015-03-08 · 19.5: An HCI-Healing 60-GHz CMOS...
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 0 of 30
Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura,
Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri,
Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi,
Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara,
Kenichi Okada, and Akira Matsuzawa
Tokyo Institute of Technology, Japan
An HCI-Healing 60GHz CMOS
Transceiver
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 1 of 30
Outline
• Motivation
• Hot-Carrier-Injection Issues,
Prior Arts and Proposed Solution
• Proposed HCI-Healing 60GHz TRX
• Detailed circuit implementation
• Measurement and Comparison
• Conclusion
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 2 of 30
Freq
(GHz)57 58 59 60 61 62 63 64 65 66
1 2 3 4
1.76 GHz
2.16 GHz
60GHz-Band Capability
Channels of IEEE 802.11ad standard
7.04Gbps/ch
in 16QAM
0.1 1 10 100
ISDB-TDVB-T
9-GHz BW@60-GHz band
Frequency (GHz)
Wir
ele
ss S
tan
dard
s
PDC
GSM
UMTS
GPSBlue-tooth UWB
WLAN
WiMAX
LTE
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 3 of 30
Hot-Carrier-Injection Issue in CMOS (1/2)
Large Vds,peak
HCI damage
Small Vds,peak
Low efficiency
Vds
t
VDD
Vds,peak=2VDD
η=50% Class-A
Vds
t
VDD
Vds,peak=1.5VDD
η=12.5% Class-A
CMOS power amplifier
Drain efficiency: η=Pout/PDC
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 4 of 30
Hot-Carrier-Injection Issue in CMOS (2/2)
Lifetime: the time when ∆IDS = 10% @ saturation
HCI damage
0
20
40
60
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VG (V)
I D(m
A)
VD=1.2 V
Stress cond.
VD=2.4V
VG=0.8V
1 hour
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 5 of 30
P-Substrate
Impact ionization
n+n+
Generated defects:Trapped charges &
Interface states
Isub
IG
Gate oxide
VG
VDVS ID
High field
Hot-Carrier-Injection Mechanism
Degrade Vt, mn, gm, ID, and lifetime
[*Y. Leblebici et al.,
JSSC 1993]
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 6 of 30
0
2
4
6
10100200 40 20 60
HCI Issue in Advanced CMOS
Process node (nm)
HCI aging ∝ 𝑬𝐥𝐚𝐭𝐞𝐫𝐚𝐥∝ 𝑽𝐝𝐬/𝑳𝐞𝐟𝐟
Nominal VDD**
Vds,peak for
same Vds,peak/Leff
Vo
ltag
e (V
)
HCI limited
Vds,peak=1.35V*
[*D. Stephens et al.,
RFIC 2009]
[**ITRS2013]
HCI issues more severe
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 7 of 30
HCI Issues for 60-GHz Applications
60-GHz power amplifier
Standard
1.0 V
L=65 nm (core Tr.)
fmax=220 GHz
2.4-GHz power amplifier
Thick oxide
2.5 V
L=250 nm (I/O Tr.)
fmax=40 GHz
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 8 of 30
Summary of Prior HCI Solutions@60GHz
Low VDD*
Better lifetime
Degraded output power, linearity and efficiency
[*M. Tanomura et al., ISSCC 2008] [**A. Siligaris et al., JSSC 2010]
Stack Transistor**
VDD=0.7V
Vds
t
VDD=1.2V
P1dB=10dBm
Low VDD or
Stack Tr. VDD=1.2V
P1dB=6dBm
P1dB=5dBm
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 9 of 30
PA1
PAn
Power
combining Output
(combiner,
antenna
array, etc.)
Compensate output power and linearity
Deteriorated efficiency can not be improved
[*J. Chen et al.,
ISSCC 2011]
Power Combining Techniques
Pin,n Pout,n
In
𝐏𝐀𝐄 =𝑷𝐨𝐮𝐭,𝐧 − 𝑷𝐢𝐧,𝐧
𝑰𝐧𝑽𝐃𝐃 𝐏𝐀𝐄 =
𝒏 × (𝑷𝐨𝐮𝐭,𝐧 − 𝑷𝐢𝐧,𝐧)
𝒏 × 𝑰𝐧𝑽𝐃𝐃 Individual: Combined: ≈
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 10 of 30
0
20
40
60
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VG (V)
I D(m
A)
VD=1.2 V
Proposed HCI-Healing Technique
Ultimate solution: Physically heal HCI damage
HCI damage
HCI healing How?
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 11 of 30
n+ n+ p+
VB
VG
VS
P-Substrate
VD
Proposed HCI Healing Mechanism (1/2)
Damage mechanism: trapped electrons
[Y. Leblebici et al., JSSC 1993]
Damaged
gate oxide
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 12 of 30
n+ n+ p+
VB
VG
VS
P-Substrate
VD
0V 2.2V
Proposed HCI Healing Mechanism (2/2)
Possible solution: charge ejection
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 13 of 30
0
20
40
60
80
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VG (V)
I D(m
A)
VD=1.2 V
Accelerated Meas.
Fresh
Damaged
Healed
Measured HCI-Healing ID-VG Curves
First HCI healing demonstration
Stress cond.
VD=2.4V
VG=0.8V
1 hour
Heal cond.
VB=2.2V
VG=VD=0V
1 second
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 14 of 30
HCI-Healing Function in Transistor
VH
Deep n-well
VG High voltage
VS
High Z
First HCI healing transistor
[**K. Miyaji et al.,
JJAP 2012]
High Z
n+ n+ p+p+
Deep n-well
n+ n+
High voltage
VB
VB
R
VHVG
VD
VS
Ejection of the trapped
electrons
EBG
EBD
[*T. Endoh et al.,
IEDM 1989]
Floating source* & low drain bias**
assisting ejection (memory cells)
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 15 of 30
VGT
VH
Deep n-well
VG
MIM TL TL
Deep n-well
VG VH
VH
Deep n-well
VG High voltage
VS
High Z
VDD
1.2 V
Equivalent circuit for
60-GHz operation
Equivalent circuit
for HCI healing
VD
VD
VB
HCI-Healing Transistor Module
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 16 of 30
VDD
Mp
VPA
Mn
RFin
RFout
VH
VGT
MIM TL
TL
VG6
S6c
S6
VD6
HCI-Healing Power Amplifier (1/3)
Proposed
HCI healing
block
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 17 of 30
VDD
Mp
VPA
Mn
RFin
RFout
VH
MIM TL
TL
VG6
VD6
VDD
VDD
GND
HCI-Healing Power Amplifier (2/3)
HCI healing
status
VH
Deep n-well
VG High voltage
VS
High Z
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 18 of 30
VDD
Mp
VPA
Mn
RFin
RFout
VH
MIM TL
TL
VG6
VD6
GND
VDD
GND
HCI-Healing Power Amplifier (3/3)
Deep n-well
VG VH
1.2 V
Vod
60GHz
operation
status VD
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 19 of 30
TX
ou
tpu
t
PA
LNA
RX
inp
ut
RF Amp.
RF Amp. Q Mixer
I Mixer
BB Amp.
BB Amp.
Control
signals
I+
I-
Q+
Q-Logic
Gain controlPower mgmt.HCI healing
VH
Ref.
40MHz20GHz PLL
HCI-healing block
60GHz QILO
60GHz QILO
I+
I-
Q+
Q-
RF Amp.
RF Amp.
I Mixer
Q Mixer
HCI-Healing TRX Block Diagram
Direct
Conversion
20GHz PLL+
60GHz QILO
Integrated
HCI-healing
function
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 20 of 30
TX
ou
tR
X in
QIL
O
PLL
Logic
LNA
2 m
m
2 mm
TX RX PLL Logic
Area (mm2) 0.79 1.01 0.27 0.21
RF Amp. & I Mixer
QIL
ORF Amp. & Q MixerHCI PA
RF Amp. & Q Mixer
RF Amp. & I MixerStandard
65 nm CMOS
Die Micrograph
Block Area
(mm2)
TX 0.79
RX 1.01
PLL 0.27
Logic 0.21
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 21 of 30
Measurements
• Transistor TEG
– DC stress lifetime
– AC stress lifetime
• Stand-alone PA TEG
– Pin-Pout with healing
– AC stress lifetime with healing
• TRX Board
– EVM versus Pout with healing
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 22 of 30
65 nm NMOSFET DC Stress Lifetime
1E+00
1E+02
1E+04
1E+06
1E+08
1E+10
0.4 0.5 0.6 0.7 0.8 0.91/VDS (1/V)
100
102
104
106
108
1010
Lif
eti
me
t (
s)
[*E. Takeda et al., EDL 1983]
VGS
VDS
VDS
t
V
Stress condition
VGS = 0.8 V 𝝉 = 𝑲 ∙ 𝒆
𝒃
𝑽𝑫𝑺 *
Lifetime = 63 years
@ VDS=1.2V
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 23 of 30
1
10
100
1E+02 1E+03 1E+04 1E+05
∆I D
Sa
t (%
)
Freq.=100 MHz
Pout=11 dBm
102 103 104 105
Time (s) [*L. Negre et al., JSSC 2012]
Vgs
Vds
Stress condition
t
0.8 V
1.2 V
Vds Vgs
∆𝑰𝐃𝐒𝐚𝐭 = 𝑨 ∙ 𝒕𝒏*
Lifetime = 2 hours
65 nm NMOSFET RF Stress Lifetime
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 24 of 30
Measured Pin-Pout of the PA
0
3
6
9
12
-30 -25 -20 -15 -10
Po
ut(d
Bm
)
Freq.=60 GHzVG6=0.7 V
Pin (dBm)
Fresh
Damaged
Healed
Symbols: P1dB
Accelerated Meas.
DC Stress-AC Meas.
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 25 of 30
1E-2
1E-1
1E+0
1E+1
1E+2
1E+31E+41E+51E+61E+71E+81E+91E+10
10-2
103 104 105 106
10-1
100
101
∆I D
6 (%
)
Fresh Tr.Stress Pout=7dBm
Healed Tr.Stress Pout=7dBm
Lifetime@10%1.2 year
Lifetime@10%81.2 years
102
107 108 109 1010
Time (s)
AC Stress-DC Meas.
Measured Lifetime of the PA
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 26 of 30
Measured TX EVM versus Pout
Fresh 9dBm
Stress cond.
12.5dBm with
VDD=1.5V (40hr)
Damaged 5dBm
Healing cond.
VB=2.2V 1sec.
Healed 8dBm -30
-27
-24
-21
-18
-2 0 2 4 6 8 10
Averaged TX Output Power (dBm)
TX
EV
M (
dB
)
Fresh
Damaged
Healed
IEEE802.11ad MCS12(16QAM) specification
7Gb/s
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 27 of 30
Ref. CMOS
Process
Data rate
(Modulation)
Pout
/each PA
(dBm)
TX
efficiency
Pout/PDC
(%)
HCI
healing
Core
area
(mm2)
Power
Consumption
Tokyo
Tech [1] 65nm
10.56Gb/s (64QAM)
28.16Gb/s (16QAM)
8.5* @TX EVM = -21dB
2.8 NO 3.9 TX: 251mW RX: 220mW
NEC [2] 90nm 2.6Gb/s (QPSK)
6 3.0 w/o PLL
NO 3.4 TX: 133mW RX: 206mW
w/o PLL
Panasonic
[3] 90nm
2.5Gb/s (QPSK)
1.9 @TX EVM = -19.6dB
0.4 NO 5.7 TX: 361mW RX: 260mW
Broadcom
[4] 40nm
4.6Gb/s (16QAM)
-4* @TX EVM = -23dB
0.5 NO 26.3†
TX: 1190mW RX: 960mW 16x16 array
This work 65nm 7Gb/s
(16QAM)
9.3 @TX EVM = -21dB
3.9 YES 2.3 TX: 218mW RX: 188mW
*Estimated from literature †Chip area
60GHz TRX Performance Comparison
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 28 of 30
– 60-GHz CMOS transceiver with HCI damage
healing function by using charge ejection
technique.
– 81-year lifetime without sacrificing the output
power and efficiency
– The transceiver demonstrates an EVM of -27.9dB
and can transmit 7Gb/s in 16QAM within 2.16GHz
bandwidth.
Conclusions
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 29 of 30
Acknowledgement
This work is partially supported by MIC,
SCOPE, MEXT, STARC, STAR, and VDEC in
collaboration with Cadence Design
Systems, Inc., Mentor Graphics, Inc.,
Synopsys Inc., and Agilent Technologies
Japan, Ltd.
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 30 of 30
References
[1] K. Okada, et al., “A 64-QAM 60GHz CMOS transceiver with 4-channel bonding,” IEEE
ISSCC, pp.346-347, 2014.
[2] M. Tanomura, et al., “TX and RX front-ends for 60 GHz band in 90 nm standard bulk
CMOS,” IEEE ISSCC, pp.558-559, 2008.
[3] T. Tsukizawa, et al., “A PVT-variation tolerant fully integrated 60 GHz transceiver for
IEEE 802.11ad,” IEEE VLSI Circuits, pp.123-124, 2014.
[4] M. Boers, et al., “A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface
and polarization diversity,” IEEE ISSCC, pp.344–345, 2014.
[5] Y. Leblebici, et al., “Modeling and Simulation of Hot-Carrier-Induced Device
Degradation in MOS Circuits,” IEEE JSSC, pp.585-595, Vol.28, No.5, May 1993.
[6] E. Takeda, et al., “An empirical model for device degradation due to hot-carrier
injection,” IEEE Electron Device Letters, Vol.EDL-4, No.4, pp.111-113, Apr. 1983.
[7] L. Negre, et al., “Reliability characterization and modeling solution to predict aging of
40-nm MOSFET DC and RF performances induced by RF stress,” IEEE JSSC, Vol.47,
No.5, pp.1075-1083, May 2012.
19.5: An HCI-Healing 60-GHz CMOS Transceiver
© 2015 IEEE International Solid-State Circuits Conference 31 of 30
References
[8] A. Siligaris, et al., “A 60 GHz power amplifier with 14.5 dBm saturation power and 25%
peak PAE in CMOS 65 nm SOI,” IEEE JSSC, Vol.45, No.7, pp.1286-1294, Jul. 2010.
[9] J. Chen, et al., “A compact 1V 18.6 dBm 60 GHz power amplifier in 65 nm CMOS,”
IEEE ISSCC, pp.432-433, 2011.
[10] K. Miyaji, et al., “Zero additional process, local charge trap, embedded flash memory
with drain-side assisted erase scheme using minimum channel length/width standard
CMOS single transistor cell,” Japanese J. Appl. Phys., Vol.51, pp.04DD02-1–04DD02-
7, Apr. 2012.
[11] D. Stephens, et al., “RF reliability of short channel NMOS devices,” IEEE RFIC,
pp.343-346, 2009.
[12] T. Endoh, et al., “New design technology for EEPROM memory cells with 10 million
write/erase cycling endurance,” IEEE IEDM, pp.599-602, 1989.