Allegro SPB V16 Advance¸文...Import Logic – Other 1.Create netlist from Capture Tools > Create...

Allegro SPB V16 Advance Allegro SPB V16 Advance

Allegro SPB Allegro SPB 16.216.2 Advance Advance

Import Logic

Back Annotate

Netlist Compare

Advanced Placement

Constraint Management

Differential Pair

Import Logic

Other

Cadence

IImport Logicmport Logic –– OtherOther

• 利用Other的方式轉出或者導入netlist的方式

Allegro Netlist.net file

Allegro NetlistAllegro Netlist.net file

Cadence AllegroCadence AllegroCadence Allegro

Orcad CaptureOrcad Capture CISOrcad CaptureOrcad Capture

Orcad Capture CISOrcad Capture CIS SchematicSchematic

PCB layoutPCB layout

Create netlist(Other allegro.dll)

Import Logic(Other)

Device.txt file

DeviceDevice.txt file +

Export Logic(Other)

Back Annotate

Capture Back Annotation.swp file

CaptureCapture Back AnnotationBack Annotation.swp file

優點 : 在Capture中定義可以相對簡單缺點 : 導入netlist和回編線路圖對複雜,

導入時需要Device file,回編時需要提供Swp file


1.Create netlist from Capture

Tools > Create Tools > Create NetlistNetlist > Other> Other注意：

在9.2版後,程式中已經沒有含allegro.dll必須在9.2之前的版本中allegro.dll複製到新的版本中

放置的路徑home：\Cadence\SPB15.7\Capture\Netforms）

{PCB Footprint}! {PCB Footprint}

Netlist 格式: DeviceValue

Part Reference

nets

• 利用Other的方式轉出或者導入netlist的方式

Allegro Netlist 格式: (其中[]的內容可以省略)[PCB Footprint] ! Device! [Value] ! [ Tolerance]；Reference

2. Import netlist to Allegro – Other

Import > Logic > OtherImport > Logic > Other


•Syntax check only –只做語法check

•Supersede all logical data –取代現有的Logic

•Append device file log –將所有使用到的device加到netin log

•Allow etch removal during ECO –當netlist有所變動時則會將相關的走線刪除

•Ignore FIXED property –忽略Fixed設定

• 針對Cadence直接導入方式,簡稱新轉法

Cadence AllegroCadence AllegroCadence Allegro

Orcad CaptureOrcad Capture CISOrcad CaptureOrcad Capture

Orcad Capture CISOrcad Capture CIS SchematicSchematic

PCB layoutPCB layout

Create netlist(Capture Allegro)

Import Logic(Cadence Capture) .brd

Back Annotate(Allegro)

Create updateAllegro board

Netlist file directoryPst*.dat files

NetlistNetlist file directoryfile directoryPst*.dat files

IImport Logicmport Logic –– CadenceCadence

優點 : Capture可以順利跟Allegro做雙向的溝通缺點 :有條件規範Capture與Allegro的Lib

直接開啟Allegro(參考Import Board File將新資料寫入Output Board File中)

輸出netlist路徑


1.Create netlist from Capture

Tools > Create Tools > Create NetlistNetlist > Allegro> Allegro

• 利用Allegro的方式轉出或者導入netlist的方式


2. Import netlist to Allegro – Allegro

Import > Logic > AllegroImport > Logic > Allegro

• Property Changes• Ref-des Changes• Pin an Gate Swaps

Back Back annotation(Cadenceannotation(Cadence))

• Property Changes• Ref-des Changes• Pin an Gate Swaps

Back Back annotation(Otherannotation(Other))

Design Compare Design Compare

Tools\Design Compare

Placement in AreasALT_SYMBOLAssign RdfDesAutomatic Swapping of Functions and Pins

Advanced Placement

1. 針對 symbols2. 針對 board

1. Shape – Polygon2. Class – Board Geometry

Subclass – Top_Room3. Edit – property

Room_Type當你轉 netlist 的方式是用Capture to Allegro

當你轉 netlist 的方式是用Other – Allegro.dll

Placement in Areas Placement in Areas

1. 當你是用Netlist – Allegro轉Netlist2. 當你是用Other – Allegro轉Netlist

在在capturecapture中對中對partpart設定設定propertyproperty

定義零件外型替換可在各零件的 device 檔中宣告可替換的零件外型語法為PACKAGEPROP ALT_SYMBOLS '(Subclass:Symbol,...;Subclass:Symbol,...)'Subclass 可為 TOP 或 T 指正面零件, BOTTOM 或 B 指正面零件.若沒指定則視為正面. 例如 C0603 可換成 C0805或C1206(DEVICE FILE: C0603) PACKAGE C0603 PACKAGEPROP ALT_SYMBOLS '(C0805,C1206)'PINCOUNT 2 END

在在Device File Device File 中加入參數中加入參數

ALT_Symbol ALT_Symbol 設定設定

Place Place –– Manually Manually 選擇滑鼠右鍵選擇滑鼠右鍵 Edit Edit –– movemove

ALT_Symbol ALT_Symbol 用法用法

兩者的差別在於Place – 有一個下拉式的選項讓你做選擇Move – 漸進式的替換

Logic Logic –– Assign Assign RefDesRefDes

Assign Assign RdfDesRdfDes

先在Options中寫入要替換的RefDes在點選Board上遇替換的Symbol注意:替換的零件必須存在於Database中其腳Pin,電氣特性需要一致才可以互換

Place – Swap – PinsPlace – Swap – FunctionsPlace – Swap – Components

Swapping of Functions and PinsSwapping of Functions and Pins

• 當你是用 Netlist – Allegro 轉 Netlist• 當你是用 Other – Allegro 轉 Netlist

定義零件邏輯互換以 DDR184 為例宣告接點可互換為 PINSWAP . 宣告邏輯閘可互換則為各FUNCTION Gate

(Device file for 7400)PACKAGE DIP14Package name (PCB Footprint)CLASS IC Placement classPINCOUNT 14 Total number of pins in devicePINORDER 7400 I0 I1 O Defines pin names for a sectionPINUSE 7400 IN IN OUT Specifies pin functions(relates to PINORDER)PINSWAP 7400 I0 I1 Specifies swappable pinsFUNCTION G1 7400 1 2 3 Defines a section (relates to PINORDER)FUNCTION G2 7400 4 5 6 DittoFUNCTION G3 7400 9 10 8 DittoFUNCTION G4 7400 12 13 11 DittoPOWER VCC ; 14 Specifies power pinsGROUND GND ; 7 DittoEND

Swapping PinsSwapping Pins

Place – Swap – Components‧需注意的事項

‧Pin腳的數量‧電器的特性

‧相同的包裝

Swapping FunctionsSwapping Functions

定義零件邏輯互換以 7400 為例宣告接點可互換為 PINSWAP . 宣告邏輯閘可互換則為各FUNCTION Gate

(Device file for 7400)PACKAGE DIP14 Package name (PCB Footprint)CLASS IC Placement classPINCOUNT 14 Total number of pins in devicePINORDER 7400 I0 I1 O Defines pin names for a sectionPINUSE 7400 IN IN OUTSpecifies pin functions(relates to PINORDER)PINSWAP 7400 I0 I1 Specifies swappable pinsFUNCTION G1 7400 1 2 3 Defines a section (relates to PINORDER)FUNCTION G2 7400 4 5 6 DittoFUNCTION G3 7400 9 10 8 DittoFUNCTION G4 7400 12 13 11 DittoPOWER VCC ; 14 Specifies power pinsGROUND GND ; 7 DittoEND

Constraint ManagementConstraint Management UIHierarchical Rule Management

A High-Speed Design Flow

Allegro DesignEntry

Topology Editor

SchematicDatabase

Boardfile

Netrev

Front-to-back Flow

Packagergenfeed

Exploration Design Capture Design Realization

Allegro PCB SI Allegro PCB Editor

Constraint Manager

Topology Editor

Topology Editor

Board file CM data

sig modelsTopologyTemplatesElectrical

CSetsSchematic

ViewConstraint

View

Schematic DB

Constraint ManagementConstraint Management

Hierarchical Rule Management

OVERRIDES

INHERITANCESystem Multi-PCB Configuration

Design Single PCB

Bus Named collection of Diff Pairs, XNets, or Nets

Diff Pair Pair of XNets or Nets to be routed differentially

XNet eXtended Net comprised of Nets connected through resistors or connectors

Net Basic connectivity as defined in schematic

Match Group Named collection of Pin Pairs for match delay requirements

Pin Pair Pair of Pins implying a connection that must be on the same XNet or Net

– Highest object is the System.

– Goal is to assign constraints at the highest possible level.

– Special cases can be handled by overrides at a lower level.


Hierarchical Rule Management


Invoking the Constraint Manager

Physical Layout: Setup > Constraints > ElectricalSchematic Entry: Tools > Constraints > Edit

Icon:

Standalone: consmgrWorksheetselector

Worksheetdisplay


Selecting a Worksheet

– Tree widgets are used to access worksheets.

– The top-most categories are ECSets and Nets.

– Under each category, constraints and properties are divided by discipline.• These can be opened for access to

entire workbook.• Bottom-most expansion will open

specific tab in workbook.

Workbook Worksheet


The User Interface for Managing Constraints

Object column

ECSetreference

Constraintvalues


Design Objects

The first column in every spreadsheet:– Displays the objects in a hierarchical

fashion – Is collapsible– Allows for setting constraints at the

highest level and applying overrides at lower levels as necessary


Electrical Constraint Set References

The second column for Net spreadsheets:

– Contains the ECSet that is applied to that object, which can be a Bus, Diff Pair, XNet, or Net

– Is usually in collapsed form to appear as a “check box”

– Can be expanded to display actual ECSet name


Viewing Constraint ValuesColumns define a constraint:

– For ECSets the columns contain constraint values.

– For Nets additional columns contain result information.


Controlling Colors

– Cells are color coded to indicate inheritance for constraints and status for results.

Use View >Options tochange cellcolor coding.


Status Indicators

– Located in lower left-hand corner of user interface window

– Provides information on specific items in the display• Progress Meter for simulations• Brief descriptions of commands• Reasons why items are inactive

out

Placing cursor overobject will result inmessage below


Basic Operations of Constraint Management

Usage can be divided into three basic functions:1. Creating Electrical Constraint Sets2. Making associations between ECSets and design

objects3. Analyzing to see if constraints are met


Creating an Electrical Constraint Set

– An ECSet can be created from scratch.

– Prompt will appear for name.

– Result is empty ECSet.

Similar set of options is available with RMB pick in Objects column.


Copying Electrical Constraint Sets

ECSets can be copied from existing ECSets.


Referencing Electrical Constraint Sets

ECSet references can be driven from ECSet or Net objects.


Analyzing ConstraintsAnalyze > Analysis Modes

Analyze > Settings


Constraint Management Summary– Create ECSet

• Create an empty ECSet to edit later either in worksheet or Topology Editor

• Import (*.top on disk)• Copy from another ECSet• Create from Net object• Extract Net Object into Topology Editor then Update Constraint

Manager icon or File > Update– Associate ECSets and Net Objects

• Reference from ECSet• Reference from Net Object

– Analyze Constraints• DRC system based• Simulation

(PCB SI)(PCB SI)

(PCB SI)

(PCB SI)


Differential Pair Overhaul• Logic >Assign Differential Pair• Constraints > Spacing rule set • Route > Connect• Line Spacing• Cornering• Via Patterns• Single Trace Mode

provide the best service

Differential Pair agendaDifferential Pair agenda

Differential Pair proper nounDifferential Pair proper noun

先認識一下新增的專有名詞a.Calculator – 可由User 設定的Impedance 計算線寬, 線距.., 存在於setup > constints> ecsets > diff pair values 中

a.Primary Gap – 兩條線主要的間距b.Line Width – 兩條線主要的線寬c.Neck Gap/Width – 兩條線次要的線寬與線距d. Coupled Tolerance +/- --兩條線的線距誤差值e.Min Line Spacing – 兩條線的最小間距f.Max Uncoupled Length – 兩條對線無法走在一起時,可允許的線長g.Phase Tolerance – 兩條線可允許的誤差值h.Pseudo Segment – Uncoupled Length 的線段用該層的DRC顏色表示出來,如下圖:

Differential Pair GenerateDifferential Pair Generate

Logic Logic –– Assign Differential PairAssign Differential Pair

可分成自動與手動兩種:•自動Auto Generate –找出對線的+-字元舉例Usb0++;Usb0--•手動Diff Pair information可用手動的方式自行尋找對線的名稱與編輯

Differential Pair Setup RuleDifferential Pair Setup Rule

Differential Pair Setup RuleDifferential Pair Setup Rule

點選點選AssignAssign進行進行RuleRule的配對的配對

Add connect with RMB options (Add connect with RMB options (viasvias, necking), necking)

Differential Pair RouterDifferential Pair Router

在Property或ECSET 中Neck mode 有設定此功能才有作用

Single trace modeSingle trace mode

雖然SPB16.X新的走線方法是兩條線一起走,不習慣的使用者也可以將他恢復單條線走線的模式,Route > ConnectRoute > Connect 中按滑鼠右鍵,點選Single trace modeSingle trace mode 結果如下圖:


若要恢復兩條線一起走,只要再點選一次再點選一次Single trace modeSingle trace mode 即可


Slide of DP object, group slide of several pairsSlide of DP object, group slide of several pairs

在Slide的功能裡,對Diff Pair Slide可以兩條線一起做 ,如下圖:••SlideSlide 按右鍵選擇CutCut

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