JISEAT

ISSN: 2454-9606

Journals for International Shodh in Engineering and Technology

Website: http://jiseat.com (Volume 02, Issue 01, January 2017)

A Review of AMBA based Memory Controller

Ashutosh Kumar Singh

akzhse@gmail.com

Anshul Soni

soni.anshulec14@gmail.com

Ashish Chouhan

ashish.chouhan87@gmail.com

Abstract – Today’s system-on--chip (SOC) is designed

with reusable intellectual property cores to meet short

time to market requirements. Embedded systems design

focuses on low Power dissipation and system-on-chip. A

reliable on-chip communication standard is a must in

any SOC. This paper gives an informative review about

the bus interfaces of Advanced Microcontroller Bus

Architecture (AMBA).

Keywords –AHB, AMBA, FIFO, RAM, ROM, VHDL.

I. INTRODUCTION

The increase in computational capacity measured in

recent years in all device electronic is bound to

double flush with the miniaturization of

components, and then with the integration of

multiple structures on the same chip. Incorporating,

for example, on the same die (the chip of

semiconductor material that all enclosed inside of

the package is the real CPU chip) the

communication devices with the external

(coprocessors, Ethernet controller, controller USB,

memory controller etc.) allows at the same time to

reduce in size and consumption but also to increase

the overall performance of the overall system

increasing the speed with which data can be

transferred between the different structures

integrated.

Despite this fusion of heterogeneous modules, the

resulting system, called SoC (System on Chip)

continues to meet the classical architecture for a

processor formalized by the mathematician John

Von Neumann and distinguished by a unit

processing (in turn integral to an internal control

unit), a bus system, the system memory and the units

of Input / Output most suitable according to the

destination d 'use of the SoC. In order to achieve this

kind of SoC, current technology offers developers

the possibility to choose between then utilization of

FPGA (Field Programmable Gate Array) or circuits

integrated ASIC (Application Specific Integrated

Circuit), with these seconds that you make prefer the

first to achieve better performance and better

utilization resource, first area, while the FPGA

appeal more successful thanks to the flexibility

offered by the same programming via software that

them It makes it highly competitive in terms of costs,

in the case of small productions scale or in the

prototyping stages, compared with slightly lower

performance.

Whatever the technology used for the realization of

the desired SoC, a point common between the FPGA

and ASIC is represented by the languages used in the

process of design and interpretable by the software

tools dedicated, for a description of the behaviour

and characteristics of the product that you want to

achieve. Among the various languages, said HDL

(Hardware Description Language) for their scope

application, if they have chosen the one called

VHDL (VHSIC Hardware Description Language).

This turns out to have some traits in common with

the classical languages programming, such as if-

then-else constructs and arithmetic operations

logical, but unlike the latter it allows to describe

some competitive features (Performed

simultaneously) in a much more natural compared to

other languages that as they can lean on the thread

management. This difference is due to the VHDL

language and permitted because with this you go to

describe directly the hardware dedicated to the

performance of a particular operation, while the

more traditional programming languages (C, C ++,

Java) the High-level programmer describes the

operations to be subsequently adapted to be able to

be carried out by a microprocessor or some generic

system that, not necessarily being optimized for

these tasks, could not have the necessary hardware

resources required to fully parallelize the operations.

The realization of an integrated circuit process

involves a series of steps that lead by a higher

abstraction level towards a lower level of

abstraction. The set of these steps is the design flow

VLSI (Very Large Scale Integration) composed of

the following main phases: Functional Description:

Allows us to draw up the functional specifications

JISEAT

ISSN: 2454-9606

Journals for International Shodh in Engineering and Technology

Website: http://jiseat.com (Volume 02, Issue 01, January 2017) and any limits required (area - performance -

consumption); algorithmic Description: Specifies

the ordered sequence of operations leading all

obtaining the desired function; Description RTL

(Register Transfer Level) At this level they

introduce resources necessary physical (logical

arithmetic operations, registers, mux-demux, etc.)

and the bond time between these structures

represented by the clock; logic description: the

circuit is represented using the logic gates

combinatorial and sequential;

Description: What are geometrically defined masks

and interconnections used for the realization of the

integrated circuit. The transition from one level of

description to the next called synthesis (algorithmic

- Logic - RTL - physical) can be automatic or, in

some cases, require the designer definition of

constraints and the choice between several possible

solutions. For each synthesis carried out must

necessarily be followed by a verification and

simulation phase to ensure that the translation of the

circuit from a high level of abstraction to a more low,

showing still correspond to what initially requested

to the system. To do so a second circuit, or software

model is almost always used, which it acts as a test

bench (testbench) responsible for providing all the

necessary signals for stimulate the component under

test. The inputs from the circuit and the answers

offered below examination are then analyzed using

the simulation tools, mostly software, through which

it will be possible to verify the correspondence of

responses obtained with those expected.

II. INTRODUCING THE AMBA AHB

AHB is a new generation of AMBA bus which is

intended to address the requirements of high-

performance synthesizable designs. It is a high

performance system bus that supports multiple bus

masters and provides high bandwidth operation.

AMBA AHB implements the features required for

high performance, high clock frequency systems

including:

Burst transfers

Split transactions

Single-cycle bus master handover

Single-clock edge operation

Non-tristate implementation

Wider data bus configurations

(64/128 bits)

Bridging between this higher level of bus and the

current ASB/APB can be done efficiently to ensure

that any existing designs can be easily integrated. An

AMBA AHB design may contain one or more bus

masters, typically a system would contain at least the

processor and test interface. However, it would also

be common for a Direct Memory Access (DMA) or

Digital Signal Processor (DSP) to be included as bus

masters. The external memory interface, APB

Bridge and any internal memory are the most

common AHB slaves. Any other peripheral in the

system could also be included as an AHB slave.

However, low-bandwidth peripherals typically

reside on APB.

A typical AMBA AHB system design contains the

following components:

i. AHB master: A bus master is able to

initiate read and write operations by

providing an address and control

information. Only one bus master is

allowed to actively use the bus at any

one time.

ii. AHB slave: A bus slave responds to a

read or write operation within a given

address-space range. The bus slave

signals back to the active master the

success, failure or waiting of the data

transfer.

iii. AHB arbiter: The bus arbiter ensures

that only one bus master at a time is

allowed to initiate data transfers. Even

though the arbitration protocol is

fixed, any arbitration algorithm, such

as highest priority or fair access can be

implemented depending on the

application requirements. An AHB

would include only one arbiter,

although this would be trivial in single

bus master.

iv. AHB decoder: The AHB decoder is

used to decode the address of each

transfer and provide a select signal for

the slave that is involved in the

transfer. A single centralized decoder

is required in all AHB

implementations.

III. INTRODUCING THE AMBA APB

The APB is part of the AMBA hierarchy of buses

and is optimized for minimal power consumption

and reduced interface complexity. The AMBA APB

appears as a local secondary bus that is encapsulated

as a single AHB or ASB slave device. APB provides

JISEAT

ISSN: 2454-9606

Journals for International Shodh in Engineering and Technology

Website: http://jiseat.com (Volume 02, Issue 01, January 2017) a low-power extension to the system bus which

builds on AHB or ASB signals directly. The APB

Bridge appears as a slave module which handles the

bus handshake and control signal retiming on behalf

of the local peripheral bus. By defining the APB

interface from the starting point of the system bus,

the benefits of the system diagnostics and test

methodology can be exploited. The AMBA APB

should be used to interface to any peripherals which

are low band width and do not require the high

performance of a pipelined bus interface. The latest

revision of the APB is specified so that all signal

transitions are only related to the rising edge of the

clock. This improvement ensures the APB

peripherals can be integrated easily into any design

flow, with the following advantages:

High-frequency operation easier to

achieve.

Performance is independent of the

mark-space ratio of the clock.

Static timing analysis is simplified by

the use of a single clock edge.

No special considerations are required

for automatic test insertion.

Easy integration with cycle-based

simulators.

Many Application Specific Integrated

Circuit (ASIC) libraries have a better

Selection of rising edge registers.

These changes to the APB also make it simpler to

interface it to the new AHB. An AMBA APB

implementation typically contains a single APB

bridge which is required to convert AHB or ASB

transfers into a suitable format for the slave devices

on the APB.

The bridge provides latching of all address, data and

control signals, as well as providing a second level

of decoding to generate slave select signals for the

APB peripherals. All other modules on the APB are

APB slaves. The APB slaves have the following

interface specification:

Address and control valid throughout

the access (un-pipelined)

Timing can be provided by decode

with strobe timing (un-clocked

interface)

Zero-power interface during non-

peripheral bus activity (peripheral bus

is static when not in use)

Write data valid for the whole access

(allowing glitch-free transparent latch

implementations).

IV. AMBA SIGNAL NAMES

All AMBA signals are named such that the first

letter of the name indicates which bus the signal is

associated with.

A lower case n in the signal name indicates that the

signal is active LOW, otherwise signal names are

always all upper case.

Test signals have a prefix T regardless of the bus

type AHB signal prefixes-H indicates an AHB

signal. For example, HREADY is the signal used to

indicate that the data portion of an AHB transfer can

complete. It is active HIGH.

APB signal prefixes-P indicates an APB signal. For

example, PCLK is the main clock used by the APB.

Choice of bus

Before deciding on which bus or buses should use in

system should consider the following:

Choice of system bus

System bus and peripheral bus

When to use AMBA AHB/ASB or

APB

Choice of system bus-Both AMBA AHB and ASB

are available for use as the main system bus.

Typically the choice of system bus will depend on

the interface provided by the system modules

required The AHB is recommended for all new

designs, not only because it provides a higher

bandwidth solution, but also because the single-

clock-edge protocol results in a smoother integration

with design automation tools used during a typical

ASIC development. System bus and peripheral bus-

Building all peripherals as fully functional AHB or

ASB modules is feasible but may not always be

desirable:

In designs with a large number of

peripheral macrocells the increased

bus loading may increase power

dissipation and sacrifice performance.

Where timing analysis is required, the

slowest element on the bus will limit

the maximum performance.

Many simple peripheral macrocells

need latched addresses and control

signals as opposed to the high-

bandwidth macrocells which benefit

from pipelined signalling.

Many peripheral functions simply

require a selection strobe which

conveys macrocell selection and

read/write bus operation, without the

requirement to broadcast the high-

frequency clock signal to every

peripheral.

JISEAT

ISSN: 2454-9606

Journals for International Shodh in Engineering and Technology

Website: http://jiseat.com (Volume 02, Issue 01, January 2017) When to use AMBA AHB/ASB or APB- A full

AHB or ASB interface is used for:

Bus masters

On-chip memory blocks

External memory interfaces

High-bandwidth peripherals with

FIFO interfaces

DMA slave peripherals

A simple APB interface is recommended for:

Simple register-mapped slave devices

Very low power interfaces where

clocks cannot be globally routed

Grouping narrow-bus peripherals to

avoid loading the system bus.

V. AMBA SPECIFICATION

The following points should be considered when

reading the AMBA specification:

Technology independence

Electrical characteristics

Timing specification

Technology independence: AMBA is a technology-

independent on-chip protocol. The specification

only details the bus protocol at the clock cycle level.

Electrical characteristics: No information regarding

the electrical characteristics is supplied within the

AMBA specification as this will be entirely

dependent on the manufacturing process technology

that is selected for the design.

Timing specification: The AMBA protocol defines

the behaviour of various signals at the cycle level.

The exact timing requirements will depend on the

process technology used and the frequency of

operation.

VI. INTRODUCING THE AMBA AHB

AHB is a new generation of AMBA bus which is

intended to address the requirements of high-

performance synthesizable designs. It is a high

performance system bus that supports multiple bus

masters and provides high bandwidth operation.

AMBA AHB implements the features required for

high performance, high clock frequency systems

including:

Burst transfers

Split transactions

Single-cycle bus master handover

Single-clock edge operation

Non-tristate implementation

Wider data bus configurations

(64/128 bits)

Figure 1: AMBA AHB Block diagram

Bus Interconnection

The AMBA AHB bus protocol is designed to be

used with a central multiplexor interconnection

scheme. Using this scheme all bus masters drive out

the address and control signals indicating the

transfer wish to perform and the arbiter determines

which master has its address and control signals

routed to all of the slaves. A central decoder is also

required to control the read data and response signal

multiplexor, which selects the appropriate signals

from the slave that is involved in the transfer. Figure

1.2 illustrates the structure required implement an

AMBA AHB design with three masters and four

slaves.

Basic Transfer

In AHB transfer consists of two distinct sections:

1. The address phase, which lasts

only a single cycle.

2. The data phase, which may

require several cycles.

This is achieved using the HREADY signal Figure 2

shows the simplest transfer, one with no wait states.

Figure 2: Simple transfer

JISEAT

ISSN: 2454-9606

Journals for International Shodh in Engineering and Technology

Website: http://jiseat.com (Volume 02, Issue 01, January 2017) When a transfer is extended in this way it will have

the side-effect of extending the address phase of the

following transfer. This is illustrated in Figure 3

which shows three transfers to unrelated addresses

A, B & C.

Figure 3: Multiple Transfer

VII. LITERATURE REVIEW

Shilpa Rao and Arati S. Phadke,

“Implementation of AMBA compliant

Memory Controller on a FPGA”,

IJETEE, 2013.

As microprocessor performance has relentlessly

improved in recent years, it has become increasingly

important to provide a high-bandwidth, low-latency

memory subsystem to achieve the full performance

potential of these processors. In the past years,

improvements in memory latency and bandwidth

have not kept pace with reductions in instruction

execution time. Caches have been used extensively

to patch over this mismatch, but some applications

do not use caches effectively. The result is that the

memory access time has been a bottleneck which

limits the system performance. A Memory

Controller is designed to avoid this problem. The

Memory Controller is a digital circuit which

manages the flow of data going to and from the main

memory. It can be a separate chip or can be

integrated into the system chipset. This paper

revolves around building an Advanced

Microcontroller Bus Architecture (AMBA)

compliant Memory Controller as an Advanced

High-performance Bus (AHB) slave. The whole

design is captured using VHDL, simulated with

ModelSim and configured to a FPGA target device

belonging to the Virtex4 family using Xilinx.

Archana C. Sharma1, Prof.Zoonubiya Ali,

“Construct High-Speed SDRAM

Memory Controller Using Multiple

FIFO's for AHB Memory Slave

Interface”, IJETAE, 2013.

The development of SOC design methodology has

increased the ability to pack a lot of logic into a

single chip and thus, has paved the way for compact

devices, these devices integrate several components

from different vendors and performing different

functionality on a single chip. Bus based

communication protocols have been proved very

efficient for interconnecting these components.

Advanced High performance bus (AHB) is a very

popular communication protocol for SOCs. This

protocol supports high speed communication and is

thus, very apt for high speed communication

between devices. Today's issue is the speed of

fetching data from memories is unable to cope up

with speed of processors since processors are getting

faster day by day and memories getting bulky, hence

fast memory controllers are needed that eventually

increases memory efficiency. Memory controller is

responsible to match speed of processor and

memory one and the other side, so as to enable

seamless communication. The challenge in

interfacing SDRAM to AHB lies in the fact that the

latency of SDRAM is not one cycle and thus, the idle

times of AHB bus increase and thus, leading to

underutilization of bus resources. In this project we

develop a memory controller that aims at reducing

the latency of SDRAM access by using local FIFO

to temporarily store the data to and from the

SDRAM.

S. Lakshma Reddy, A .Krishna Kumari,

“Architecture of An AHB Compliant

SDRAM Memory Controller”,

International Journal of Innovations in

Engineering and Technology, 2013.

Microprocessor performance has improved rapidly

these years. In contrast, memory latencies and

bandwidths have improved little. The result is that

the memory access time has been a bottleneck which

limits the system performance. As the speed of

fetching data from memories is not able to match up

with speed of processors. So there is the need for a

fast memory controller. The responsibility of the

controller is to match the speeds of the processor on

one side and memory on the other so that the

communication can take place seamlessly. Here we

have built a memory controller which is specifically

targeted for SDRAM. Certain features were

included in the design which could increase the

overall efficiency of the controller, such as,

searching the internal memory of the controller for

the requested data for the most recently used data,

instead of going to the Memory to fetch it. The

memory controller is designed which compatible

with Advanced High-performance Bus (AHB)

which is a new generation of AMBA bus. The AHB

is for high-performance, high clock frequency

system modules. The AHB acts as the high-

performance system backbone bus.

Arun G, Vijaykumar T, “Improving

Memory Access time by Building an

JISEAT

ISSN: 2454-9606

Journals for International Shodh in Engineering and Technology

Website: http://jiseat.com (Volume 02, Issue 01, January 2017)

AMBA AHB compliant Memory

Controller”, IJARCET, 2012.

Memory access time has been a bottleneck in many

microprocessor applications which limits the system

performance. Memory controller (MC) is designed

and built to attacking this problem. The memory

controller is the part of the system that, well, controls

the memory. The memory controller is normally

integrated into the system chipset. This paper shows

how to build an Advanced Microcontroller Bus

Architecture (AMBA) compliant MC as an

Advanced High-performance Bus (AHB) slave. The

MC is designed for system memory control with the

main memory consisting of SRAM and ROM.

Additionally, the problems met in the design process

are discussed and the solutions are given in the

paper.

S.Ramakrishna, K.Venugopal,

B.VijayBhasker, R.Surya Prakash Rao,

“HDL Implementation of AMBA-AHB

Compatible Memory Controller”,

IJCER, 2012.

Microprocessor performance has improved rapidly

these years. In contrast, memory latencies and

bandwidths have improved little. The result is that

the memory access time has been a bottleneck which

limits the system performance. Memory controller

(MC) is designed and built to attacking this problem.

The memory controller is the part of the system that,

well, controls the memory. The memory controller

is normally integrated into the system chipset. This

paper shows how to build an Advanced

Microcontroller Bus Architecture (AMBA)

compliant MC as an Advanced High-performance

Bus (AHB) slave. The MC is designed for system

memory control with the main memory consisting of

SRAM and ROM. Additionally, the problems met in

the design process are discussed and the solutions

are given in the paper.

Jayapraveen. D and T. Geetha Priya,

“Design of memory controller based on

AMBA AHB protocol”, Elixir

International Journal, 2012.

The performance of a computer system is heavily

dependent on the characteristics of its interconnect

architecture. A poorly designed system bus can

throttle the transfer of instructions and data between

memory and processor, or between peripheral

devices and memory. This communication

bottleneck is the focus of attention among many

microprocessor and system manufacturers have

adopted a number of bus standards. Hence memory

access time has been a bottleneck which limits

system performance. Memory controller (MC) is

designed to tackle this problem. The Advanced

Microcontroller Bus Architecture (AMBA)

specification defines an on chip communications

standard for designing high-performance embedded

microcontrollers. This paper focuses on how to build

an AMBA Advanced High performance Bus (AHB)

based memory controller that can work efficiently in

multi- master and multi- slave communication

model.

Ch. Vijayalakshmi, Mr B. Raghavaiah,

“Implementation of AMBA AHB

Compliant Memory Controller with

Peripherals”, ICITEC, 2012.

The main aim of the project is to increase the speed

to access the peripherals and which we have the built

storage units for peripherals like memories and

FIFO’s. Memory controller (MC) is designed and

built to reduce the memory access time. The

memory controller is the part of the system that,

well, controls the memory. The memory controller

is normally integrated into the system chipset. This

paper shows how to build an Advanced

Microcontroller Bus Architecture (AMBA)

compliant MC as an Advanced High-performance

Bus (AHB) slave with peripherals. The MC is

designed for system memory control with the main

memory consisting of SRAM and ROM.

KareemullahShaik, Mohammad Mohiddin,

Md. Zabirullah, “A Reduced Latency

Architecture for Obtaining High System

Performance”, IJRTE, 2012.

Microprocessor performance has improved rapidly

these years. In contrast, memory latencies and

bandwidths have improved little. The result is that

the memory access time has been a bottleneck which

limits the system performance. As the speed of

fetching data from memories is not able to match up

with speed of processors. So there is the need for a

fast memory controller. The responsibility of the

controller is to match the speeds of the processor on

one side and memory on the other so that the

communication can take place seamlessly. Here we

have built a memory controller which is specifically

targeted for SDRAM. Certain features were

included in the design which could increase the

overall efficiency of the controller, such as,

searching the internal memory of the controller for

the requested data for the most recently used data,

instead of going to the Memory to fetch it. The

memory controller is designed which compatible

with Advanced High-performance Bus (AHB)

which is a new generation of AMBA bus. The AHB

is for high-performance, high clock frequency

system modules. The AHB acts as the high-

JISEAT

ISSN: 2454-9606

Journals for International Shodh in Engineering and Technology

Website: http://jiseat.com (Volume 02, Issue 01, January 2017) performance system backbone bus. AHB supports

the efficient connection of processors, on-chip

memories and off-chip external memory interfaces

with low-power peripherals.

Hu Yueli; Yang Ben, “Building an AMBA

AHB Compliant Memory Controller”,

IEEE, 2011.

Microprocessor performance has improved rapidly

these years. In contrast, memory latencies and

bandwidths have improved little. The result is that

the memory access time has been a bottleneck which

limits the system performance. Memory controller

(MC) is designed and built to attacking this problem.

The memory controller is the part of the system that,

well, controls the memory. The memory controller

is normally integrated into the system chipset. This

paper shows how to build an Advanced Micro

controller Bus Architecture (AMBA) compliant MC

as an Advanced High-performance Bus (AHB)

slave. The MC is designed for system memory

control with the main memory consisting of SRAM

and ROM. Additionally, the problems met in the

design process are discussed and the solutions are

given in the paper.

Varsha vishwarkama, Abhishek choubey,

Arvind Sahu, “Implementation of AMBA

AHB protocol for high capacity memory

management using VHDL”, IJCSE,

2011.

Microprocessor performance has improved rapidly

these years. In contrast memory latencies and

bandwidths have improved little. The result is that

the memory access time is the bottleneck which

limits the system performance. In case of larger

system design which requires more number of I/O

ports and more memory capacity the system

designer may interface external I/O ports and

memory with the system. In this paper we are using

advanced microcontroller bus architecture with its

advanced high performance bus. AMBA AHB

provides parallel communications with multi master

bus management, high clock frequency, high

performance systems for data transfer operation

from the memory interfaced with the master or slave

peripheral devices. AMBA AHB supports on chip

communications standard for designing high-

performance embedded microcontrollers.

Zhao, B., “High speed DDR memory

interface design”, IEEE, 2009.

Summary form only given. As the bandwidth

requirement increases, Double Data Rate (DDR)

interface is becoming very commonly used in many

types of memories, such as, DDR I/II/III DRAM,

RLDRAM I/II, QDR I/II/II+ SRAM etc. The major

feature of DDR interface compared to a single data

rate (SDR) one is to use both rising and falling edges

of a clock to transfer data which allow it to provide

two times the throughput at the same clock

frequency. The high speed (up to 1.6 GHz for DDR

III) nature and complex timing issues take the most

attention for designers of ASIC chips with DDR

memory controllers. Furthermore, the mixed signal

aspect of the architecture requires careful designing

or selection of I/O cells to mitigate power switching

noises and manage signal integrities for the interface

channel of the whole system: ASIC chip die,

package, board traces and memory module /

components. Multiple ways could be used in

designing ASIC's with DDR memory interfaces.

This tutorial will try to provide attendees some

basics on the following topics: (1) Overview and

Comparison of various DDR memories interfaces;

(2) DDR Controller clocking scheme and strobe

delay circuits; (3) Data Transmit and data capture

logic implementation; (4) I/O driver impedance and

receiver ODT control and calibration circuits; (5)

DDR interface timing budget analysis and Chip

timing constraints.

McGee, S.W.; Klenke, R.H.; Aylor, J.H.;

Schwab, A.J., “Design of a processor bus

interface ASIC for the stream memory

controller”, IEEE, 1994.

The Stream Memory Controller (SMC) is an

experimental memory interface which allows

hardware-assisted memory access reordering for

vector computations in order to maximize the

efficiency of the system memory bus. This paper

describes the design and test strategies for the SMC

Processor Bus Interface (PBI) and FIFO logic ASIC.

This IC is designed as part of a daughter card

attachment to a 40 MHz Intel i860 system. The

entire integrated circuit design was completed in a

top-down design environment using VHDL for

synthesis and a target process of 0.75 μm. The

design includes SRAM elements, combinatorial

logic, and state machine components. This ASIC is

the first in a series of ICs intended as a proof-of-

concept of the SMC based system.

VIII. CONCLUSION

Carrying out literature review is very significant in

any research project as it clearly establishes the need

of the work and the background development. It

generates related queries regarding improvements in

the study already done and allows unsolved

problems to emerge and thus clearly define all

boundaries regarding the development of the

JISEAT

ISSN: 2454-9606

Journals for International Shodh in Engineering and Technology

Website: http://jiseat.com (Volume 02, Issue 01, January 2017) research project. Plenty of literature has been

reviewed in connection with the implementation of

AMBA based Memory Controller and the

significantly related ones have been discussed in this

paper.

REFERENCES [1] Shilpa Rao and Arati S. Phadke, “Implementation of

AMBA compliant Memory Controller on a FPGA”,

IJETEE, 2013.

[2] Archana C. Sharma1, Prof.Zoonubiya Ali, “Construct

High-Speed SDRAM Memory Controller Using

Multiple FIFO's for AHB Memory Slave Interface”,

IJETAE, 2013.

[3] S. Lakshma Reddy, A .Krishna Kumari, “Architecture

of An AHB Compliant SDRAM Memory Controller”,

International Journal of Innovations in Engineering

and Technology, 2013.

[4] Arun G, Vijaykumar T, “Improving Memory Access

time by Building an AMBA AHB compliant Memory

Controller”, IJARCET, 2012.

[5] S.Ramakrishna, K.Venugopal, B.VijayBhasker,

R.Surya Prakash Rao, “Hdl Implementation of Amba-

Ahb Compatible Memory Controller”, IJCER, 2012.

[6] Jayapraveen.DandT.GeethaPriya, “Design of memory

controller based on AMBA AHB protocol”, Elixir

International Journal, 2012.

[7] Ch.Vijayalakshmi, Mr B.Raghavaiah,

“Implementation of AMBA AHB Compliant Memory

Controller with Peripherals”, ICITEC, 2012.

[8] KareemullahShaik, Mohammad Mohiddin, Md.

Zabirullah, “A Reduced Latency Architecture for

Obtaining High System Performance”, IJRTE, 2012.

[9] Hu Yueli; Yang Ben, “Building an AMBA AHB

Compliant Memory Controller”, IEEE, 2011.

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