96-1 Under-Graduate Projectaccess.ee.ntu.edu.tw/course/under_project_96/lecture/... · 2010. 7....

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

9696--11 UnderUnder--Graduate ProjectGraduate ProjectCoding StyleCoding Style

Speaker: 詹承洲Adviser: Prof. An-Yeu Wu

Date: 2007/11/19

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P. 2

OutlineOutlinePrinciples of RTL Coding StylesnLint


P. 3

Principles of RTL Coding StylesPrinciples of RTL Coding StylesReadabilityLocalityPortabilityReusabilityParameterized


P. 4

Naming ConventionsNaming ConventionsLowercase letters for signal namesUppercase letters for constantsCase-insensitive namingUse clk for clocks, rst for resetsSuffixes

_n for active-low_a for async_z for tri-state

Identical names for connected signals and portsDo not use HDL reserved words


P. 5

File HeaderFile HeaderShould be included for all source filesContents

Author informationRevision historyPurpose descriptionAvailable parametersReset scheme and clock domainCritical timing and asynchronous interfaceTest structures

A corporation-wide standard template


P. 6

Example: ALU.vExample: ALU.v


P. 7



P. 8

PortsPortsOrdering

One port per line with appropriate commentsOutputs first then inputsClocks, resets, enables, other controls, address bus then data bus

Instantiating MappingUsing named mapping instead of positionalmapping


P. 9



P. 10

PrePre--RTL Preparation ChecklistRTL Preparation ChecklistCommunicate design issues with your team

Naming conventions, revision control, directory trees and other design organizations.

Have a specification for your design?Take it for granted that everyone has a specification BEFORE they start coding.

Design partitionFollow the specification’s recommendations for partition.Break the design into major functional blocks.


P. 11

PrePre--RTL Preparation ChecklistRTL Preparation ChecklistWork from the outside: I/O interfaces

Make sure the function and timing of each interface is clear.

How are the buses defined?Try to use unidirectional buses wherever possible.

Are there any compatibility requirements?Get the tester’s specification and understand how the chip is supposed to behave.

What other IP are you using?Start with the interface to each IP block.


P. 12

RTL Coding StyleRTL Coding StyleCreate a block level drawing of your design before you begin coding.

Draw a block diagram of the functions and sub-functions of your design.

Always think of the poor guy who has to read your RTL code.

Correlate “top to bottom” in the RTL description with ”left to right” in the block diagram.Comments and headers.

Hierarchical design


P. 13

Comments and FormatsComments and FormatsAppropriate comments

Process (always block), function, …

Comment end statementsOne statement per lineCoding in a tabular mannerbeginend

Line length restrictionA fixed number between 72-78

Indentation2 or 4 spacesdo not use tab


P. 14

Coding PracticesCoding PracticesLittle-endian for multi-bit bus

[31:0] instead [0:31]Operand sizes should match

reg [32:0] a; a = 33’h1_ffff_ffff;Use parentheses () in complex statementsDo not assign signals don’t-care values

Avoid don’t-care propagationReset all storage elements

Avoid don’t-care propagation


P. 15

Coding PracticesCoding PracticesUse high level constructs (case, if, always@) as much as possible.

DV takes Boolean expressions and gate level instantiations and replaces them with a sum-of-products “pla”-like internal description that is fed to the gate level mapping optimization.

Don’t instantiate gates unless you have to; make the code technology independent.Use for-loops only for bit-wise operations that can only be described one bit at a time.


P. 16

Combinational vs. Sequential BlocksCombinational vs. Sequential Blocks

Use separate always@ processes for sequential logic and combinational logic.

There is a sequential optimization process in DV.Combinational block

Use blocking (=) assignmentsMinimize signals required in sensitivity listAssignment should be applied in topological order

Sequential blockUse non-blocking (


P. 17

Function, Conditional StatementsFunction, Conditional StatementsUse function to model combinational logic when possible, instead of repeating the same sections of code.Know whether you have prioritized or parallel condition.

Prioritized: if-else, parallel: case

Completely specify all branches of all conditional statements.

If you completely specify the case statement (or use default), DV will recognize the case is fully specified and parallel.


P. 18

Coding for FSMCoding for FSMPartition FSM and non-FSM logicPrefer Moore (PO is PI-independent) to Mealy (PO is PI-dependent)Prefer Moore with state-outputs as POs3-always paradigm

One for sequential logicOne for next-state logicOne for PO logic (if required)

Use parameters to define the state namesAssign a default (reset) state


P. 19

PortabilityPortabilityDo not use hard-coded numbersAvoid embedded synthesis scriptsUse technology-independent librariesAvoid instantiating gates


P. 20

Clocks and ResetsClocks and ResetsSimple clocking is easier to understand, analyze, and maintain

The preferred clocking structure is a single global clock and positive edge-triggered flops.

Avoid using both edges of the clockDuty-cycle sensitiveDifficult DFT process

Don’t buffer clock and reset networksShould be handled during physical synthesis later

Avoid gated clocksClock gating circuits tend to be technology specific and timing dependent.


P. 21

Clocks and ResetsClocks and ResetsAvoid internally generated clocks and resets

Limited testability

Q’

QD

Q’

QD

clock


P. 22

Clocks and ResetsClocks and ResetsGated clock / internally generated clock design

If your design requires a gated clock, model it using synchronous load registers.

Q’QD

Q’QD

Q’QD

submodule1

submodule2

submodule3

clk1

clk2

clk3

TOPClock Generationclock


P. 23

Low PowerLow PowerClock gating

50%~70% power consumed in clock network reportedGating the clock to an entire blockGating the clock to a register

always @(posedge clk)if (en)

q


P. 24

SynchronicitySynchronicityInfer technology-independent registers

(positive) edge-triggered registers

Avoid latches intentionallyExcept for small memory and FIFOFor low-power

Avoid latches unintentionallyAvoid incomplete assignment in case statementUse default assignmentsAvoid incomplete if-then-else chain

Avoid combinational feedback loopsSTA and ATPG problem


P. 25

Coding for SynthesisCoding for SynthesisNo # delay statementsAvoid full_case and parallel_case

Evil twinPre-synthesis and post-synthesis simulation mismatch

Avoid glue logic at the top-levelAvoid expression in port connections


P. 26

PartitioningPartitioningRegister all outputs

Make output drive strengths and input delay predictableEase time budgeting and constraints

R1clk

A B R2clk

C

R1clk

ABC R2clk

R1clk

R2clk

ABC

Bad

Better

Best


P. 27

PartitioningPartitioningKeep related logic together

Improve synthesis qualityPartition logic with different design goalsAvoid asynchronous logic

Technology dependentMore difficult to ensure correct functionality and timingAs small as possible and isolation

Keep sharable resources in the same block


P. 28

PartitioningPartitioningAvoid timing exception

Point-to-point, false path, multi-cycle path

Keep sharable resources in the same block

muxmux

mux

AB

CD

AB

CD

control control


P. 29

nLintnLintnLint is a design rule checker that can help hardware designers to create syntax and semantics correct HDL code.nLint reads in HDL source code, analyzes it, and outputs warnings and errors.

Including position and message.nLint checks against approximately 200 rules, which are RMM compliant.

Reusable Methodology Manual


P. 30

Example: bad_conditional.vExample: bad_conditional.v

Incomplete conditional assignment

Incomplete sensitivity list

Error!!need “ ; ”

1

2

3


P. 31

Use commandUse commandnLint bad_conditional.v

1

23

1

2


P. 32

No Error & WarningNo Error & Warning


P. 33

GUIGUInLint –gui &


P. 34

Import DesignImport Design


P. 35

Edit FileEdit File


P. 36

File OrganizerFile Organizer


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Rule OrganizerRule Organizer


P. 38

Lint Lint --> Run> Run


P. 39

Fix errorFix error


P. 40

Fix Warning 1Fix Warning 1


P. 41

Fix Warning 2Fix Warning 2


P. 42

Search RuleSearch RuleRight clock -> Search Rule


P. 43

Show Source On Show Source On nTracenTraceTools -> Preferences


P. 44

Show Source On Show Source On nTracenTrace


P. 45

No Error & WarningNo Error & Warning

96-1 Under-Graduate Project� Coding StyleOutlinePrinciples of RTL Coding StylesNaming ConventionsFile HeaderExample: ALU.vExample: ALU.vPortsExample: ALU.vPre-RTL Preparation ChecklistPre-RTL Preparation ChecklistRTL Coding StyleComments and FormatsCoding PracticesCoding PracticesCombinational vs. Sequential BlocksFunction, Conditional StatementsCoding for FSMPortabilityClocks and ResetsClocks and ResetsClocks and ResetsLow PowerSynchronicityCoding for SynthesisPartitioningPartitioningPartitioningnLintExample: bad_conditional.vUse commandNo Error & WarningGUIImport DesignEdit FileFile OrganizerRule OrganizerLint -> RunFix errorFix Warning 1Fix Warning 2Search RuleShow Source On nTraceShow Source On nTraceNo Error & Warning

96-1 Under-Graduate Projectaccess.ee.ntu.edu.tw/course/under_project_96/lecture/... · 2010. 7....

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Transcript of 96-1 Under-Graduate Projectaccess.ee.ntu.edu.tw/course/under_project_96/lecture/... · 2010. 7....