94747528-VHDL (1)

Tip cn lp trnh cho FPGA t Spartan -3

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M UTrong nhng nm gn y, k thut in t lin tc c nhng tin b vt bc, c bit l trong nhng k thut vi in t. Khi kch thc v phc tp ca cc h thng s ngy cng gia tng, rt nhiu cng c thit k c tr gip bi my tnh c a vo qu trnh thit k phn cng. H tr mnh m cho phng php thit k ny l nhng ngn ng m t phn cng HDL. Ni n HDL tc l chng ta cp n cng ngh thit k ASIC hay cn gi l IC chuyn dng. nc ta, do nhu cu v cng ngh ASIC cn cha cao trong khi vic mua sn cc DSP a nng khng phi l iu kh khn. Tnh hnh s hon ton thay i trong tng lai khi nhu cu v bo mt, c lp v t ch cng ngh in t - vin thng phc v cng cuc cng nghip ho v hin i ho t nc tng ln nhanh chng. Vic ng dng rng ri cng ngh ASIC trong tng lai gn s l mt iu c th d on trc. Do vy, vic tm hiu v cng ngh ASIC c th lm ch cc ng dng trong cng nghip l mt vic lm hon ton cn thit. Hn th na, nhng hiu bit su sc v cc c tnh k thut trong cng ngh ASIC khng nhng ch c ngha ring i vi cc lnh vc in t - Vin thng, Cng ngh thng tin ni chung m cn c ngha c bit quan trng trong lnh vc an ninh, quc phng. Cng ngh FPGA (Field-Programmable Gate Array) xut hin nh mt gii php c bn cho vn tranh th thi gian v chi ph ban u thp. N cho php ch to ngay v gi thnh sn phm thp, to nn sc cnh tranh ln trn th trng. FPGA l mt thit b cu trc logic c th c ngi s dng lp trnh trc tip m khng phi s dng bt k mt cng c ch to mch tch hp no. FPGA c cng ty Xilinx gii thiu u tin vo nm 1985. Hin nay FPGA c nhiu cng ty pht trin l AcTel, Altera, Plus Logic, AMD, Vit Nam, trong mt s nm gn y, vic nghin cu v FPGA t c nhng thnh tu nht nh c bit trong cc lnh vc nh x l tn hiu Raa, cc


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lnh vc bo mt in thoai.... Trn mt s din n, ngi ta gii thiu rt nhiu v FPGA, v cng ngh lp trnh Ram tnh, cu tr nghch. Vi nhng ngi b ra khong thi gian khng nh nghin cu v lnh vc ny th c th nhng thng tin hon ton hnh dung ra vn , xong nhng ngi ang c nh tm hiu th qu thc vi nhng thng tin hiu ra c th cng li phi mt mt khong thi gian kh di. Cun sch Tip cn lp trnh cho FPGA t Spartan -3 vi mc ch cung cp nhng thng tin cn thit nht v cng ngh FPGA v c bit cung cp cho cc i tng ang c nhu cu tm hiu v cng ngh ny c kh nng tip cn mt cch nhanh chng vi cch thc lp trnh cho mt FPGA c th. Cun sch bao gm 5 chng: Chng I: Gii thiu v cng ngh ASIC Chng II: Gii thiu mt s cng ngh mi lin quan n thit k ASIC hin nay Cng ngh FPGA . Chng III: Gii thiu bo mch Spartan-3 starter kid board v mi trng lp trnh ISE 7.1 Chng IV: S lc v ngn ng VHDL Chng V: Cc bi ton thit k v giao tip Trong ngi c c th c lt qua cc chng I v II tm kim mt vi thng tin mong mun. Chng III c bit phi quan tm v y l mt FPGA c th. Chng IV gii thiu s lc v ngn ng VHDL, thc ra v ngn ng VHDL c rt nhiu sch cp ti. Tuy vy, chng ta ch cn nm lng thng tin chng ny sau c k tng bi ton chng V s gip chng ta c iu kin hiu r hn v ngn ng. Chng V s l cc bi ton t d n kh, vi 6 bi tp chng ta hon ton lm ch c bo mch, v v vy, vi cc bi ton bt k ch cn cn c vo thut ton l chng ta hon ton c th trin khai thc hin c. Do trnh cn hn ch v vy khng trnh khi nhng khim khuyt rt mong nhn c cc kin ng gp t ngi c. Cun sch ny c s dng kh nhiu chi tit t lun vn cao hc ca anh L Hi Triu HBK H Ni.


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CHNG I: CNG NGH ASIC1.1. Cc hng tip cn thit k ASIC 1.1.1. Cc cng ngh lp trnh thit k ASIC Tm tt cc cng ngh lp trnh cho ASIC c trnh by trong bng di y. Bng1.1. Cc c tnh cng ngh lp trnh thit k ASIC Cng ngh lp trnh Tnh bay hi C th lp trnh Din tch ca ASIC in tr (ohm) in dung (pF) Cc phn t RAM tnh C Trong mch Lp trnh cu ch nghch PLICE (PLICE Anti-fuse) Lp trnh cu ch nghch ViaLink (ViaLink Anti-fuse) EPROM Khng Ngoi mch EEPROM Khng Trong mch 1.1.2. Thit k logic ASIC u vo (Logic Design Entry) Mc ch ca thit k u vo l m t mt h thng vi in t da trn cc cng c ca h t ng thit k in t EDA (Electronic-Design Automation). Cc 2xEPROM 2 - 4K 10 - 20 Khng Khng Khng Khng Anti-fuse nh S tranzitor ln Anti-fuse nh S tranzitor ln Nh 2 - 4K 10 - 20 50 - 80K 1-3 300 - 500K 3-5 Ln 1 - 2K 10 - 20


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h thng in t c xy dng da trn cc thnh phn tnh, nh l cc IC TLL. Thit k u vo i vi cc h thng ny chnh l cng vic v cc mch v tng hp dng gin . Gin th hin cc thnh phn c kt ni vi nhau nh th no, chnh l lin kt ca mt ASIC. Phn ny ca qu trnh thit k u vo c gi l u vo gin , hoc l bt gin . Mt gin mch m t mt ASIC ging nh l mt bn thit k cho mt cng trnh xy dng. Gin mch l mt bn v, l mt khun dng n gin chng ta c th hiu v s dng, nhng cc my tnh cn lm vic vi cc phin bn ASCII hoc cc tp nh phn m chng ta gi l netlist (i dy). u ra ca cng c thit k gin chnh l mt file netlist m c cha m t ca tt c cc thnh phn trong mt bn thit k v cc ng kt ni ca chng. Khng phi tt c cc thng tin thit k c th chuyn thnh gin mch hoc netlist, v khng phi tt c cc chc nng ca mt ASIC u c m t qua thng tin kt ni. V d, gi s chng ta s dng mt ASIC lp trnh c cho mt vi chc nng logic ngu nhin. Mt phn ca ASIC c th c thit k bng cch s dng ngn ng lp trnh dng vn bn. Trong trng hp ny thit k u vo cng gm c c vit m ngun. Vy iu g nu mt ASIC trong h thng ca chng ta c cha mt PROM (Programmable Memory)? Phi chng vi m lnh l mt phn ca thit k u vo? Vic iu hnh h thng ca chng ta chc chn l ph thuc vo chng trnh chun ca PROM. V vy c l m lnh PROM phi l mt phn ca thit k u vo. Mt khc khng ai coi m lnh h iu hnh c np vo RAM trn mt ASIC l mt phn ca thit k u vo. R rng l c nhiu dng thit k u vo khc nhau. Trong mi mt trng hp n rt quan trng bo m l bn hon thnh ch nh cho h thng - khng ch l xy dng cu trc chnh xc m cn bt k ai cng hiu c l h thng lm vic nh th no. Thit k u vo l mt trong nhng phn quan trng nht ca cng ngh ASIC. Cho n hin hay th hu ht cc thit k u vo cho ASIC vn s dng phng php gin u vo. Do ASIC ngy cng tr nn phc tp hn, cc phng php thit k u vo khc ngy cng tr nn ph bin. Cc phng php


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thit k u vo u c th s dng phng php ho, chng hn l mt gin , hoc cc tp dng text di dng ngn ng lp trnh. Vic s dng ngn ng m t phn cng HDL (Hardware Description Language) cho mc ch thit k u vo cho php chng ta to ra cc netlist trc tip bng cch tng hp logic. Chng ta s cp n cc phng php thit k u vo mc thp cng vi cc u im cng nh nhc im ca chng trong mc 2.3. Thit k u vo bao gm cc thnh phn thit k sau: Thit k th vin ASIC. Thit k th vin cc vi mch ASIC lp trnh c (Programmable ASIC). Thit k phn t logic ASIC lp trnh c. Thit k phn t vo/ra ASIC lp trnh c. Thit k phn t kt ni ASIC lp trnh c. Thit k logic mc thp u vo (low-level design entry) s dng VHDL: B Quc Phng M (The U.S. Department of Defence - DoD) h tr vic pht trin ngn ng VHDL (VHSIC Hardware Description Language) nh mt phn ca chng trnh quc gia VHSIC (Very HighSpeed IC) vo u thp k 80. Tng hp logic (logic synthesis): Tng hp logic cung cp lin kt gia mt tp HDL (VHDL hoc Verilog) v mt netlist tng t nh cch m mt b bin dch C cung cp lin kt gia m lnh chng trnh C v ngn ng my. M phng (simulation): Cc k s quen vi cc h thng mu dng kim tra sn phm thit k ca h, thng thng s dng mt th mch mu, cho php cm cc IC v cc dy dn ln. th mch mu c th thc hin c khi c cho php xy dng h thng t mt vi IC TTL. Tuy nhin iu ny l phi thc t i vi thit k ASIC. Do vy hu ht cc k s thit k ASIC u s dng phng php m phng tng ng thay cho m hnh th mch.

Phn mm thit k ASIC lp trnh c:


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Th nghim mc logic (test): Cc ASIC c th nghim theo hai giai on trong qu trnh sn xut bng cch s dng cc phng php th nghim sn xut.

1.1.3. Thit k vt l (Physical Design) Hnh 1.1 biu din mt phn ca s thit k, l cc bc thit k vt l i vi mt ASIC.

Hnh 1.1. Mt phn ca thit k ASIC gm c phn chia h thng, ln s mt bng, sp xp cc phn t v cc bc nh tuyn ng kt ni. u tin chng ta p dng vic phn chia h thng chia mt h thng vi in t thnh cc ASIC. Trong phn ln s mt bng chng ta s nh gi kch thc v t cc v tr lin quan ca cc khi trong ASIC (i khi cn c gi l xp chip - chip planning). Cng thi im ny chng ta nh v khong trng cho ng xung nhp v ngun v quyt nh v tr ca cng I/O. Vic sp xp nh ngha v tr ca cc phn t logic cng vi s linh hot ca cc khi v khong trng dnh cho vic ni cc phn t logic. Vic sp xp i vi thit k ma trn


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cng (gate-array) hoc phn t tiu chun (standard-cell) b tr mi mt phn t logic vo v tr trong cng mt hng. Vic ln s mt bng v sp xp phn t i khi c th s dng cng c CAD. Vic nh tuyn thc hin ng kt ni gia cc phn t logic. Vic nh tuyn l mt vn rt kh v thng c phn chia thnh cc bc ring bit c gi l nh tuyn ton cc v nh tuyn cc b. nh tuyn ton cc xc nh cc kt ni gia cc phn t logic t ch v cc khi s t ch u. Cn nh tuyn cc b l mc nh tuyn c th v chi tit n tng phn t. 1.1.4. Cc cng c CAD (CAD Tools) pht trin mt cng c CAD cn thit phi chuyn i mi mt bc trong thit k vt l thnh cc vn c mc ch v nh hng r rng. Mc ch l nhng g chng ta cn phi thc hin, cn nh hng l cch thc hin mc ch. V d trong cc bc thit k vt l ASIC th cc mc ch v nh hng nh sau: Phn chia h thng (System partitioning): Mc ch: Phn chia mt h thng thnh mt s cc ASIC. nh hng: Ti thiu ho s lng cc kt ni ngoi gia cc ASIC. Gi cho mi ASIC nh hn kch thc cc i. Ln s mt bng (Floorplanning): Mc ch: Tnh ton kch thc ca tt c cc khi v sp xp v tr ca chng. nh hng: Bo m s lin kt cao gia cc khi v mt t nhin cng gn cng tt. Sp xp cc phn t (Placement): Mc ch: Sp xp vic kt ni gia cc vng v v tr ca tt c cc phn t logic cng vi cc khi linh hot. nh hng: Ti thiu ho cc vng ASIC v mt kt ni. Mc ch: Quyt nh v tr ca tt c cc kt ni. nh hng: Ti thiu ho ton b vng kt ni c s dng. nh tuyn ton cc (Global routing):


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nh tuyn chi tit (Detailed routing): Mc ch: Hon thnh nh tuyn tt c cc kt ni trn chip. nh hng: Ti thiu ho tng s di kt ni c s dng.

1.2. Thit k ASIC u vo (design entry) 1.2.1. Thit k th vin ASIC Th vin phn t l mt phn chnh trong thit k ASIC. i vi mt ASIC lp trnh c th mt cng ty chuyn v PLD, FPGA cung cp cho chng ta mt th vin cc phn t lgic di hnh thc mt b kit thit k, thng l chng ta khng c mt s la chn no v gi ca n ni chung khong vi nghn la. i vi MGAs v CBICs chng ta c ba la chn : nh cung cp ASIC (cng ty s xy dng ASIC cho chng ta) s cung cp mt th vin phn t, hoc chng ta c th mua mt th vin phn t t mt nh cung cp th vin th ba, hoc chng ta c th t xy dng th vin phn t ca chnh mnh. S la chn u tin, l s dng mt th vin ASIC ca nh cung cp, yu cu chng ta phi s dng mt tp cc cng c thit k c cung cp bi nh cung cp ASIC a vo v m phng thit k ca chng ta. Tc l chng ta phi mua cc cng c v th vin phn t. Mt vi nh cung cp ASIC (c bit cho MGAs) cung cp cc cng c c pht trin theo yu cu. Th vin ca nh cung cp ASIC thng thng l mt th vin o - cc phn t ch l cc khi trng rng, nhng n bao gm thng tin b tr s mch. Sau khi chng ta hon thnh vic b tr s mch, chng ta a ra netlist n nh cung cp ASIC h b sung vo cc phn t o trc khi bt u sn xut chip cho chng ta. Cc la chn th hai v ba yu cu chng ta thc hin mt quyt nh mua bn. Nu chng ta hon thnh vic thit k mt ASIC s dng th vin phn t m chng ta mua, th chng ta s hu vic ch to chip c s dng sn xut ASIC ca chnh mnh. Nhng th vin phn t nh vy thng t (c th ln n vi trm nghn la). Tuy nhin iu ny c ngha rng vic mua mt th vin t c th r v lu di nu chng ta sn xut nhiu hn l cc gii php khc.


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La chn th ba s pht trin mt th vin phn t theo yu cu. Nhiu cng ty my tnh v cng ty in t ln chn phng n ny. Hu ht th vin phn t thit k hin nay vn tip tc c pht trin theo hnh thc yu cu mc d thc t qu trnh pht trin th vin rt phc tp v t. Tuy nhin to ra mi phn t trong mt th vin phn t ASIC phi bao gm cc yu t sau: - S b tr vt l - M hnh hot ng - M hnh Verilog/VHDL - M hnh tnh ton thi gian chi tit - Chin lc th nghim, kim tra - S mch - Biu tng ca phn t - M hnh ti - M hnh nh tuyn 1.2.2. Cc vi mch ASIC lp trnh c C hai loi ASIC lp trnh c: Thit b logic lp trnh c - PLD (Programmable Logic Device) v Ma trn cng lp trnh c theo hng - FPGA (Field-Programmable Gate Array). Vic phn bit gia hai loi ASIC ny cha c chun ho. S khc nhau thc t ch l s k tha ca chng. PLDs bt u t nhng thit b nh dng th thay th mt mt phn ca h IC TTL, v chng c pht trin tng t nh ngi anh em FPGA ca chng, ch khc nhau v cng ngh ch to. Trong mc ny, chng ta s coi li c hai loi ASICs u l cc ASIC lp trnh c. Mt ASIC lp trnh c chnh mt chip m chng ta, nh mt ngi thit k h thng, c th t lp trnh. Chng ta tin hnh thit k u vo v m phng. Tip theo, mt phn mm c bit to ra mt chui cc bit m t thm m rng cc kt ni theo yu cu thc hin thit k ca chng ta - gi l tp cu hnh. Sau , chng ta kt ni my tnh ti chip v lp trnh cho chip tun theo tp cu hnh.


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Tuy nhin cng ngh lp trnh c th c hoc c th khng lu di. Do vy chng ta khng th xo b nhng lp trnh trong cc ASIC lp trnh c mt ln. V th, ngy nay ngi ta thng s dng cc loi PLD v FPGA c kh nng lp trnh li c. 1.2.3. Cc phn t logic ASIC lp trnh c Tt c cc ASIC (hoc PLD hoc FPGAs) u cha mt phn t lgic c bn. l ba kiu phn t lgic c bn khc nhau: (1) B dn knh c s; (2) Bng s tht c s; (3) Phn t logic ma trn lp trnh c. Vic la chn gia cc phn t ph thuc vo cng ngh lp trnh. 1.2.4. Cc phn t vo/ra ASIC lp trnh c Tt c ASICs lp trnh c u cha mt vi kiu phn t Vo/Ra (I/O) no . Cc phn t Vo/Ra iu khin mc lgic tn hiu vo - ra ca chip, nhn v kim tra iu kin ca cc u vo t bn ngoi, cng nh bo v tnh in cho chip. Sau y l cc yu cu khc nhau ca cc loi phn t Vo/Ra: - Ngun u ra DC: iu khin tr khng ti ti u ra DC hoc tn s thp (thp hn 1 MHz). V d cc loi tr khng ti nh LED, r le, m-t loi nh - Ngun u ra AC: iu khin dung khng ti tc cao (ln hn 1 MHz). V d dung khng ti cc chip logic khc, bus d liu hoc bus a ch, cp ruy bng. - Ngun u vo DC: v d cc ngun nh chuyn mch, cm bin, hoc cc chip logic khc. - Ngun u vo AC: v d cc ngun nh tn hiu logic tc cao (ln hn 1 MHz) t cc chip khc. - Ngun to xung nhp u vo: v d l ng h xung nhp h thng hoc cc tn hiu trn bus ng b. - Ngun cung cp u vo: chng ta cn cp ngun cho phn t Vo/Ra v cc phn t lgic bn trong chip, m in p khng b st hoc nhiu. Ngoi ra chng ta c th cng cn mt ngun cung cp ring bit lp trnh cho chip.


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Cc ty chn i vi phn t Vo/Ra l: s khc nhau v mc ca ngun, tnh tng thch vi TTL, cc u vo trc tip hoc phi c iu chnh, cc u ra trc tip hoc phi c iu chnh, phi hp tr khng, bo v qu in p, iu khin tc trn, v qut hn ch. 1.2.5. Cc phn t ASIC lin kt ni lp trnh c Tt c ASIC u cha cc phn t lin kt ni lp trnh c. Cu trc v s phc tp ca cc phn t lin kt ni phn ln c xc nh thng qua cng ngh lp trnh v kin trc ca cc phn t lgic c bn. Cht liu m chng ta dng xy dng cc phn t lin kt ni l hp kim nhm, loi hp kim c th chu c xp x 50 mW/1 n v din tch v dung khng l 0.2 pFcm-1. Cc loi ASIC lp trnh c i u tin c xy dng s dng cng ngh hai lp kim loi; cn cc ASIC hin nay s dng ba lp kim loi hoc nhiu hn. 1.2.6. Phn mm thit k ASIC lp trnh c C nm thnh phn cu thnh mt ASIC: (1) Cng ngh lp trnh, (2) Phn t lgic c bn, (3) Phn t Vo/Ra, (4) Phn t lin kt ni, v (5) Phn mm thit k cho php chng ta lp trnh ASIC. Phn mm thit k thng l b rng buc gn gi hn vi kin trc PLD v FPGA hn cc kiu ASICs khc. i vi bt k ASIC no th mt nh thit k cng cn phn mm thit k u vo, mt th vin phn t, v phn mm thit k vt l. Mi mt nh cung cp ASIC thng bn cc b kit thit k bao gm tt c phn mm v phn cng m mt ngi thit k cn n. Rt nhiu b kit thit k ny s dng phn mm thit k u vo ca mt cng ty khc. Thng th ngi thit k mua lun phn mm t nh cung cp ASIC. Phn mm ny c gi l phn mm OEM (Original Equipment Manufacturer). Tt c cc nh cung cp ASIC u c phn mm thit k vt l ca ring mnh - v cc phn mm thit k nh vy mi c th ph hp vi cc gii thut tng ng vi kin trc h. Gin u vo khng phi l phng php duy nht thit k u vo cho cc ASIC lp trnh c. Mt s nh thit k m t vic iu khin lgic v trng thi my di dng cc phng trnh lgic v gin trng thi. Mt gii php khc na


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cho thit k ASIC l s dng mt trong s cc ngn ng m t phn cng (HDL) da theo mt s tiu chun. C hai dng ngn ng thng dng. Th nht l cc phn mm c pht trin t vic lp trnh cho cc ASIC loi PLD. l ABEL, CUPL, v PALASM, l cc ngn ng n gin v d hc. Cc ngn ng ny rt mng trong vic m t cc my trng thi v t hp lgic. Th hai l cc ngn ng HDL bao gm VHDL v Verilog, l cc ngn ng bc cao hn v s dng phc tp hn nhng chng c kh nng m t hon chnh cc ASICs v c mt h thng. Sau khi hon thnh thit k u vo v to ra mt netlist, bc tip theo l vic m phng. C hai kiu m phng thng c s dng cho thit k ASIC. Kiu m phng u tin l m phng lgic theo hot ng, chc nng, v m phng thi gian. Cng c ny c th pht hin bt k li thit k no. Ngi thit k cung cp cc tn hiu u vo m phng v kim tra u ra theo yu cu. Kiu m phng th hai, l kiu thng s dng nht trong thit k ASIC, l mt cng c phn tch - tnh ton thi gian. Cng c phn tch - tnh ton thi gian l mt thit b m phng tnh v b qua vic cung cp cc tn hiu u vo. Thay vo cng c phn tch - tnh ton thi gian kim tra cc ng gii hn m lm hn ch tc hot ng - cc ng tn hiu gy ra tr ln. 1.3. Thit k logic mc thp u vo (low-level design entry) 1.3.1. Gin u vo (Schematic Entry) Gin u vo l phng php ph bin nht ca thit k u vo i vi cc ASIC. Cc ngn ng HDL ang thay th cho cc gin u vo mc cng thng thng, nhng cc cng c ho mi da trn cc gin u vo ngay nay cng ang c s dng to ra mt s lng ln cc m ngun HDL. Cc gin mch c v trn cc sheet gin . Kch thc tiu chun ca cc sheet gin tun theo tiu chun ANSI A-E (ch yu dng M) v ISO A4A0 (ch yu dng chu u). Nh trn hnh 2.2 th hin 2 hnh ging ci ci mai v ci xng, l cc biu tng c cng nhn ca cc cng AND, NAND, OR v NOR.


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Hnh 1.2. IEEE khuyn ngh kch thc v cc k hiu cho cc cng logic. (a) Cng NAND; (b) Cng OR-c nht.

Hnh 1.3. Cc thut ng c dng trong cc gin mch Cc cng c v gin u vo cho thit k ASIC tng t nh thit k bo mch in PCB (Printed-Circuit Board). Trn mt PCB thng ch c vi trm thnh phn hoc phn t TTL hoc cc in tr, tranzitor hoc t in, cun cm... Nu chng ta coi mt cng logic trn mt ASIC tng ng vi mt thnh phn trn mt PCB, th mt ASIC c ln cha hng trm ngn thnh phn nh vy. Do vy v ton b cc phn t ca mt ASIC l iu khng tng. 1.3.1.1. Thit k theo th bc (Hierarchical Design) Vic thit k theo th bc s lm gim kch thc v phc tp ca mt gin u vo. Mt gin in t c th cha cc gin con. Cc gin con cng c th cha cc gin nh hn na. Vic la chn thit k theo th bc l c th v c tt c cc thnh phn ca mt ASIC trn mt gin cc ln khng c th bc dng thit k phng. i vi mt ASIC i mi c cha hng ngn hoc nhiu hn na cc cng logic


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bng cch s dng thit k phng hoc gin phng l iu khng th thc hin c. Do vy ngi ta phi phn cp thit k cho cc gin thit k u vo. 1.3.1.2. Th vin phn t (The Cell Library) Cc thnh phn trong mt gin ASIC thng c chn t mt th vin cc phn t logic. Cc phn t ca th vin cho tt c cc loi ASIC i khi cn c bit n nh l cc khi modul (module). Hu ht cc cng ty trong lnh vc ASIC u cung cp mt th vin cc phn t vi cc cng c bn c s dng trong gin u vo. C hai vn cn t ra i vi cc th vin gin ASIC l khng c qui c v t tn v khng c tiu chun dnh ring cho hot ng ca phn t. Trong th vin cc phn t th cc cng logic l cc phn t c bn, chng hn nh cng NAND. Trong mt thit k phn cp ASIC th mt phn t c th l mt cng NAND, mt mch flip-flop, mt b nhn hoc thm ch c th l mt b vi x l. Chnh v vy m chng ta thy rng cc thut ng v phn t u c chp nhn mt cch chung chung trong mt gin u vo nhiu khi gy ra s lm ln. Thut ng phn t c dng biu din c cc phn t c bn v c cc gin con. Mc d chng c khc nhau trn thc t nh chng vn c mi lin quan gn gi, v c chp nhn dng chung. 1.3.1.3. Cc tn gi (Names) Mi mt phn t, c th l phn t c bn hoc khng phi, khi c t vo mt gin thit k ASIC u phi c tn. Mi phn t khi s dng u dng theo mt tn duy nht v khng c trng lp trong gin u vo mc d chng c th l bn sao chp ca nhau t cng mt th vin. 1.3.1.4. Cc biu tng v k hiu trn gin (Schematic Icons and Symbols) Hu ht cc chng trnh v gin u vo u cho php ngi thit k s dng cc biu tng c bit hoc biu tng t to. Ngoi ra cng c v gin u vo cng thng t ng to ra biu tng cho cc gin con dng trong cc gin mc cao hn. y c gi l cc biu tng gc hoc k hiu gc.


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Cc ng kt ni ngoi ca gin con c t ng gn thm biu tng, thng thng l mt hnh ch nht. V d v cc biu tng v k hiu i vi mt phn t c tn l DLAT c cho trong hnh 2.4.

Hnh 1.4. Mt phn t v cc gin con ca n. (a) Mt th vin gin cha cc biu tng dnh cho cc phn t c bn; (b) Mt gin con cho mt phn t DLAT, cha tn ca cc phn t c bn; (c) Biu tng cho phn t DLAT. 1.3.1.5. Cc ng ni (Nets) Cc gin trn hnh 2.4 c cha c cc ng ni cc b v ng ni bn ngoi. Nh trn hnh 2.4.b ng ni cc b l n1, ni gia mt phn t AND c tn l and1 v mt phn t OR c tn l or1. Cn ng ni ngoi l ng ni gia mt phn t vi mt ng ni khc, trn hnh 2.4.b l n3. thun tin cho vic t tn cc ng kt ni trong mt gin phn cp ngi ta s dng tn tin t ca phn t t tn cho ng ni. Cc k t c bit (nh ; / $ # ...) khng c dng t tn cho ng ni. Tuy nhin vic t tn thng l c thc hin t ng thng qua cng c v gin u vo. Trong cc ngn ng HDL (VHDL v Verilog) c cch t tn cho ng ni rt chnh xc v cht ch c tiu chun trong cc kin trc phn cp. 1.3.1.6. Cc u ni (Connections) Cc phn t c cc u cui (terminal) l cc u vo hoc u ra ca phn t . Cc u cui (terminal) cn c bit n di cc tn nh cc chn (pin), cc u ni (connection), hoc l cc u tn hiu (signal). Thut ng chn (pin) c s dng rt rng ri, tuy nhin y chng ta ch yu s dng thut ng u cui trnh nhm vi thut ng chn (pin) trong mt ASIC ng gi. Ngoi ra thut


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ng chn (pin) cn thng c dng trong gin u vo v chng trnh nh tuyn ng ni ch yu cho cc thit k PCB.

Hnh 1.5. V d v vic s dng bus n gin ho mt gin . (a) Cc u ni A, B, C; (b) Cc u ni A, B, C v DQ0 - DQ7... 1.3.2. Cc ngn ng thit k mc thp (Low-level Design Languages) Trong trng hp thit k ASIC th ngn ng ny rt quan trng. C hai vn cn cp n l: vic thay i mt gin rt kh v vn cha c tiu chun i vi cc k hiu v thng tin gin dng lu tr trong mt netlist. iu ny c ngha l chng ta cn phi chuyn i t thit k mc thp m bn s dng thit k PLD thnh mt hoc nhiu thit k ASIC tng ng. Thng thng th chng ta nhp nhiu PLD thnh mt PLD n ln hn chnh l ASIC. chnh l ngn ng thit k mc thp chuyn i v c hiu t cc PLD sang khun dng m bn c th s dng c trong cc h thng thit k ASIC khc. Mt s ngn ng nh sau: Ngn ng ABEL: ABEL l mt ngn ng lp trnh PLD t cc d liu I/O (Data I/O). Ngn ng CUPL: CUPL l mt ngn ng thit k PLD t cc thit b logic (Logical Devices). nh dng EDIF: y l mt tiu chun dng trao i thng tin gia cc cng c EDA vi nhau l nh dng trao i ln nhau trong thit k in t - Electronic Design Interchange Format - EDIF. Phin bn hay c s dng nht l EDIF 2 0 0 do EIA (Electronic Industries Association - Hip hi cng nghip in t) pht hnh c


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tn l Tiu chun ANSI/EIA 548-1988 - cn c gi l EDIF 1988. Hin nay c phin bn 3.0.0 v 4.0.0. Hu ht cc cng ty trong lnh vc EDA u h tr chun EDIF. Cc cng ty chuyn v ASIC - FPGA l Altera v Actel u s dng EDIF nh l khun dng netlist ca h v Xilinx cng thng bo h cng cp n vic chuyn dn khun dng XNF ca h sang khun dng EDIF. 1.4. Tng hp logic (Logic Synthesis) Tng hp logic cung cp mt lin kt gia HDL v netlist tng t nh cch mt trnh bin dch C cung cp lin kt gia m ngun C v ngn ng my. Tuy nhin, vic so snh song song nh trn cung ch mang tnh tng i. C c pht trin s dng vi cc trnh bin dch, cn HDL th khng c pht trin s dng vi cc cng c tng hp logic. Verilog th c thit k nh mt ngn ng m phng cn VHDL th c thit k nh mt ngn ng m t v d liu. C Verilog v VHDL u c pht trin t u thp nin 80, trc khi n c gii thiu nh mt phn mm thng mi dng tng hp logic. Do cc ngn ng HDL hin nay c s dng vo mc ch khng phi nh ng ban u, nn hin trng ca n trong tng hp logic gn ging nh cc b bin dch ngn ng my tnh. Do vy tng hp logic buc ngi thit k phi s dng mt tp con ca c Verilog v VHDL. Hin nay, VHDL c s dng rng ri v ch yu Chu u, cn Verilog th c dng chnh M v Nht. Vic ny lm cho tng hp logic l mt vn rt kh. Hin trng ca cc phn mm tng hp ging nh vic mt ngi hc ngoi ng nhng nm nm sau mi s dng n. Khi ni n cng c tng hp logic s dng HDL th ngi ta thng ngh n lin quan n phn cng hn l vic tng hp logic s thc hin trn netlist. Theo nh gi ca cc chuyn gia ASIC hc th phi 5 nm na chng ta mi hon thin c qu trnh tng hp logic nh mong mun. Ngi thit k s dng thit k u vo dng text hoc ho to ra m hnh hot ng HDL khng bao gm bt k tham chiu no n cc phn t logic. Cc s trng thi, cc m t ng dn d liu ho, cc bng s tht, cc mu RAM/ROM, v cc gin mc cng (gate-level) c th s dng cng vi mt m


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t HDL. Mi khi hon thnh mt m hnh hot ng HDL, hai thnh phn yu cu phi x l l: mt b tng hp logic (bao gm phn mm v ti liu i km) v mt th vin phn t (bao gm cc phn t logic chng hn nh cng NAND, AND...) c gi l th vin ngun. Hu ht cc cng ty phn mm tng hp ch cung cp phn mm. Cn hu ht cc nh cung cp ASIC th ch cung cp cc th vin phn t. M hnh hot ng c m phng kim tra vic thit k theo tham s k thut cn sau b tng hp logic s c s dng to ra mt netlist, mt m hnh cu trc ch cha tham chiu n cc phn t logic. Hin nay khng c khun dng tiu chun cho cc netlist m tng hp logic to ra, nhng ph bin nht hin nay ngi ta vn s dng khun dng EDIF. Mt vi cng c tng hp logic cng c th to ra cu trc HDL (nh Verilog v VHDL). Sau khi tng hp logic bn thit k c thc hin m phng li so snh vi vic m phng hot ng trc . Vic xp lp i vi bt k ASIC no u c th c to ra t m hnh cu trc sinh ra thng qua qu trnh tng hp logic. 1.4.1. V d v tng hp logic Trc ht chng ta hy tm hiu v mt v d ca tng hp logic. y cc phn t logic u s dng cng ngh VLSI 1.0 m m. ASIC u tin c thit k bng tay s dng cc gin u vo v mt s tay d liu. ASIC th hai s dng Verilog cho thit k u vo v mt b tng hp logic. Bng 2.2 so snh kt qu ca hai phng php trn. Vic tng hp ASIC theo phng php th hai cho kt qu l ASIC nh hn 16% v tc nhanh hn 13% so vi cch tng hp bng tay. Chng ta cng tm hiu ti sao li c vn trn. Hnh 2.6 biu din gin mt b so snh v dn knh c thit k bng tay. Cn bn phi ca hnh 2.6 l m ngun cng ca b so snh v dn knh c cng chc nng. Vic so snh hai kt qu cho trong bng 2.3 ch ra l do ca phng php th hai cho sn phm c kch thc nh hn, tc nhanh hn thm ch cn s dng nhiu phn t hn.


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Bng1.2. So snh thit k tng hp logic ASIC bng tay v tng hp logic s dng Verilog theo l thuyt Tr ng S cc phn t logic dn/ns (1) Thit k bng tay Thit k tng hp logic 41.6 36.3 tiu chun 1,359 1,493 S tranzitor tiu chun 16,545 11,946 Kch thc/ mils 2 (2) 21,877 18,322

Bng 1.3. So snh thit k tng hp logic ASIC bng tay v tng hp logic s dng Verilog trn b so snh v dn knh trong thc t Tr ng S cc phn t logic dn/ns (1) Thit k bng tay Thit k tng hp logic 4.3 2.9 tiu chun 12 15 // comp_mux.v module comp_mux(a, b, outp); input [2:0] a, b; output [2:0] outp; function [2:0] compare; input [2:0] ina, inb; begin if (ina 12V) VPP cung cp ti cc mng cc in t c nng lng nhy vo cng treo gate 1; (b) Cc in t cng gate 1 tng ln in p gi m to cho cc transistor kho cho mc in p hot ng bnh thng; (c) nh sng cc tm cung cp nng lng cc phn t cng gate 1 nhy v v tr c cho php transistor hot ng bnh thng.


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u im ca tranzitor EPROM l chng c th ti lp trnh m khng cn b nh bn ngoi. Tuy nhin khng ging nh SRAM, tranzitor EPROM khng th c lp trnh li ngay trn bo mch (in-circuit). Phng php dng EEPROM tng t nh cng ngh EPROM, ch khc l din tch ca tranzitor EEPROM chim din tch gp hai ln din tch chp so vi tranzitor EPROM v cn nhiu ngun in th hn cc loi khc. 2.1.2.4. Tm tt cc loi FPGA trn th trng Bng 6.1. Tm tt cc h FPGA trn th trng Cng ty Xilink Altera Actel Plessey Plus AMD QuickLogic Algotronix Concurent Crosspoint Kin trc tng qut Symmetrical Array Hierachical-PLD Row-based Sea-of-gates Hierachical-PLD Hierachical-PLD Symmetrical Array Sea-of-gates Sea-of-gates Row-based Kiu khi logic Look-up Table PLD Block Multiplexers-Based NAND-gate PLD Block PLD Block Multiplexer-Based Multiplexers & Based Gates Multiplexers & Based Gates Transistor Pairs & Multiplexers 2.1.2.5. Cc loi FPGA v gii thiu cng ngh lp trnh C nhiu loi FPGA ca cc cng ty khc nhau, tuy nhin chng c th c chia thnh 4 loi chnh nh sau (xem hnh 2.2): - Cu trc mng i xng (symmetrical array) - Cu trc hng (row-based) - Cu trc PLD phn cp (hierachical PLD) - Cu trc a cng (sea-of-gate) Anti-fuse Static RAM Cng ngh lp trnh Static RAM EPROM Anti-fuse Static RAM EPROM EPROM Anti-fuse Static RAM


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2.2. Gii thiu phng php thit k ASIP cho cc h thng nhng Mt thch thc m nhiu ngi tng cp n trong qu trnh thit k b x l nhn c nhng kt qu tt nht c th i vi phm vi ng dng in hnh cui cng cn t c ni chung l m t theo nhng chun nh gi. Vic thu c kt qu tt nht c th ln lt tr thnh mt s tho hipphc tp gia tnh tng qut ca nhng b x l v c trng vt l ca chng. Trong nhng nm gn y, cc b vi x l c tp lnh chuyn dng - ASIP (Application-Specific Intruction-Set Processor) c s pht trin c bit trong ngnh sn xut chip v ang c nghin cu. Trong mc ny, ch ch yu gii thiu mt kiu kin trc v phng php lun c dng thit k ASIPs trong phm vi cc b iu khin. 2.2.1. Gii thiu chung Nhiu h thng nhng b hn ch v rng buc i vi gi thnh sn phm. Gi biu hin theo hai c trng chnh : gi ca chng trnh ngun v gi ca b x l. Do vy vic dung ho gia gi thnh sn phm v cht lng cng nh ng dng ca sn phm rt d i vi cc nh thit k c th tm ra gii php tt nht cho b x l tng ng vi vic thc hin mt ng dng trung bnh v cng sut tiu th ca n. Do vy, phi chn gii php s dng b ng vi x l ASIC (coprocesor ASIC) hoc l ng dng cn phi nng cp thnh mt b x l c kh nng hot ng cao hn vi gi thnh ni chung cao hn. Nn cng nghip bn dn ni chung ch yu nhm vo cc b x l m c sn xut cho mt phm vi ng dng c bit nh cc chip DSP. Cc chip DSP thng thng l nhng b vi x l vi nhng c tnh v nhng kin trc c bit ch yu phc v cho vic x l tn hiu s. Tuy nhin, vic thit k chuyn bit v cc b x l khng gii quyt c tt c cc vn . Cn nhng ng dng ph hp vi cc c im ring ca mt b x l, th gi thnh ca b x l t hn do ch c sn xut theo n t hng. V mt thut ng ni chung, vic thit k ASIP chnh l vic to ra mt b vi x l mi, vi tp lnh v kin trc c ty bin cho ph hp vi mt s nhng ng dng chuyn bit.


33

Mc ch ca chng ta l c th ti u ha hiu qu chng trnh ngun v kh nng hot ng ca mt ng dng cho sao cho bo m cc yu cu sau: - Hiu qu h thng (gi thnh, kch thc chng trnh ngun, kh nng thc hin, v in nng tiu th) bo m chp nhn c cho cc h thng nhng. - Tu bin theo yu cu khch hng cng bn a ho cng tt. - Gim ti a s thay i mi trng phn mm cng tt (bo m tnh tng thch ngc ca cc phn mm). - C th linh hot thay i trong qu trnh sn xut (c th ty bin chng trnh, mt n lp trnh c, ) 2.2.2. Cng ngh thit k ASIP Cng ngh thit k y l vic ty bin mt b x l hin ti hn l tng hp mt b x l mi vi mt tp lnh v kin trc mi c ti u ha cho mt nhm cc ng dng chun dng nh gi. 2.2.2.1. S lung thit k

Thit k theo phn mm truyn thngChng trnh nh dng tp lnh mi

Qu trnh gia cng to tp lnh mi

Cc hm

Chui lnh thc hin

Tu bin b vi x l vi tp lnh mi

Cp nht phn mm vi tp lnhHnh 2.5. S lung thit k ASIP


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S lung thit k ASIP c cho trong hnh 2.5. Vic thit k ban u s dng nhng phn mm c s (firmware) theo cc phng php truyn thng (Traditional Software Design), sau mt chng trnh nh dng tp lnh mi (New Instruction Identification) s gia cng to ra tp lnh mi chuyn bit. Ri b x l c ty bin thng qua vic b sung cc lnh chuyn bit v ng dng (Customize CPU). Cui cng, phn mm c s (firmware) c cp nht c th s dng c cc lnh mi. 2.2.2.2. nh dng tp lnh mi Tp lnh mi ni chung c mt trong s hai c trng sau. Chng hoc l mt tin trnh con trong phn mm c s (firmware) m c s dng thng xuyn hoc l mt chui cc lnh dng chung trong ng dng. V d v tin trnh con bao gm cc trnh iu khin thit b (device driver), cc phn t tnh ton c bn, cc b hn gi, v cc h iu hnh nguyn thu. V d chui cc lnh thng dng bao gm cc lnh dch v cng (shift-and-add) thng c s dng trong cc b lc s, vng qui khng, b chuyn i kiu d liu (ADC hoc DAC), d liu nh dng i vi cng Vo/Ra (I/O), kim tra tn hiu. 2.2.2.3. Kin trc b x l Phng php thit k y ph thuc vo kin trc b x l c c nh mt tp lnh v ng dn d liu, tuy nhin vn cho php b sung cc phn t logic iu khin v ng dn d liu mi thng qua vic lp trnh cho phn cng. Nhng, vic ny c hon thnh m khng lm thay i kin trc ca ton b b vi x l. Hai phng php tu bin thit k kin trc b x l c gii thiu trong hnh 2.6 v hnh 2.7. Nhng kin trc ny khng lm nh hng n bt k vng cm no trong khi gii m lnh, ng dn d liu hoc bus h thng. Do vy, cc kin trc ny ph hp vi a s cc b x l cng nghip. Vic tnh ton chuyn bit cng c th c thc hin trn mt thit b ngoi vi hot ng thng qua khi logic lp trnh c.


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a. Kin trc b gii m tnh (Static decode Architecture)

Khi iu khinKhi gii m lnh lgic c nh

Khi ng dn d

B chn/Kt hp

Bus iu khin

starti

donei

Khi logic lp trnh c

Bus 1 Bus N

Cc tn hiu iu kin v d liu Lgic c nh Lgic lp trnhHnh 2.6. Kin trc gii m tnh (Static-Decode Architecture) Kiu kin trc ny (hnh 2.6) ch cho php mt tp cc m lnh c xc nh trc s c s dng cho cc lnh mi, nh vy cn phi c mt cu trc gii m lnh hiu qu. Nu c bt k m lnh no c np vo v gii m, th tn hiu starti dnh cho m lnh i c kch hot. Cng lc , b x l giao vic iu khin ca cc tn hiu iu khin ng dn d liu n khi logic lp trnh c. Khi no m lnh i hon thnh, n kch hot tn hiu donei ring, sau iu khin ngc li. Cc lnh thc khng truy nhp n cc khi chc nng c thc hin thng qua khi logic lp trnh c. Kin trc ny cho hiu qu thc hin tt hn, nhng li phi chi ph nhiu cho vic nh v trc s lnh mi c th s dng khi logic lp trnh c. b. Kin trc b gii m ng (Dynamic decode Architecture) Kiu kin trc ny (hnh 2.7) linh hot hn v cho php cc m lnh mi c nh ngha trn c s ng dng. Vic gii m cc lnh mi c thc hin thng qua khi logic lp trnh c. Khi mt lnh nh vy c np vo, b x l khng th gii m lnh , tip theo n a ra mt tn hiu by trap bng vic gi mt


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tn hiu n khi logic lp trnh c. Nu khi logic lp trnh c c th gii m lnh , th sau lnh c kch hot. Nu lnh cha c khi logic lp trnh c nhn dng, th n kch hot mt tn hiu by trap hng dn cho khi gii m lnh lgic c nh khi ng qu trnh nhn dng lnh mi.

Khi iu khinKhi gii m lnh lgic c nh

Khi ng dn d

B chn/Kt hp

Bus iu khin

trap

trap' done

Khi logic lp trnh c

Bus 1 Bus N

Cc tn hiu iu kin v d liu Lgic c nh Lgic lp trnhHnh 2.7. Kin trc gii m ng (Dynamic-Decode Architecture) 2.2.2.4. Cp nht phn mm c s Mi mt ln mt lnh mi c thc hin trong b x l, th phn mm nhng c s li cn cp nht sa i s dng lnh mi ny. Tu thuc vo phng php trn phn mm c s dng, c ba cch thc hin vic cp nht ny. Th nht, nu phn mm c s l ngn ng dng ng gi hon chnh hoc cc lnh mi ch lin quan n mt phn ca phn mm c s th ch c phn m lnh ng gi c thay i. Nu phn mm s dng mt chng trnh bin dch ngn ng bc cao nh C v nu cc lnh mi c th p dng c vo cc ng dng khc, th sau cc lnh mi c th c b sung vo chng trnh bin dch .


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Khi cc chng trnh bin dch c cp nht li tr thnh cc cng c dng chung, th mt b tham s v kin trc mi ca b x l c th c thm vo chng trnh bin dch tr thnh kh dng i vi cc lnh mi. 2.2.3. Hng pht trin ca ASIP Trn y ch l mt trong s nhiu phng php lun v ng thit k v kin trc cho cc ASIP ng dng trong cc h thng nhng. Hin nay cn c nhiu phng php khc nghin cu v thit k ASIP. Vic tu bin ho tp lnh ca b vi x l theo yu cu ca tng ng dng ph thuc vo ngi thit k v do n t hng. 2.3. ng thit k phn cng/phn mm (Hardware/Software Co-Design) Nh chng ta bit hu ht cc h thng in t ngy nay (c h thng nhng hoc kt hp mt phn) u c cha mt phn ln cc thnh phn c s ho, cc phn cng hot ng c chnh l nh vo cc phn mm ng dng c ci t sn. ng thit k phn cng/phn mm chnh l s gp g mc h thng ca phn cng v phn mm thng qua qu trnh thit k. Hin nay vic thit k phn cng s c s pht trin gn nh tng ng vi thit k phn mm. Cc mch phn cng c m t bng cc ngn ng lp trnh hoc dng m hnh ho bng phn mm, v nh vy chng hon ton ph hp v hot ng theo s iu khin ca phn mm. i khi ngi ta gi l thit k phn cng chuyn bit. Do vy, vic thit k cc h thng s i hi ngi thit k phi nm rt vng c phn cng v phn mm. Mc ch ca mc ny ch gii thiu trong phm vi hp v ng thit k cc h thng phn cng/phn mm. Chng ta ch cp n cc bc ng thit k cc h thng phn cng/phn mm mc cao (tc l ch ni n thun tu v mt cng ngh). y ta ch cp n cc vn chung ch khng i su v mt vn no, nhm lm sng t s ging v khc nhau gia cc h thng s thit k kt hp vi cc h thng t nhin khc. Ta cng cp n cc k thut tng t nhau c p dng trong ng thit k cc h thng phn cng/phn mm.


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ng thit k cc h thng phn cng/phn mm l bao gm m hnh (modeling), ng dng (validation) v cch tin hnh (implementation). M hnh x l l cc tham s k thut mang tnh khi nim v nh ngha li v sn phm l cc m hnh phn cng v phn mm. ng dng x l l mc ng dng c th c ca ring h thng s lm vic nh c thit k v cch tin hnh l tin cy v mt vt l ca phn cng (trong qu trnh tng hp) v kh nng c th lm vic tng ng ca phn mm (trong qu trnh bin dch). Khi cp n cc h thng nhng cc mu m hnh khc nhau v cc chin lc th ta ch cp n hon ton phn cng (v d nh ASIC) v/hoc hon ton phn mm (phn mm nhng chy trn nn card ISA) v chng l cc h thng ng thit k. Do vy tt c cc m hnh h thng nhng u c kiu l thun nht (homogeneous) hoc khng thun nht (heterogeneous). Ngoi ra cn c m hnh ngn ng (v d nh m hnh lp trnh C chng hn) hoc cc hnh thc ho c dng trnh din c phn cng v phn mm. Vn phn chia phn cng/phn mm c th da vo cc tm tng phn ca m hnh thc hin tt nht trong phn cng v tt nht trong phn mm. Vic phn chia ny do ngi thit k thc hin da trn m hnh ban u hoc bng cc cng c CAD. Khi s dng m hnh khng thun nht, vic phn chia phn cng v mm thng da vo m hnh ca bn thn h thng, v cc thnh phn phn cng v phn mm c th c biu din theo cc ngn ng tng ng. V d, phin bn th nht ca mt sn phm c th c thm thnh phn phn mm v l do thi gian thng mi ho v tnh linh hot nhng n th h tip theo ca sn phm th thnh phn phn mm c th li c thc hin v l do gi thnh sn phm. ISA c m hnh ho theo cc mc khc nhau. Tp lnh cung cp cc thng tin cn thit v kin trc, h tr cho vic pht trin c phn cng v phn mm. Vic t chc x l thng c m t trong ngn ng c t phn cng HDL (Hardware Description Language) i vi mc ch tng hp thit k phn cng, trong khi cc m hnh b vi x l (v d nh m hnh cc bus chc nng) li thng s dng cc phng php gi lp kt hp.


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Trong trng hp cu hnh li h thng, chng ta cn phi ch phn chia gia m hnh ng dng ch v m hnh ch. Nhim v u tin thng ph hp vi h thng ca ngi dng, trong khi nhim v th hai tng ng vi mc pht trin h thng. Do vy, hai nhim v ny thng khc nhau v yu cu kt hp thit k. Do cc h thng ngy cng tr nn phc tp, vic ng dng l rt cn thit bo m cc chc nng lm vic chnh xc v yu cu cc mc hot ng ng theo m hnh hot ng ca h thng. Ngoi ra vic ng dng cng nh hng n s hot ng chnh ca h thng. S hot ng ca cc ng dng da trn s phi hp hot ng gia phn cng v phn mm. Mt khc cc h thng iu khin nhng yu cu phi c phn chia cc ng dng nhng s hot ng km hiu qu cn phi c kim tra trong tt c cc iu kin bo m an ton cho h thng. S hot ng ca h thng phn cng/phn mm c th gii quyt nhiu tin trnh con. 2.3.1. Phn chia phn cng/phn mm Vic phn chia h thng thnh phn cng v phn mm l yu cu rt quan trng v n l yu t u tin nh hng n c trng gi thnh/tnh nng ca vic thit k. Do vy, bt k s phn chia no cng phi tnh n cc chi tit ca vic phn chia thnh cc khi phn cng v phn mm. Cng thc ca vic phn chia phn cng v phn mm tuan th theo nguyn tc kt hp thit k. Trong trng hp cc h thng nhng, vic phn chia phn cng v phn mm chnh l vic phn chia v mt vt l cc chc nng ca h thng thnh cc ng dng c bit dnh cho phn cng v phn mm trn mt hay nhiu b x l. C nhiu quan im phn chia cng v mm da trn cc tiu ch nh kin trc hoc mc ch s dng... Khi cp n mc ch chung ca h thng my tnh, th vic phn chia h thng c thc hin theo cc chc nng logic, trong phn cng c thit k h tr cho s hot ng ca phn mm. Vic phn chia ny thng tun theo tp lnh. Do vy, vic la chn lnh nh hng n vic t chc phn cng v phn mm.


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Tuy nhin khi cu hnh li h thng th vic phn chia ph thuc vo mc u tin. i vi cc h thng ch c cc chip kiu FPGA, th vic phn chia cc chc nng h thng li thnh cc thnh phn tng ng vi cng ngh ch to [16]. 1. Quan im phn chia theo kin trc: quan im ny ch yu p dng trong cc h thng nhng vi cc b x l hot ng v cc ng dng phn cng, kin trc chung trong cc h thng ny l c th tham s ho nh l mt h ng x l... l cc b x l lm vic kt hp vi cc phn cng trong cc ng dng c bit. in hnh l cc kin trc x l ho 3-D vi ct cu phn cng h tr ring cho k thut ho. Giao din phn cng/phn mm c nh ngha kiu kin trc thay i m nh hng ln n vic phn chia ny. Ch yu n s dng vic nh x kiu b nh thng qua b x l hoc theo kiu truyn d liu. 2. Phn chia theo mc ch: Cc kin trc ng x l thng c chn ci thin hiu qu lm vic ca h thng theo cc thut ton c bit [5, 34]. Do vy, trong mt vi quan im phn chia a ra cch phn chia ng dng theo tc . Do s c lp ca d liu, trong mt vi phm vi ng dng th tc khng phi l cch phn chia tt. Nn trong cc ng dng thi gian thc c yu cu ngt ngho v mt thi gian, vic phn chia ny t ra khng hiu qu. 3. Cc chin lc phn chia: Mt s quan nim sai v cch thc phn chia l theo cch thc s dng cc cng c CAD. Thng thng vic xc nh phn cng i li vi s hot ng ca phn mm theo cc chc nng thi hnh cc mc tru tng m khng phi l c m hnh ho theo tham s h thng. Do vy c hai quan im phn chia: l phn chia m v phn chia theo quan nim kin trc. Da vo kin trc c bit r, ngi ta phn chia mc h thng theo cc chc nng m t nh vic gn nhn cho cc chc nng ca n theo s hot ng ca phn cng hay phn mm. Gii php chnh xc nht cho vn phn chia, thm ch trong trng hp n gin nht, cng i hi cch tnh ton cc k phc tp. Trong mt n lc a ra m hnh ton hc v vn phn chia, th cng thc ca m


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hnh lp trnh s nguyn IP (programming integer) v m hnh lp trnh tuyn tnh s nguyn ILP (programming linear integer) thng c s dng hn c. Vic so snh cc phng php m hnh ton hc v phn chia phn cng v phn mm rt kh khn, bi v cht lng ca vic phn chia i khi cn chu s nh hng ca gi thnh/tnh nng hot ng. Cc phng php m phn chia c hai tng chnh l: cc phng php xy dng chng hn nh cc cng ngh hp nhm v cc phng php lp nh l cc lung thng tin trn mng, k thut tm kim nh phn cng ch v m hnh lp trnh ng. Ngoi ra, hu ht cc phng php c s dng u da trn cc phng php tm kim theo su, chng hn nh s thay i ca phng php d on m KL (Kernighan-Lin), hoc cc phng php khc... Cn cc phng php theo quan nim kin trc th ch yu l theo nhim v, chc nng, tnh lin kt.... Ngoi nhng mi quan h rt mt thit gia cc chng trnh con vi nhau, th vic phn chia cn i mt vi cc vn nh la chn gia cc yu t tnh nng/gi thnh cng l mt bi ton kh. Trong khi cc phng php c lng tt i vi s hot ng ca phn cng th cc tham s phn mm ni chung ph thuc vo rt nhiu yu t... 2.3.2. Lp chng trnh thc hin (Scheduling) Lp chng trnh thc hin c rt nhiu vn cn cp n. Cc gii thut lp chng trnh do cc nh nghin cu ln gii khoa hc my tnh a ra theo nhiu m hnh v quan im khc nhau p dng vo k thut thit k cc h thng phn cng v phn mm. Thc t, mt s gii thut lp chng trnh cho phn cng da trn cc k thut c s dng trong phn mm v mt s phng php lp chng trnh mc h thng - ngc li da trn cc tng xy dng phn cng. Lp chng trnh c th hiu mt cch gn ng nh l vic gn mt kch hot start time cho mt mt s kin trong mt tp, trong cc s kin c lin kt thng qua mt s mi lin h (nh l tnh c lp, mc u tin,).


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Mt s gii thut lp chng trnh c p dng vo vic thit k phn cng, trnh bin dch v h iu hnh nh sau: - Lp chng trnh hot ng trong phn cng: tng t nh vic thit k ASIC bng cc ngn ng HDL. - Lp chng trnh lnh trong cc trnh bin dch: cc trnh bin dch l cc cng c phn mm phc tp, gm c cc thit b ngoi vi, c ch nh tuyn lm vic ti u trn cc khun dng tc thi v cc chng trnh ph tr. - Lp chng trnh x l trong cc h iu hnh khc nhau: chnh l vn xc nh khi cc cc x l kch hot v gm c c ng b v ngn chn cc s c. Cc gii thut i vi lp chng trnh x l rt quan trng i vi cc h iu hnh v cc chng trnh thc hin di thi gian thc. 2.3.3. Nhn xt ng thit k phn cng/phn mm l mt vn rt kh hin nay v chnh l cc c hi th thch i vi cc nh thit k h thng. Vic s dng v s dng li cc khi lnh phn cng v phn mm c th to ra cc sn phm vi cht hng u (nh l v gi c, tnh nng, linh hot, ) vi thi gian thit k v pht trin ngn hn ging nh chng vic chng ta so snh cc th h cng ngh ch to mt mch tch hp (IC). Ch yu hin nay chng ta vn ang s dng cc cng c CAD c sn thit k v ch to cc h thng phn cng/phn mm. Cc nh khoa hc v cc nh thng mi vn nui hy vng vo cc phng php v cc cng c ng thit k phn cng/phn mm tng trng v pht trin mnh trong nhng nm ti y. Nhn chung, ng thit k phn cng/phn mm l mt lnh vc nghin cu rt rng, do tnh a dng ca cc ng dng, cc cch thc thit k v cng ngh ch to cng nh hot ng.


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Chng III. Gii thiu bo mch Spartan -3 starter kid board v mi trng lp trnh ISE 7.1I. Tng qut. y l h FPGA mi nht ca Xilinx vi nhiu u im ni bt. u

tin phi k n l kh nng tch hp ca Spartan-3 t 50,000K-gate n 5 triu Kgate. Mt s c im chnh ca Spartan-3 l: - Gi thnh thp, tiu th in nng t. - Mt tch hp ln n 74K trn mt phn t logic - Tc xung nhp h thng ln n 325MHz - 3 mc tiu th in nng (1.2V; 3.3V; 2.5V) - C 784 chn - Tc truyn d liu ln n 622Mbps Bng 3.2. Mt s sn phm ca dng Spartan-3 Tn sn phm S cng ca h thng Cc phn t logic S hng S ct Khi RAM S chn

XC3S200 XC3S400 XC3S1000 XC3S2000 XC3S4000 XC3S5000

200K 400K 1M 2M 4M 5M

4320 8064 17280 46080 62208 74880

24 32 48 80 96 104

20 28 40 64 72 80

216K 288K 432K 720K 1728K 1872K

173 264 391 565 712 784

Hin nay vi dng sn phm Spartan-3 Platform FPGA Xilinx tr thnh hng u tin trn th gii tip cn cng ngh 90nm.


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Spartan -3 starter kid board l mt cng c hu hiu cho bt k ai ang c nh thit k cc sn phm da trn cng ngh FPGA (Field-Programmable Gate Array) vi mt gii php c bn cho vn tranh th thi gian v chi ph ban u thp. N cho php ch to ngay v gi thnh sn phm thp v l mt thit b cu trc logic c th c ngi s dng lp trnh trc tip m khng phi s dng bt k mt cng c ch to mch tch hp no. Trong phn ny ta ch gii thiu s qua cc chi tit c th nhn thy t giao din b ngoi ca bo mch. Cc chi tit c th, cc c im cng nh cc vn cn ch i vi mi thnh phn trn bo mch s c trnh by c th trong mi ng dng sau ny. Hnh 3.1 l hnh nh ca Spartan-3 Starter Kit Board nhn t mt trn. Hnh 3.2 l hnh nh ca Spartan-3 Starter Kit Board nhn t mt di. Hnh v 3.2 l hnh nh ca Spartan-3 Starter Kit Board khi ta tri trn mt phng.

Hnh 3.1 . Spartan-3 Starter Kit Board nhn t mt trn


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Hnh v 3.2 : Spartan-3 Starter Kit Board nhn t mt di

Spartan-3 Starter Kit Board: bao gm cc thnh phn vi cc c trng sau ( y ta ch gii thiu nhng thnh phn c lin quan n ng dng sau ny, chi tit chng ta tm hiu phn Gui ca SP3 trn http://xilinx.com). 1. Khi s 1: chnh l chp iu khin chung Xc3s200ft256. Tn gi ca n rt quan trng v chng ta s cn phi s dng sau ny khi thc hin vic gn chn. 2. Khi s 2 v khi 3 : l Prom loi XCF02S, n c chc nng lu tr cc cu hnh cng nh chng trnh np t trnh dch vo. 3. Khi s 5 : y l cng kt ni VGA. Spartan 3 c kh nng kt ni vi mn hnh v hin th cc d liu bng vic thc hin qut dng qut mnh theo phng thc qut ln lt. Chi tit v vic to nh trn mn hnh hin th s c phn tch c th trong phn ng dng s c cp phn sau. 4. Khi s 6,7: Cng kt ni Rs232. 5. Khi 9 : Kt ni vi bn phm hoc l chut. 6. Khi s 10 : Cc led 7 on. C th l c 4 led 7 on anot chung. 7. Khi 11: 8 chuyn mch. C th dng chn ch lm vic, hoc cho nhng ng dng kim tra khi thit k thc hin chc nng 8 bt u vo s. 8. Khi 12: 8 led, dng kim tra qu trnh thit k. L mt trong nhng phng tin kim tra u ra hiu qu cc chng trnh m chng ta thit k.


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9. Khi 13: 4 nt n. Cng tng t nh 8 chuyn mch, chng ta c th dng n chn ch lm vic cho bo mch. 10. Khi 15 : V tr cm ca b to dao ng thch anh. B to dao ng thch anh to ra dao ng chun 50mhz. Chnh v vy, trong qu trnh thit k, vi cc ng dng c th cn thc hin lm vic tn s ng b no chng ta phi thc hin chia tn s trung tm ny ra t c tn s mong mun. Thc t, chng ta hon ton c th kt ni vi mt b to dao ng a vo t ngoi thng qua cc thnh phn kt ni A1,A2, B1 nh ch ra trn hnh v. 11. Khi 17 v 18: Khi ng chng trnh thng trc trong Rom. Chi tit ny s c phn tch k khi thc hin mt chng trnh c th. 12. y chng ta cng cn quan tm n cc khi 19, 20 v 21: y l cc thnh phn dng kt ni vi ngoi vi hoc dn tn hiu ra sau khi thc hin x l. Cc khi ny tng ng vi cc thnh phn c k hiu trn bo mch l A1, A2, B1. y l mt chi tit quan trng v cn phi c bit quan tm v cch thc thc hin u cui s liu.Chnh v vy khi tin hnh thc hin kt ni vi thnh phn ngoi phi quan tm n cc mc in p cng nh cc chn tng ng ca n. tin hnh dung chng ta xt mt cng A1 nh sau

Hnh 3.2 Cng kt ni ngoi vi A1

Th t ca cc chn t phi qua tri, vi chn s mt l chn GND, chn s 3 l chn tng ng vi in p +3.3V, chn s 2 tng ng mc +5V. Nh vy cc chn l tr chn 1 ni t, cc chn l cn li s c kt ni mc in p +3.3V, cc chn chn s c kt ni mc in p +5V. 13. Ngoi ra n cn mt s thnh phn khc na. d hnh dung hn chng ta c th quan st hnh v di y m t cc thnh phn c kt ni vi XC2s300.


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Hnh 3.3: S khi cc thnh phn trn Spartan-3 Starter Kit Board


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II. Gii thiu mi trng lp trnh ISE. Khi kch thc v phc tp ca cc h thng s gia tng, nhiu cng c thit k c tr gip bi my tnh CAD (Computer Aided Design) c a vo qu trnh thit k phn cng. Phng php thit k trn giy c thay bng cch thit k trn my tnh, t cc nh thit k c th kim tra v c cc cng c to ra phn cng t ng t cc bn thit k . H tr mnh m nht cho cc cng c thit k ny l cc ngn ng m t phn cng HDL (Hardware Description Languages). Hin nay, cc nh nghin cu tm ra nhiu cch cho php HDL c th ci tin qu trnh thit k h thng s. Qu trnh thit k bt u t tng thit k ca ngi thit k phn cng. Lc ny ngi thit k cn phi to ra cc nh ngha cho hnh vi ca h thng di thit k. Sn phm ny c th l dng s khi, lu hoc ch l dng ngn ng t nhin. Giai on ny tng thit k mi ch c u vo v u ra, ch hon ton cha c mt chi tit no v phn cng cng nh kin trc ca h thng. Giai on th hai ca qu trnh thit k l vic thit k ng dn d liu h thng. Trong giai on ny, ngi thit k ch r cc thanh ghi v cc phn t logic cn thit cho qu trnh ci t. y chnh l giai on thit k th vin cc phn t cho h thng. Cc thnh phn ny c th c kt ni thng qua bus 2 chiu hoc 1 chiu. Da trn chc nng hoc hnh vi ca h thng, tin trnh iu khin hot ng ca d liu gia cc thanh ghi v cc phn t logic thng qua cc bus c pht trin. Giai on ny khng cung cp cc c im v s hot ng ca cc b iu khin, cch i dy, k thut m ho Giai on th 3 l l giai on thit k logic, giai on ny lin quan n ng dng ca cc cng v cc mch c bn cho vic ci t cc thanh ghi d liu, cc bus h thng, cc phn t logic v phn cng iu khin chng. Kt qu ca giai on ny chnh l mt danh sch kt ni (netlist). Giai on thit k tip l chuyn netlist ca giai on trc thnh s hay l danh sch cc tranzitor. Giai on ny xt n c ch ti v thi gian trong qu


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trnh thc hin hnh vi ca h thng cng nh vic chn tranzitor hoc cc phn t ca n. Giai on ny bao gm: tng hp logic, nh x cng ngh, flooplanning, placement, routing. Giai on ny s dng cng c CAD l ch yu. Giai on cui cng l np vo kid v kim tra kt qu, hon chnh sn phm. 2.1. Gii thiu gi phn mm ISE: Phn mm ISE (Integrated Software Environment) ny l mt mi trng thit k hon ho ca Xilinx, n tr gip cho ngi thit k hu ht cc cng c cn thit nht c th hon thnh mt n thit k nhanh nht v hiu qu nht. ISE tch hp cc cng ngh tin tin nht mng li tnh linh hot, giao din GUI thn thin vi ngi s dng. Mt s u im ca ISE l: - Tn dng ti a tt c cc cng ngh tin tin nht ca PLD. - Tit kim thi gian thit k, h tr tt c cc dng sn phm ca Xilinx. - Tng hiu qu v gim gi thnh. - H tr ti a cho vic thit k cc h thng nhng. B sn phm ISE bao gm cc gi phn mm: a. ISE WebPACK: y l gi sn phm dng pht trin h thng mt cch d dng nht v n l mi trng thit k on-line (trc tuyn) trn Web v c h tr trc tip t Xilinx. ISE WebPACK cho php ngi dng hon thnh bn thit k nhanh chng nh s kt hp ca cc thit k u vo HDL, cc cng v tng hp tin tin v kh nng kim tra i vi c CPLD v FPGA trc tuyn. b. ISE BaseX: y l gi phn mm hiu qu v kinh t nht, l mi trng thit k PLD trn my tnh c nhn linh hot v n nh. N cung cp tt c cc kh nng nh ISE WebPACK, ngoi ra n cn c b sung nhiu cng c khc h tr cho ngi dng. c. ISE Alliance: gi phn mm ny c thit k ph hp vi mi trng thit k c sn ca ngi dng. N kt hp cc cng c hay nht ca Xilinx to mi trng thit k hon chnh vi cc tnh nng cao hn ISE BaseX.


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d. ISE Foundation: y l gi phn mm hon chnh nht, d s dng, tnh nng nhiu nht ng thi tch hp cc cng c phn tch, tng hp v cng ngh kim tra sn phm vi cc gii php hu hiu. 2.2. Hng dn s dng phn mm ISE Foundation 7.1 Giao din chng trnh

Hnh 3.4: Giao din chnh ca mi trng lp trnh ISE 7.1Hng dn cc bc to mt n mi ( y la chn kid l Spartan 3) Bc 1: T mnu file next: new project in tn vo Poject name chn ngn ng vit chn th mc lu project location

Hnh 3.5: To mt n mi


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Bc 2: La chn kid l spartan-3, loi Xc3s200, speed grade l -4, ngn ngi son tho l VHDL, m phng dng ModenSim.

Hnh3.6: Cc la chn c th cho mt n.Bc 3.Sau khi l xong bc trn chng ta next, s c mt ca s ta thm ngun mi vo n. Chn New source module chn tn m un next: next chn Vhdl

Hnh 3.7: Thm mt module vo n thit k.


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Bc 4: Chn cc cng vo ra cho n.

Bao gm tn cng, m t vo (in), ra(out) hay vo ra (inout). S bt vo ra tng ng vi cc cng. Cc bc tip theo c next n khi k thc (finish). Sau khi nh ngha v m t xong bc ny lc trnh dch s t ng to ra thc th vi cc cng c m t bng lnh ( VHDL) nh sau: entity chiatansodauvao is Port ( clock : in std_logic; 1hz : out std_logic; led : out std_logic_vector(7 downto 0)); end chiatansodauvao; architecture Behavioral of chiatansodauvao is begin end Behavioral; Nh vy ta to ra mt n. Tip theo l ta vit chng trnh ca s son tho. Vn t ra l vi chng trnh ln c nhiu hn mt m ule ta s lm th no? chng ny ta ch gii thiu cch thc chng ta to ra mt n mi. Cc phn cn li bao gm kim tra cu trc lnh, kim tra mc logic, gn chn, np cu hnh chy th s c hng dn chi tit cng vi bi tp c th.


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CHNG IV: NGN NG VHDL4.1. Gii thiu chung v ngn ng VHDL VHDL (VHSIC Hardware Description Laguage) l mt ngn ng c dng m t cc h thng in t s. N c chng trnh quc gia v Cc mch tch hp Tc rt cao - VHSIC (Very High Speed Integrated Circuits) do chnh ph M khi xng vo u nhng nm 1980. Cc cng ty tham gia chng trnh VHSIC nhn thy rng h cn phi c mt cng c no thit k cc gin u vo cho cc IC chuyn dng c ln, v h xut vic lp ra mt ngn ng m t phn cng dng m t cu trc v chc nng ca cc mch tch hp (cn c gi l IC - Integrated Circuits). K t , VHDL ra i v c pht trin, ri sau c Hip hi cc k s in v in t - IEEE (Institude of Electrical and Electronic Engineers) chp nhn coi nh l tiu chun ti M. Phin bn u tin l Tiu chun IEEE 10761987 (cn c gi l VHDL-87). Phin bn ny c b sung sa i nm 1993 thnh IEEE 1076-1993 (cn c gi l VHDL-93). VHDL c thit k nhm thay th cho mt s khu cn thit trong qu trnh thit k. u tin, n cho php m t cu trc ca mt bn thit k, tc l lm th no c th phn tch bn thit k thnh cc bn thit k con, v lm th no kt ni cc bn thit k con li vi nhau. Th hai l n cho php m t c im chc nng ca cc bn thit k tng t nh trong ngn ng lp trnh. Th ba l da vo kt qu t c, n cho php mt bn thit k c th m phng c trc khi a vo sn xut, v vy cc nh thit k c th so snh mt cch nhanh chng vic thay th v kim tra iu chnh chnh xc m khng mt thi gian v tin bc vo vic ch to mu th u tin. 4.1.1. M t cu trc (Describing Structure) Mt h thng in t s c th c m t thnh cc khi - cn gi l modul (module) vi cc u vo v/hoc u ra. Cc gi tr in 0 u ra c mi quan h


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vi cc gi tr trn cc u vo. Hnh 4.1.a biu din mt v d nh vy. Khi F c hai u vo A v B, v c mt u ra Y.

Hnh 4.1. (a) Khi F c hai u vo v mt u ra; (b) Khi F gm c 3 thc th G, H v I S dng ngn ng VHDL m t khi F, th ta gi khi F l mt thc th (entity) thit k, v cc u vo v u ra l cc cng (port). C mt cch m t chc nng ca khi F, l chng ta m t cc khi con (sub-module) thnh phn ca n. Mi mt khi con c gi l mt tp hp (instance) ca mt vi thc th, v cc cng ca cc tp hp c ni li bng cc ng tn hiu (signal). Hnh 4.1.b m t khi F l mt tp hp gm cc thc th G, H v I. Kiu m t ny c gi l m t cu trc (structural). Cc thc th G, H v I cng c m t theo cu trc tng t nh vy. 4.1.2. M t hot ng (Describing Behaviour) Trong nhiu trng hp, vic m t cu trc khng tng ng vi vic m t hot ng. Ngi ta thng dng cch m t hot ng theo kiu t di ln da vo m t cu trc. V d, khi chng ta thit k h thng in t th khng cn phi m t c th cu trc bn trong ca tng con IC m ch cn m t theo chc nng ca cc khi ca h thng m thi. Trng hp ny c gi l m t chc nng (fuctional) hoc m t hot ng (behavioural).


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minh ho cho iu ny, chng ta gi s rng chc nng ca thc th F trong hnh 4.1(a) l mt mch OR o. Khi m t hot ng ca F ta c th bin i theo i s Boolean nh sau:Y = A.B + A.B

i vi cc mch c chc nng hot ng phc tp hn, th khng th bin din theo cc chc nng u vo c. Trong cc h thng c phn hi ngc, u ra thng l cc hm chc nng theo thi gian. Ngn ng VHDL cho php gii quyt vn ny bng cch m t hot ng theo khun dng chng trnh lp trnh. 4.1.3. M hnh thi gian theo cc s kin ri rc Khi chc nng hot ng v cu trc ca khi c ch nh r, th ngi ta c th m phng khi bng cch kch hot theo m t hot ng ca n. iu ny c th thc hin c bng cch m phng qu trnh hot ng c ri rc thnh cc bc theo thi gian. Ti mt vi thi im m phng, khi u vo c kch hot bng cch theo i gi tr trn cng u vo. Khi ny phn ng li bng cch thc hin m lnh theo m t hot ng ca n c gn v to ra cc gi tr mi a n ng tn hiu a n cc cng u ra ca n ti cc thi im m phng tip theo sau. Vic ny c gi l k hoch giao tc (scheluding a transaction) trn tn hiu . Nu gi tr mi khc gi tr trc c trn ng tn hiu, th s c mt s kin (event) xy ra, v cc khi khc vi cc u vo c kt ni vi ng tn hiu c th s c kch hot. Qu trnh m phng bt u vi mt pha c gi l pha khi ng (initilation phase), v sau cc qu trnh c thc hin lp li hai giai on trong mt chu k m phng (simulation cycle). Trong pha khi ng, tt c cc tn hiu c cung cp sn cc gi tr khi ng, thi gian m phng c a v 0, v mi mt chng trnh hot ng ca mt khi c kch hot. Trong giai on u tin ca chu k m phng, thi gian m phng c nng ln thnh thi gian sm nht ti thi im m giao tc c thc hin. Tt c cc


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giao tc c a vo ti thi im ny u c kch hot, v iu ny c th gy ra mt s s kin no . Trong gian on th hai ca chu k m phng, tt c cc khi m phn ng li i vi cc s kin va xy ra trong giai on mt s kch hot chng trnh hot ng ca chng. Cc chng trnh thng l k hoch giao tc trn cc tn hiu u ra ca chng. Khi tt c cc chng trnh kt thc hot ng, chu k m phng c lp li. Nu khng c thm giao tc no th qu trnh m phng hon thnh. Mc ch ca vic m phng l bit thm thng tin v s thay i trong h thng ti tng thi im. Vic ny c th thc hin c gim st bi chng trnh kim sot m phng (simulation monitor). Chng trnh ny nhm mc ch ghi li qu trnh hot ng theo tng thi im ti cc im dng vo vic phn tch v sau. 4.1.4. V d Chng ta c mt b m hai bit COUNT nh trong hnh v 4.2, gm c 3 khi: 2 khi T_FLIPFLOP v mt khi INVERTER. B m ny c 2 u ra l q1 v q0, mt u vo l clock.

Hnh 4.2. S b m COUNT Dng ngn ng VHDL nh ngha b m ny nh sau: entity count2 is generic (prop_delay : Time := 10 ns);


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port (clock : in bit; q1, q0 : out bit); end count2; Nhn vo on chng trnh trn chng ta thy b m COUNT c nh ngha vi mt cng vo clock v hai cng ra q1, q0 u thit lp theo cc gi tr bit. Hng s prop_delay c s dng iu khin hot ng ca COUNT vi thi gian m s l 10 ns mt ln. Trn y mi ch l nh ngha b m, cn hot ng ca b m ny s c vit theo hai cch. Cch th nht l vit theo hot ng ca b m: architecture behaviour of count2 is begin count_up: process (clock) variable count_value : natural := 0; begin if clock = '1' then count_value := (count_value + 1) mod 4; q0 clock, q => ff0); inv : inverter port map (a => ff0, y => inv_ff0); bit_1 : t_flipflop port map (ck => inv_ff0, q => ff1); q0 r.b, b => r.a) := r


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4.2.4.2. Khai bo If (nu) Khai bo If cho php la chn cc khai bo kch hot ph thuc vo mt hoc nhiu iu kin. C php l: khai bo if ::= if iu kin then chui cc khai bo { elsif iu kin then chui cc khai bo [ else chui cc khai bo } end if; Cc iu kin l cc biu thc tr v gi tr boolean. Cc iu kin c nh gi l ng khi c mt gi tr c tr v true. Ngc li th mnh else c thc hin, v khai bo ca n c kch hot. 4.2.4.3. Khai bo Case (cy) Khai bo case cho php la chn cc khai bo kch hot ph thuc vo gi tr ca mt biu thc chn. C php l: khai bo case ::= case biu thc is khai bo case c th chn { khai bo case c th chn } end case; khai bo case c th chn ::= when cc la chn => chui cc khai bo cc la chn ::= la chn { | la chn} la chn ::= biu thc n | phm vi n


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| tn phn t n | others Biu thc chn phi a n hoc l kiu ri rc hoc l mng mt chiu cc k t. Khi mt la chn trong danh sch cha gi tr ca biu thc c chn th khai bo ca la chn c kch hot. Cc la chn phi c lp, khng c gi tr trng nhau. Ngoi ra, tt c cc gi tr phi c biu din trong bng danh sch cc la chn, hoc others c bit phi nm trong khai bo cui cng. Nu khng c la chn no cha gi tr ca biu thc, th others s c chn. Nu biu thc kt qu l mt mng, th cc la chn c th l mt xu hoc mt xu bt. V d th nht: case element_colour of when red => statements for red; when green | blue => statements for green or blue; when orange to turquoise => statements for these colours; end case; V d th 2: case opcode of when X"00" => perform_add; when X"01" => perform_subtract; when others => signal_illegal_opcode; end case; 4.2.4.4. Cc khai bo vng lp VHDL c mt khai bo vng lp c bn c th s dng cc vng lp while v for ging nh trong cc ngn ng lp trnh khc. C php ca mt khai bo vng lp l: khai bo vng lp ::=


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[ nhn vng lp : ] [ lc lp ] loop chui cc khai bo end loop [ nhn vng lp ]; lc lp ::= while iu kin | for c im tham s lp c im tham s lp nh danh in phm vi n Nu lc lp b b qua, chng ta s b ri vo vng lp v tn. V d v mt vng lp v tn: loop do_something; end loop; Lc lp while cho php kim tra mt iu kin nh gi trc mi mt vng lp. Vng lp ch c thc hin nu vic kim tra c nh gi l ng (true). Nu vic kim tra l sai (false), th khai bo vng lp s kt thc. V d nh sau: while index < length and str(index) /= loop index := index + 1; end loop; Lc lp for cho php ch nh mt s c nh vng lp. c im tham s lp c m t l mt i tng s thc hin vi gi tr ng trong phm vi cho i vi mi vng lp. Cng vi cc khai bo ng trong vng lp, i tng c coi nh l hng s, v do vy khng th gn c. V d nh: for item in 1 to last_item loop table(item) := 0; end loop;


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C hai khai bo b sung c th s dng bn trong vng lp kim tra mu c s ca vng lp. Khai bo next kt thc vic kch hot vng lp hin thi v bt u vng lp con. Khai bo exit kt thc vic kch hot vng lp hin thi v kt thc lun vng lp. C php ca cc khai bo l: khai bo next ::= next [ nhn vng lp ] [ when iu kin ]; khai bo exit ::= exit [ nhn vng lp ] [ when iu kin ]; Nu nhn vng lp b b qua, th khai bo c p dng cho vng lp gn n nht, ngc li n c gn cho tn ca vng lp. Nu mnh when tn ti nhng iu kin li sai (false), th vng lp s tip tc bnh thng. V d: for i in 1 to max_str_len loop a(i) := buf(i); exit when buf(i) = NUL; end loop; V d: outer_loop : loop inner_loop : loop do_something; next outer_loop when temp = 0; do_something_else; end loop inner_loop; end loop outer_loop; 4.2.4.5. Khai bo Null (rng) Khai bo null khng c hiu qu. N c th c s dng biu din trng thi r rng l khng c hnh ng no c yu cu trong trng hp . Ngi ta thng s dng n trong cc khai bo case, trong tt c cc gi tr c th ca biu thc la chn phi c lit k chn, nhng i vi mt vi la chn th khng yu cu hnh ng no. V d:


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case controller_command is when forward => engage_motor_forward; when reverse => engage_motor_reverse; when idle => null; end case; 4.2.4.6. Cc xc nhn Mt khai bo xc nhn c s dng kim tra mt iu kin c ch nh v lp bo co nu iu kin b vi phm. C php l: khai bo xc nhn ::= assert iu kin [ report biu thc ]; -- bo co bng biu thc [ severity biu thc ]; -- mc vi phm bng biu thc Nu mnh report tn ti, kt qu ca biu thc phi tr v mt xu. y l thng ip s c bo co nu iu kin l sai (false). Nu n b b qua, thng ip mc nh l Assertion violation. Nu mnh severity tn ti, biu thc phi tr v mc vi phm severity_level. Nu n b b qua, gi tr ngm nh l error. 4.2.5. Cc chng trnh con v cc dng ng gi Ging nh cc ngn ng lp trnh khc, VHDL cung cp cng c thc hin chng trnh con linh hot di dng cc th tc v cc hm. VHDL cng cung cp mt kiu ng gi mnh i vi tp cc m t v cc i tng a vo cc n v dng modul. Cc ng gi cng cung cp mt tiu chun v tnh tru tng d liu v thng tin n. 4.2.5.1. Cc th tc v hm Cc chng trnh con dng th tc v hm c m t theo c php sau: m t chng trnh con ::= c im chng trnh con ; c im chng trnh con ::= procedure tn ch nh [ ( danh sch tham bin chnh ) ] | function tn ch nh [ ( danh sch tham bin chnh ) ] return nh du kiu tr v


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Mt chng trnh con m t theo c php trn c cc tn n gin ca chng trnh con v ch nh tham s theo yu cu. Thn ca cc khai bo nh ngha hot ng ca chng trnh con phi thc hin theo. i vi cc chng trnh con dng hm (function), vic m t cng ch ra kiu ca kt qu tr v khi hm c gi. Khun dng chng trnh con ny m t kiu thng dng c dng trong cc c im ng gi (xem thm mc 3.2.5.3), trong thn chng trnh con c gn trong thn ca ng gi, hoc nh ngha cho cc th tc qui. C php i vi vic ch nh cc tham bin chnh ca chng trnh con l: danh sch tham bin chnh ::= danh sch giao din tham s danh sch giao din ::= phn t giao din { ; phn t giao din } phn t giao din ::= m t giao din m t hng s giao din | m t tn hiu giao din | m t bin giao din m t hng s giao din [constant] danh sch nh danh : [in] k hiu kiu con [ := biu thc tnh ] m t bin giao din [variable] danh sch nh danh : [mode] k hiu kiu con [ := biu thc tnh ] Chng ta ch cp n cc tham s hng s v cc tham s bin, mc d cc tham s tn hiu cng c th c s dng, tuy nhin phn ny c cp n trong mc 3.3. u tin l v d n gin v mt th tc khng c tham s: procedure reset; Vic gi th tc reset trn thc hin n gin nh sau: reset; Tip theo l mt th tc c vi tham s: procedure increment_reg(variable reg: inout word_32; constant incr: in integer := 1)


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Th tc increment_reg c hai tham s l reg v incr. reg l tham bin, trong thn chng trnh con n c s dng nh mt i tng bin v c th gn cho n c. Cn khi th tc increment_reg c gi th tham s thc phi tng ng vi bin reg v bn thn tham s thc cng phi l bin cng kiu. Ch ca reg l inout, c ngha l bin ny c th c hoc gn. Nu ch c ch in - tc l ch c, cn out - tc l ch gn. Khi ch l inout hoc out th c th b qua t variable v c ngm nh. Cn tham s th hai l incr, l mt tham hng (tham s hng s), c ngha l n c gn l mt i tng hng s trong thn chng trnh con, v khng th gn cho n c. Vic gi mt chng trnh con bao gm mt danh sch cc tham s thc tng ng vi tham s chnh ca chng trnh con c th c v v tr v tn gi hoc c hai. V d: increment_reg(index_reg, offset-2); -- b sung gi tr vo index_reg increment_reg(prog_counter); prog_counter Vic gi theo tn gi tng ng theo tham s chnh nh v d sau: increment_reg(incr => offset-2, reg => index_reg); increment_reg(reg => prog_counter); Trong lnh gi th hai, tham s incr khng c, nn n c gn gi tr mc nh. V d v m t mt hm: function byte_to_int(byte : word_8) return integer; Hm trn ch c mt tham s. i vi cc hm, ch tham s phi l in. Nu lp tham s khng c ch nh th n c coi nh l constant. Gi tr tr v ca hm trn phi l mt s nguyn (integer). Khi thn ca chng trnh con c ch nh, c php s dng nh sau: thn chng trnh con ::= tham s chng trnh con is -- b sung 1 (mc nh) vo


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thnh phn m t chng trnh con begin thnh phn khai bo chng trnh con end [tn ch nh]; thnh phn m t chng trnh con ::= {mc m t chng trnh con} thnh phn khai bo chng trnh con ::= {khai bo tun t} mc m t chng trnh con ::= m t chng trnh con | thn chng trnh con | m t kiu | m t kiu con | m t hng s | m t bin | m t tn ph Cc mc m t chng trnh con c lit k sau c im ca chng trnh con m t tt c nhng g c s dng cc b trong thn chng trnh con. Tn ca cc mc ny khng nhn thy c ngoi chng trnh con. Ngoi ra, cc mc ny l bng ca tt c nhng g c cng tn c m t ngoi chng trnh con. Khi mt chng trnh con c gi, cc khai bo trong thn c kch hot n khi hoc l gp du kt thc danh sch khai bo hoc khi mt khai bo quay li (return) c kch hot. C php ca mt khai bo quay li nh sau: khai bo quay li ::= return [biu thc]; Nu mt khai bo quay li xy ra trong thn ca mt th tc, th n phi khng c cha mt biu thc. V cng phi c t nht mt khai bo quay li trong thn mt hm, n phi cha mt biu thc, v hm c kt thc bng vic kch hot mt khai bo quay li. Gi tr ca biu thc l gi tr c tr v khi gi hm. V d : function byte_to_int(byte : word_8) return integer is


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variable result : integer := 0; begin for index in 0 to 7 loop result := result*2 + bit'pos(byte(index)); end loop; return result; end byte_to_int; 4.2.5.2. Overloading (trng tn) VHDL cho php hai chng trnh con cng tn, nhng tn v kiu ca cc tham s phi khc nhau. Tn ca chng trnh con nh vy c gi l tn overloaded (trng tn). Khi thc hin gi mt chng trnh con s dng tn overloaded, th s lng tham s thc, th t ca chng, kiu ca chng v cc tn tham s chnh tng ng c s dng xc nh l chng trnh con no c gi. Nu cuc gi l mt cuc gi hm, th kiu kt qu tr v s c s dng. V d, chng ta c hai chng trnh con sau: function check_limit(value:integer) return boolean; function check_limit(value:word_32) return boolean; Sau , khi hm no c gi th cn c vo gi tr ca kiu integer hay l word_32 m tham s thc s dng bit. Chng hn: test:=check_limit(4095) s gi hm th nht, cn: test:=check_limit(X0000_0FFF) s gi hm th hai. Ngi s dng c th s dng cch nh ngha tn chng trnh con theo mt nh danh hoc mt xu biu din bi cc k hiu ton t nh lit k trong phn 2.2.3. V d nh sau: function +(a,b:word_32) return word_32 is begin return int_to_word_32(word_32_to_int(a)+word_32_to_int(b));


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end +; Ton t cng, khi thc hin php tnh ca mnh, ch thc hin vi cc ton hng l s nguyn. Cn khi hm + ny c gi th n li thc hin biu thc vi kiu word_32 theo hai cch nh sau: X1000_0010 + X0000_FFD0 hoc l: + (X1000_0010,X0000_FFD0) 4.2.5.3. ng gi v m t thn cc ng gi Mt ng gi l mt tp bao gm cc kiu, cc hng s, cc chng trnh con v c th c cc thnh phn khc, thng thng n c d nh cho hot ng ca mt vi dch v thnh phn hoc tch mt nhm cc thnh phn c lin quan vi nhau. c bit, chi tit cc gi tr hng s v cc thn chng trnh con c th n do ngi dng, chng ch nhn thy c giao din m thi. Mt ng gi c th phn chia thnh hai phn: phn m t ng gi dng nh ngha giao din ca n v phn thn ng gi dng nh ngha cc chi tit khc. Phn thn c th b qua nu chng khng c chi tit no. C php ca phn m t ng gi nh sau: m t ng gi ::= package tn nh danh is phn m t ng gi end [tn n ca ng gi]; phn m t ng gi ::= {thnh phn m t ng gi} thnh phn m t ng gi ::= m t chng trnh con | m t kiu | m t kiu con | m t hng s | m t tn ph | mnh s dng


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Cc m t nh ngha cc thnh phn khc m nhn thy c i vi ngi dng ng gi, v chng cng nhn thy c bn trong ca thn ng gi. V d : package data_types is subtype address is bit_vector(24 downto 0); subtype data is bit_vector(15 downto 0); constant vector_table_loc : address; function data_to_int(value : data) return integer; function int_to_data(value : integer) return data; end data_types; Trong v d trn, gi tr ca hng s vector_table_loc v thn ca hai chng trnh con khc nhau, do vy thn mt ng gi cng cn phi gn. C php ca thn mt ng gi l: thn ng gi ::= package body tn n ca thn ng gi is phn m t thn ng gi end [tn n ca thn ng gi]; phn m t thn ng gi ::= {thnh phn m t thn ng gi} thnh phn m t thn ng gi ::= m t chng trnh con | m t kiu | m t kiu con | m t hng s | m t tn ph | mnh s dng Thn i vi ng gi data_types biu din trn c th vit li nh sau: package body data_types is constant vector_table_loc : address := X"FFFF00"; function data_to_int(value : data) return integer is


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body of data_to_int end data_to_int; function int_to_data(value : integer) return data is body of int_to_data end int_to_data; end data_types; Trong thn ng gi ny, gi tr i vi hng s c ch nh trc, v thn ng gi phi c gn trc. Cc m t kiu con khng c lp li, do cc m t ng gi l nhn thy c trong thn ng gi. 4.2.5.4. Thay th Tn v s dng ng gi Khi mt ng gi c m t, th cc thnh phn m t km vi n c th s dng bng cch ly tin t cc tn ca chng vi tn ng gi. Nh v d trong mc 3.2.5.3, cc thnh phn c m t c th s dng nh sau: variable PC : data_types.address; int_vector_loc := data_types.vector_table_loc + 4*int_level; offset := data_types.data_to_int(offset_reg); Thng thng thun tin c th tham chiu n cc tn t mt ng gi m khng cn c iu kin l mi khi s dng phi km vi tn ng gi. Vic ny c thc hin bng mnh Use (s dng) trong mt m t cc b. C php ca n nh sau: mnh s dng ::= use tn c chn { , tn c chn}; tn c chn ::= tin t . hu t Tc dng ca mnh use l cho tt c cc tn c lit k ri sau c th s dng m khng cn tin t ca chng. Nu tt c cc tn c m t trong mt ng gi u s dng cch ny, th ta c th dng mt hu t c bit l all, v d nh: use data_types.all; 4.3. M t cu trc ca VHDL


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Trong mc 4.1 tc gi gii thiu v mt s thut ng dng m t cu trc ca mt h thng s. Trong mc ny, tc gi s cp n vic m t h thng s bng ngn ng VHDL. 4.3.1. M t u vo Mt h thng s thng c thit k di dng kin trc kiu cc khi (module). Mi mt khi s c mt s cng vo/ra dng giao tip gia khi vi cc thnh phn bn ngoi. Trong VHDL, khi nim thc th (an entity) thc ra cng l mt khi thnh phn trong qu trnh thit k, m thng l n c thit k mc trn cng (top level) - cn gi l thc th. C php m t mt thc th nh sau: m_t_thc_th ::= entity tn_nh_danh is header_ca_thc_th phn_chnh_ca_thc_th [begin phn_khai_bo_ca_thc_th ] end [tn_ca_thc_th]; header_ca_thc_th ::= [mnh__nghi_thc_chung] [mnh__nghi_thc_cng] mnh__chung ::= generic (lit_k_c_im_chung); lit_k_c_im_chung ::= lit_k_giao_din_chung mnh__cng ::= port (lit_k_cng); lit_k_cng ::= lit_k_giao_din_cng phn_chnh_ca_thc_th ::= {cc_thnh_phn_ca_thc_th} Phn chnh ca thc th c th c s dng m t cc thnh phn s c dng trong qu trnh hot ng ca thc th. Thnh phn header ca thc th l thnh phn gn nh quan trng nht trong m t thc th. N c th cha cc thnh phn hng s chung (generic constant),


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c dng iu khin cu trc v hot ng ca thc th, cc cng (port), l cc knh thng tin vo v ra ca thc th. Cc hng s chung c ch nh s dng giao din lit k tng t nh vic m t mt chng trnh con. Tt c cc thnh phn con u phi l thuc lp hng s chung ny. Do vy, c php ch yu ca hng s giao tip (interface constant) c m t nh sau: m_t_hng_s_giao_tip ::= [constant] lit_k_nh_danh : [in] biu_din_kiu_con [ := biu_din_tnh] Gi tr thc i vi mi hng s chung c b qua khi thc th c s dng nh mt thnh phn ca qu trnh thit k. Cc cng (port) u vo cng c ch nh vic s dng trong giao din c lit k, nhng cc thnh phn trong danh sch lit k phi c phn vo lp tn hiu. C php l: m_t_tn_hiu_giao_tip ::= [signal] lit_k_nh_danh : [mode] biu_din_kiu_con [bus] [ := biu_din_tnh] Do gia cc lp phi c tn hiu nn t signal c b qua v coi nh l c sn. T bus c th c s dng nu cc cng c ni ti nhiu hn mt u ra. d hiu, chng ta xem xt v d sau: entity processor is generic (max_clock_freq : frequency := 30 MHz); port (clock : in bit; address : out integer; data : inout word_32; control : out proc_control; ready : in bit); end processor;


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Trong trng hp ny, hng s chung l max_clock_freq c s dng ch r tn s hot ng ca thc th. Vic m ho hot ng ca thc th s s dng gi tr ny xc nh tr trong qu trnh cc gi tr tn hiu thay i. Tip theo l v d v cc tham s chung c s dng ch nh lp ca cc u vo vi cu trc c th thay i c. V d: entity ROM is generic (width, depth : positive); port (enable : in bit; address : in bit_vector(depth1 downto 0); data : out bit_vector(width1 downto 0) ); end ROM; y hai hng s chung l width v depth c s dng ch nh s lng cc bit d liu v cc bit a ch tng ng cho ROM. Ch rng khng c gi tr mc nh cho trc i vi cc hng s ny. V d cui cng l m t thc th khng c hng s chung hay cng no: entity test_bench is end test_bench; Vic m t ny c biu din trong hnh 3.3. Thc th mc trn cng (toplevel) i vi vic thit k kim tra (Design under test - DUT) c s dng nh mt thnh phn trong mch kim tra chun vi mt thc th khc (TG).


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Hnh 4.3. S mch kim tra chun 4.3.2. M t kin trc Mi mt thc th c mt m t nh ngha ring, tuy nhin v hot ng th c th mi thc th c nhiu chng trnh khc nhau, do vy mi thc th cn c th c biu din dng cu trc chng trnh. Vic m t kin trc ny khc vi m t hot ng s c trnh by trong mc 3.4. Kin trc thn thc th c m t theo c php sau: kin_trc_thn ::= architecture tn_nh_danh of tn_u_vo is phn_chnh_ca_kin_trc begin phn_khai_bo_ca_kin_trc end [tn_ca_kin_trc] phn_chnh_ca_kin_trc ::= {cc_mc_chnh_trong_khi} phn_khai_bo_ca_kin_trc ::= {khai_bo_tng_tranh} cc_mc_chnh_trong_khi ::= m_t_chng_trnh_con | thn_chng_trnh_con | m_t_kiu | m_t_kiu_con | m_t_hng_s | m_t_tn_hiu | m_t_tn_hiu | m_t_tn_ph_(b_danh) | m_t_thnh_phn | c_im_cu_hnh | mnh__s_dng khai_bo_tng_tranh ::= khai_bo_khi


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| khai_bo_thuyt_minh_cc_thnh_phn 4.3.2.1. M t tn hiu Cc tn hiu c dng ni cc khi con vi nhau trong mt thit k. Chng c m t theo c php sau: m_t_tn_hiu ::= signal lit_k_tn_nh_danh : diu_din_kiu_con [loi_tn_hiu] [:= biu_din]; loi_tn_hiu ::= register | bus Mt im quan trng cn ch l cc cng ca mt i tng cn phi x l ng tn hiu cho i tng . 4.3.2.2. Cc khi (Block) Cc modul con trong kin trc khi chnh c th c biu din di dng cc khi. Mt khi l mt n v cu trc modul, vi giao din ring, c ni n cc khi khc hoc cc cng bng tn hiu. C php m t khi nh sau: khai_bo_khi ::= nhn_khi : block [(biu_din_bt_buc)] header_ca_khi phn_chnh_ca_khi begin phn_khai_bo_ca_khi end [nhn_khi]; header_ca_khi ::= [ mnh__chung [ nh_x_ca_mnh_; ]] [ mnh__cng [ nh_x_ca_cng; ]] nh_x_ca_mnh_ ::= generic map (danh_sch_tng_ng_cc_mnh_)


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nh_x_ca_cng ::= port map (danh_sch_tng_ng_cc_cng) phn_chnh_ca_khi ::= {cc_mc_chnh_ca_khi} phn_khai_bo_ca_khi ::= {khai_bo_tng_tranh} Biu din header ca khi cng tng t nh header ca u vo. Danh sch tng ng cc mnh ch nh cc gi tr i vi cc hng s chung. Danh sch tng ng cc cng ch nh cc tn hiu thc hoc cc cng t v ca khi hoc thn kin trc c ni n cc cng ca khi . V d v kin trc ca mt b vi x l trong v d 3.3.1 phn 3.3.1 c m t di dng kin trc trong v d di y. V d v kin trc c cu trc ca mt b vi x l: architecture block_structure of processor is type data_path_control is ; signal internal_control : data_path_control; begin control_unit : block port (clk : in bit; bus_control : out proc_control; bus_ready : in bit; control : out data_path_control); port map (clk => clock, bus_control => control, bus_ready => ready; control => internal_control); declarations for control_unit begin statements for control_unit end block control_unit; data_path : block port (address : out integer; data : inout word_32;


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control : in data_path_control); port map (address => address, data => data, control => internal_control); declarations for data_path begin statements for data_path end block data_path; end block_structure; 4.3.2.3. M t cc thnh phn (component) Thn kin trc cng c th s dng cc kiu m t u vo khc nhau c sn trong th vin. Do vy, kin trc cn phi dng m t mt thnh phn no . Sau , l t cu hnh cho vic s dng thnh phn . C php m t thnh phn nh sau: m t thnh phn ::= component tn nh danh [ mnh chung cc b ] [ mnh cng cc b ] end component; V d v cng NAND 3 u vo: component nand3 generic (Tpd : Time := 1 ns); port (a, b, c : in logic_level; y : out logic_level); end component; V d v m t thnh phn ca b ROM vi ln cc bit a ch v d liu ph thuc vo cc hng s chung: component read_only_memory generic (data_bits, addr_bits : positive); port (en : in bit;


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addr : in bit_vector(depth1 downto 0); data : out bit_vector(width1 downto 0) ); end component; 4.3.2.4. Thuyt minh thnh phn Sau khi m t mt thnh phn trong kin trc, chng ta c th m t thuyt minh v n theo c php sau: khai bo thuyt minh thnh phn ::= tn thnh phn [ nh x ca mnh ] [ nh x ca cng ] V d v thuyt minh thnh phn i vi cc m t thnh phn trong 2 v d v cng NAND v thnh phn ca ROM phn 3.3.2.3 nh sau: enable_gate: nand3 port map (a => en1, b => en2, c => int_req, y => interrupt); parameter_rom: read_only_memory generic map (data_bits => 16, addr_bits => 8); port map (en => rom_sel, data => param, addr => a(7 downto 0); 3.4. VHDL m t hot ng Trong mc 1.1.2, chng ta bt u cp n cc hot ng ca mt h thng s c th m t bng ngn ng lp trnh. Trong phn ny, chng ta s m t hot ng ca mt h thng s bao gm cc khai bo dnh cho vic thay i gi tr tn hiu, ng thi l phn ng ca h thng cng thay i theo. 4.4.1. Ch nh tn hiu Vic ch nh tn hiu thc hin mt hoc nhiu giao tc n tn hiu (hoc n cng). C php ca vic ch nh tn hiu l: khai bo ch inh tn hiu ::= ch n inv_ff0, q => ff1); q0 q0, q1 => q1); clock_driver : process begin clock digit_out(i)); port map(i => pb_in(i), o => pb(i));


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elsif clk50'event and clk50 = '1' then if hertz_en = '1' then point x"00005c005d0d000000003d5b00270000002d703b6c2f2e000039306f696b2c00", -- 3F - 20 -- 5F - 40


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INIT_03 => x"0000000000000000001b000000007f0000000000000000000008000000000000",

-- 7F - 60

INIT_04 => x"00325741535a00000031510000000000007e0900000000000000000000000000", -- 9F - 80 INIT_05 => x"003837554a4d00000036594748424e0000355254465620000033344544584300", -- BF - A0 INIT_06 => x"00005c005d0d000000003d5b00270000002d503b4c2f2e000039304f494b2c00", -- DF - C0 INIT_07 => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- FF - E0 INIT_08 => x"00405741535a00000021510000000000007e0900000000000000000000000000", -- 1F - 00 INIT_09 => x"002a26554a4d0000005e594748424e0000255254465620000023244544584300", -- 3F - 20 INIT_0A => x"00007c007d0d000000002b7b00220000005f503a4c3f3e000028294f494b3c00", -- 5F - 40 INIT_0B => x"0000000000000000001b000000007f0000000000000000000008000000000000", -- 7F - 60 INIT_0C => x"00407761737a0000002171000000000000600900000000000000000000000000", -- 9F - 80 INIT_0D => x"002a26756a6d0000005e796768626e0000257274667620000023246564786300", -- BF - A0 INIT_0E => x"00007c007d0d000000002b7b00220000005f703a6c3f3e000028296f696b3c00", INIT_0F => x"0000000000000000001b000000007f0000000000000000000008000000000000" ) -- DF - C0 -- FF - E0

port map ( clk => clk, en => cs, we => we, rst => rst, addr => addr, di => wdata, do => rdata); my_ram_512 : process ( rw ) begin we clk; Reset =>reset; Clkout=>ps2_clk); my_key_map : key_b4 Port map ( clk => clk, rst => reset, cs => '1', rw => '1', addr => shift_key_plus_code, rdata => ascii, wdata => "00000000" ); --x l vi hai tn hiu ps2_clk_hi_z, ps2_data_hi_z to ra tr khng cao nhm khng cho truyn d liu khi c nhiu phm c n.


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ps2_direction : process( ps2_clk_hi_z, ps2_data_hi_z ) begin if( ps2_clk_hi_z = '1' ) then ps2_clk

94747528-VHDL (1)

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