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赛灵思中国通讯53期:为何使用Zynq SoC可以让企业产品利润激增
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Transcript of 赛灵思中国通讯53期:为何使用Zynq SoC可以让企业产品利润激增
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18
X i l i n x News 2 0 1 4 I s s u e 5 3 S u m m e r 2 0 1 4
china.xilinx.com/xcell
Zynq SoC
Virtex UltraScale FPGA Tb
DDR
Vivado HLS
Vivado 2014.2
FPGA
-
All Programmable
ICASICICASSP SoCASICASIC
QuicklogicCEO Tom Hart
ASIC
ASIC
IP(SoC)SoC
AS-
SPASSP
ASSP
ASSP
ASSPASSP
ASSP
ASSP
IPASICASSPASSP
Zynq-7000 All Programmable SoC
Zynq SoC
Mike Santarini
/
2014 Xilinx, Inc
4 2014
-
3018
24
All Programmable... 4
XCELLENCE BY DESIGNAPPLICATION FEATURES
FPGA 18
UltraScale
Virtex UltraScale FPGA Tb24
DDR 30
8 Zynq SoC
6 2014
-
XTRA READING Vivado 2014.2 62
66
38
52
44
Excellence in Magazine & Journal Writing2010, 2011
Excellence in Magazine & Journal Design2010, 2011, 2012
2 0 1 4
THE XILINX XPERIENCE FEATURES
FPGA 101
MTBF38
Vivado HLS 44
FPGA52
NI 58
6 2014 2014 7
-
Zynq SoC
Mike Santarini [email protected]
8 2014
-
Zynq Soc
2011 Zynq-7000 All
Programmable SoC
Zynq SoC
Zynq SoC
Zynq SoC ARM
Cortex -A9 MPCore
Zynq SoC
Zynq SoC
ASIC ASSP ASSP+FPGA
Zynq
SoC
2014 9
-
500
450
400
350
300
250
200
150
100
50
0
Cos
t ($
M)
65nm(354M)
45/40nm(615M)
28nm(1.044M)
20nm(1.317M)
Feature Dimension (Transistor Count)
16/14nm(1.636M)
Physical
Verification
IP qualification
500
450
400
350
300
250
200
150
100
50
0
Cos
t ($
M)
65nm(90M)
45/40nm(130M)
28nm(180M)
20nm(240M)
Feature Dimension (Transistor Count)
16/14nm(310M)
Architecture
Prototype
Software
Validation
Physical
Validation
Prototype
Verification
Architecture
IP qualification
1 IC 10
5,000
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IBS2013/2014
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2013 IC
28nm
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10 2014
-
2
$140
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[ ]
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-
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169
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12 2014
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28nmASIC
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10 13
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SoC
12 2014 2014 13
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14 2014
-
[zor!TpD $1300 $23 $195.00 $73.67 2.54291& $1040 $9.2 $156.00 $69.78 6.02361& $650 $9.2 $97.50 $39.55 3.41
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5 NPVZynq SoCASIC
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Zynq SoC
ASIC 20%
Zynq SoC NPV
1.0727 PI 3.7
ASIC 1285 NPV
0.1 PI 20%
Zynq SoC NPV PI
5
Zynq SoC
60%
20% Zynq
SoC
80% ASIC
Zynq SoC NPV 9,666
PI 8.33 ASIC
NPV 7,478PI 2.14
Zynq SoC
50% NPV
5,634PI 4.86
ASIC
A S I C
20%
15% - Zynq SoC
Zynq SoC
Zynq SoC
15%
Zynq SoC NPV 7367
PI 2.45 ASIC
1,285 NPV 0.1 PI
ASIC
20%
Zynq SoC
80%10.4
Zynq SoC 23
Zynq SoC
NPV
6978PI 6.02
ASIC 7478
NPV 15% Zynq
SoC PI ASIC
2.14 PI ASIC
20%
Zynq SoC
50% Zynq SoC
3955 NPV
I P 3 . 4 1
ASIC 0.98 PI
Zynq SoC PI
Zynq SoC
14 2014 2014 15
-
Zynq SoC
Mike Santarini
Zynq SoC
James Smith Zynq
Zynq SoC
2011 11
Zynq SoC
2013 (NI)
Zynq SoC
CompactRIO-9068
myRIO
FIRST
roboRIO
Smith 10NI
FPGA
Zynq SoC NI RIO
NI CompactRIO
Chris Rake Zynq SoC
Zynq
7
DSP
Rake
[DMA] DMA
DMA
Rake
FPGARake
Zynq
Rake
Zynq
SoCRake Zynq
ARM A9
A9 ASSP
Rake
NI Zynq-7020
LabVIEW RTOS NI Linux
Rake
NI
NI
Rake
Zynq SoC
Zynq
Zynq NI
Rake
2014 1
Zynq SoC
58
Smith
Zynq
SoC
2013NI
cRIO-9068 sbRIO
myRIO
Smith
60%
30%
ASIC
16 2014
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Automotive AdaptiveCruise Control ECU
Derivatives ofderivatives
Car Co. A Car Co. C
Initial product
Derivative product
Base platform with greatestpotential for scalability Longer development time High initial design cost
Expand to multiple customers Fast development time Low design cost (design reuse) High profitability
Expand to multiple productlines - luxury to economy for each customer Fast development time Lowest design cost Highest profitability
Luxury car
SUV
Sports car
Trucks
Economy
Luxury car
SUV
Sports car
Trucks
Economy
Luxury car
SUV
Sports car
Trucks
Economy
Car Co. B
3 Zynq SoC
20% ASIC
15% Zynq SoC Zynq
SoC
Zynq SoC
ZYNQ SOC
Zynq SoC
ECU
Zynq SoC
Zynq SoC
IP
ECU
/
3 Zynq SoC
ECU
Zynq SoC
Zynq SoC
Zynq-7000 All Programmable SoC
ARM
FPGA
I/OZynq SoC
Zynq SoC
Zynq SoC
http://china.
xilinx.com/products/silicon-devices/
soc/zynq-7000/index.htm
16 2014 2014 17
-
FPGA
Steve [email protected]
18 2014
-
FPGA
3 17
BICEP2
CMB B
CMB
1
TES
E B
Virtex-4 FPGA DFMUX
Kintex-7
Kintex
CMB B
CMB
2.73K B 1K
E
B
CMB
B
10
SPT SPTSBTpol
2013 CMB
B 1SPT BICEP2
BICEP3 CMB
-
2014 19
-
BR
AD
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D B
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C M B
1964
Holmdel
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150GHz CMB
NIST
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150GHz TES
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90GHz CMB
90GHz
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PdAu
/
TES 2
150GHz 90GHz
TES Hz
1536
TES
1536768
TES
1 -
20 2014
-
SQUID 1536
SQUID
Virtex-4
FPGA
DFMUX
SQUID
SQUID
DFMUX
/
-
NIST
S P T p o l
Virtex-4 FPGA McGill
DFMUXFPGA
DDS
12
12 TES
LC 12
TES
CMB
0.1Hz~20Hz TES
12 TES
DDS
SQUID
SQUID
FPGA
3
A D C
Virtex-4 FPGA
GSM
/DUC/DDC
TES
Hz
Virtex-4 FPGA
TES
Virtex-4 FPGA
SPTpol 12
4
DFMUX Virtex-4 FPGA
DSP
FPGA
FPGA
FPGA
FPGA
DMFS
DMFD
DMFS
BR
AD
FOR
D B
ENSO
N
2 7150GHz 90GHz
2TES
20 2014 2014 21
-
Carrier Comb Generator
Nuller Comb Generator
Sub-Kelvin Stage
Mezzanine CardDFMUX Motherboard
4K Stage
Bo
lom
eter
1
Bo
lom
eter
12
Room-Temperature Electronics
Virtex-4 FPGA
3 CMBDFMUXTES
20MHz
16 25Msps
DAC
DDS 11 2
0.006Hz
25Msps 14
FPGA
CIC CIC
28 128
17
D F M U X 8
25Msps
200MHz CIC1CIC1
28 24
CIC1
CIC2CIC2 6
163264128256
512CIC2 152
FIR
FIR
SDRAM
FPGA Micro- Blaze
Linux
MMU
Linux OS
MicroBlaze
Web HTTP
DFMUX
DFMUX
WebPython
DFMUX
SPTpol CMB
DFMUX EBEX
E B
Huan Tran
CMB
Kintex-7
FPGA ICEboard DFMUX
CMB
CHIME
CHIME
5
10020
22 2014
-
CHIME
C H I M E
CMB
70~110 3D
21400~800MHz
CHIME
BAO
BAO
4.9
BAO
CHIME
2D
CHIME
160 Kintex-7 FPGA
Tbps BAO
10-35
CMB
CGB CGB CMB
BECEP2
SPTpolEBEX
BICEP3
CHIME
SPTpol TES FPGA DFMUX
J . E. Austermann S P T p o l C M B arXiv:1210.4970v1 [astro-ph.IM]
Ron Cowen2014 3 17
Matt Dobbsmm arXiv:0708.2762v1 [physics. ins-det]
M.A. Dobbs arXiv:1112.4215v2 [astro- ph.IM]
J. W. Henning SPTpol CMB150GHz TESarXiv:1210.4969v1 [astro- ph.IM]
J. T. SayreSPTpol 9 0 G H z T E SarXiv:1210.4968v1 [astro-ph.IM]
Graeme Smecher ACM SIGBED LinuxEWiLi 20122012 6 2 9
Graeme Smecher Kilopixel TES
arXiv:1008.4587 [astro- ph.IM]
K. Story arXiv:1210.4966v1 [astro-ph.IM]
Xilinx20145G
2014 8 11
All Programmable
(NASDAQ: XLNX)
2014
5G
Sunil Kar 5G
5G
2014
2014 8 14 -15
5G
5G
All Programmable
SoC 20nm
Zynq-7000Kintex
UltraScale 5G
All Programmable
SoC 3D IC
IP
: http://china.xilinx.com/
22 2014 2014 23
-
U LT R A S C A L E
Virtex UltraScale FPGA Tb
Romi [email protected]
Frank [email protected]
24 2014
-
TVirtex UltraScale FPGA Tb UltraScale 28 Gbps 1 Tbps
I E E E
2015 1Tbps
2020 10 Tbps
2012
150
OTN
2015
100G 400G2020
400G 1T
Virtex UltraScale All
Programmable FPGA FPGA
1Tbps
Virtex UltraScale
1Tb
25G/28G
Virtex UltraScale
25G/28G
1Tbps
2014 25
U L T R A S C A L E
-
2 A 1 Tbps25G 1 Tb
2U40*25G/28
36H039H!
40 25G/28
GTY
Bridging
PCS
FEC
GTY/GTH
GTY/GTH
GTY
PCS
FEC
MAC
GTY
Bridging
PCS
FEC
GTY/GTH
GTY/GTH
GTY
PCS
FEC
MAC
3 A 1TbOTN 25G/28GOTN
-
All Programmable SoC
db (B
ackp
lane
_25G
_Los
s)db
(Bac
kpla
ne_1
0G_L
oss)
m4freq = 12.50GHzdB (Backplane_25G_Loss = 24.573
m5freq = 5.000GHzdB (Backplane_10G_Loss = 26.070
m4
freq, GHz0 2 4 6 8 10 12 14 16 18 20 22 24 26
0
20
40
60
80
m5
5 25G10G
I(Next) = I(Cm) + I(Lm) while I(Fext)
= I(Cm) I(Lm).
NEXTFEXT
IL
Megatron-6
0.004 5 1
1
0.35010G
3
0.350
40
100 25G
7
0.350 16
5 10G
2 5 G
10G
Vi r t e x U l -
traScale
25G/28G 1Tbps
1Tbps
25G/28G
Xilinx400GE
2014 6 18
400GE
400GE FPGA
400GE
400GE
400GE
400GE 400GE
400GE
400GE
400GE
400GE
400G
400GE
400GE 1-3
400GE
400GE
400G
Hemant
Dhulla , 400GE
28nm Virtex-7 H870T FPGA
400GE
Virtex
UltraScale 400GE
400GE
28 2014
U L T R A S C A L E
-
All Programmable SoC
28 2014
-
DDRTamara I. Schmitz
30 2014
-
90% DDR DDR4 DDR DDR4
DDR
DDR4
90%
1
DDR3
DDR4
D D R 3
D D R 4
LPDDR3/4
(HMC)
DRAM
DDR
DDR LPDDR
2
DRAM
D D R 3 D R A M
70%
2009 2010
40%DDR4
DRAM
LPDDR LPDDR
DDR4
DDR4
2014 31
-
DDR3 PC
PC DRAM
70% PC
DDR4
DDR4
DDR4
DDR5
MP3
10,000
12013 Vivado Memory Interface Generator (MIG)
2DRAMLPDDRDRAM
32 2014
-
ULTRASCALE
UltraScale FPGA DDR4
2,400 Mbps Agilent
DDR4
(POD) I/O UltraScale POD I/O 1.2V DDR4
I/O DDR3 35%
DDR3 DDR4UltraScale LPDDR3RLDRAM3QDRII+
QDRIVUltraScale HMC MoSys Bandwidth Engine 120
UltraScale FPGA I/O Bank
Bank I/O I/O Bank PLL 5
I/O Bank 4 13 I/O
4 DIMM 4 4
UltraScale FPGAMIG IP Vivado
Tamara I. Schmitz
UltraScale
FPGA
(TSV)
DDR
DDR3
32 2014 2014 33
-
DDR4
DDR
FPGA
FPGA FPGA
DDR4 FPGA
DDR5
DDR3
DDR4 DDR3
DDR4 DDR3
PC DDR4
DDR5
DDR3 DDR4
LPDDR4LP
Low-Power DDR4
LPDDR
LPDDR4
DDR
DDR I/O
LPDDR4 DDR
6 9
LPDDR
10 15
6 9
10 15
LPDDR
LPDDR
3
FPGA
CT
3LPDDR4HMC
34 2014
-
4TSV
LPDDR
I/O
FPGA
15 Gb HMC
30 Gbps
HMC
DDR DRAM
(HMC) (HMC Consortium)
4
HMC
HMCHMC
HMC MoSys
Bandwidth Engine SRAM
TCAM
(HBM)
TSV DRAM
HMC DDR3 DDR4
HMC TSV
4 8 DRAM 2G 4G
8
1 4
256
16 8
15 Gbps
DDR
1 (DDR3/DDR4/
HMC) 60 GbpsHMC
8
5
FPGA
1/20HMC
34 2014 2014 35
-
4TSV
5 2x100GEDDR3HMC
2/3
HMC DDR4
HMC
MoSys Bandwidth Engine
TCAM Intel HBM
MoSys Bandwidth EngineBE2
SRAM DRAM
16 Gbps
BE2 DDR
72
QDR RLDRAM
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TCAM
TCAM
TCAM
HBM HMC HBM
HBM
160Gbps
DDR3 DDR4 HMC 715 592 70 8,250 mm2 6,600 mm2 378 mm2
+FPGA 49 pJ/bit 34 pJ/bit 36 pJ/bit
18 MB/pin 29 MB/pin 857 MB/pin
36 2014
-
HBM
HBM
MoSys BE2HMC
LPDDR4 HBM
HBM
HBM
DDR3 DDR4
DDR4
DDR3
LPDDR4
DDR4
/
HMC DDR Bandwidth Engine
QDR RLDRAM
XilinxPico Computing15Gb/s HMCAll Programmable UltraScale
2014 6 24 All Programmable Xilinx, Inc.
(NASDAQ:XLNX)HMCC Pico Computing
All Programmable UltraScale 15Gb/sHMC UltraScale
64 HMC 15Gb/sPico Computing HMC IP
15Gb/s HMC
HMC
HMCC HMC
Tamara Schmitz 20nm
FPGA IP 15Gb/s HMCUltraScale FPGA HMC
Pico Computing HMC
HMC
Pico Computing CEO Jaime CumminsPico Computing HMC IP
UltraScale HMC UltraScale
36 2014 2014 37
-
F P G A 1 0 1
MTBF
38 2014
-
Adam P. Taylor [email protected]
(MTBF)
/
FPGA
2014
UG116
MTBF
MTBF
MTBF
MTBF
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HDBK-217F Bell-core/Telcordia
SR332MTBF FIT
1
38 2014 2014 39
F P G A 1 0 1
-
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FailureRate
1/MTBF
Wear OutTime
Constant Failure Rate
1 -
MTBF
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()
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MTBF
0.37 2
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/
MTBF
0.99 MTBF
4,361,048 497
MTBF
40 2014
F P G A 1 0 1
-
2 - MTBF0.37
1/2 MTBF P (s) - 0.6
One MTBF P (s) - 0.37
Time (years)
Pro
bab
ility
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
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Success Probability
1/2 MTBF P (s) - 0.6
One MTBF P (s) - 0.37
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
00 0.5 1 1.5 2 2.5 3
Success Probability
MTBF
MTBF
ECSS-Q-30-11A
NAVSEA TE000-AB-GTP-010
QML Q IC
QML V IC
1
40 2014 2014 41
F P G A 1 0 1
-
! ! ! ! NJM.QSG.49646! RNM!R!)C*! RNM!W!)T*! NJM.QSG.49647! I!! L!! NJM.QSG.2:611! KBO!UYW! KBO!T
! ! ! ! ! tvcsfhvmbufe! ! 0! ! DSD!
Prime Connector
Single Interface
Redundant Connector
Single Interface
Prime Connector
Module 1 Module 2
Module 1 Module 2
1 - IC
2 -
3 -
( B E R
ECC)
2
flash
FRAM
(elapsed-time counter)
42 2014
F P G A 1 0 1
-
ARM
ACK
ACK
FIRE
! ! ! !
Parity X
N of M X
CRC X BCH X X Hamming X X FEDReed Solomon X X CDI
4 -
3 - EDAC
3
MIL-STD 38999
/
4
(NACK)
(ACK)
NACK
(EMI)
3
Xilinx
2014 5 27
Multicore Association
All Programmable
Xilinx,
Inc. (NASDAQ:XLNX)
Markus Levy
25
SHIM MCAPI
Tomas
Evensen
Zynq-7000 All Programmable SoC
42 2014 2014 43
F P G A 1 0 1
-
Vivado HLS
Kimon [email protected]
James [email protected]
44 2014
-
Vivado HLS
RTL
FPGA
FPGA
HLS
HLS
Vivado
HLS
Vivado HLS
ARP/ICMP
pingARP
IP
Vivado HLS
Vivado HLS
Vivado HLS
Vivado HLS
C/C++
RTL
Vivado HLS
2014 45
-
1
FIFOHLS
Vivado HLS C++
RTL
Vivado HLS FIFO
Block RAM
RAM C
Vivado HLS FIFO
AXI4-Stream
Vivado HLS
Vivado HLS
GUI Tcl
FIFO
C RTL Vivado HLS
C
C/C++ C/C++
C/RTLVivado
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RTL
Vivado HLS
Vivado HLS
Vivado SDNet
52 RTL
Vivado SDnet
RTL Vivado HLS
DCM
Vivado HLS
Vivado HLSVivado HLS
C/C++
1
Vivado HLS
46 2014
-
1 Vivado HLS
1 void topLevelModule(stream &inData, stream &outData) {2 #pragma HLS dataflow interval=13 4 #pragma INTERFACE axis port=inData5 #pragma INTERFACE axis port=outData6 7 static stream modOne2modTwo;8 static stream modTwo2modThree;9 10 moduleOne(inData, modOne2modTwo);11 moduleTwo(modOne2modTwo, modTwo2modThree);12 moduleThree(modTwo2modThree, outData);13 }
1
streamVivado HLS
HLS
FIFO
C++
axiWordStruct 2
2 C++
struct axiWord { ap_uint data; ap_uint strb; ap_uint last;};
s t r u c t A X I 4 - S t r e a m
Vivado HLS
pragma
1 4
5 Vivado HLS
AXI4-Stream
AXI4-Stream I/F
Vivado HLS AX4 I/F
AXI4-Stream I/F Vivado
HLS
AXI4-StreamVivado HLS
AXI4-Stream
7 8
Vivado HLS
ap_uint
64 I/F
C/C++
2
Vivado HLS
internal
IIII Vivado
HLS
>1 II=2
Vivado
HLS RTL
II=1
Vivado HLS
46 2014 2014 47
-
II Vivado HLS
modOne2modTwo
3
inData
validBuffer
1outData
Vivado HLS
Vivado HLS
ap_uint
2 Vivado HLS
1II=1
Vivado HLS
3 Vivado HLS
1 void dropper(stream& inData, stream& validBuffer, stream& outData) {
2 #pragma HLS pipeline II=1 enable_flush34 static enum dState {D_IDLE = 0, D_STREAM, D_DROP} dropState;
5 axiWord currWord = {0, 0, 0, 0};
67 switch(dropState) {8 case D_IDLE:9 if (!validBuffer.empty() && !inData.empty()) {10 ap_uint valid = validBuffer.read();11 inData.read(currWord);12 if (valid) {13 outData.write(currWord);14 dropState = D_STREAM;15 }16 }17 else18 dropState = D_DROP;19 break;20 case D_STREAM:21 if (!inData.empty()) {22 inData.read(currWord);23 outData.write(currWord);24 if (currWord.last)25 dropState = D_IDLE;26 }27 break;28 case D_DROP:29 if (!inData.empty()) {30 inData.read(currWord);31 if (currWord.last)32 dropState = D_IDLE;33 }34 break;35 }36 }
4
FSM
ap_unit 5
axiWord
7
if-else
Vivado HLS
RTL
48 2014
-
D_IDLE FSM 10
11
Vivado HLS
4
4
1 void merge(stream inData[NUM_MERGE_STREAMS], stream &outData) {
2 #pragma HLS INLINE off3 #pragma HLS pipeline II=1 enable_flush45 static enum mState{M_IDLE = 0, M_STREAM} mergeState;
6 static ap_uint rrCtr = 0;
7 static ap_uint streamSource = 0;
8 axiWord inputWord = {0, 0, 0, 0};910 switch(mergeState) {11 case M_IDLE:12 bool streamEmpty[NUM_MERGE_STREAMS];13 #pragma HLS ARRAY_PARTITION variable=stream-
Empty complete14 for (uint8_t i=0;i
-
2 3 4
2 -
5 MAC
1 if (!inData.empty()) {2 inData.read(currWord);3 switch(wordCount) { 4 case 0: 5 MAC_DST = currWord.data.range(47, 0); 6 MAC_SRC.range(15, 0) = currWord.
data.range(63, 48); 7 break; 8 case 1:9 MAC_SRC.range(47 ,16) = currWord.
data.range(31, 0); 10 break;11 case 2:12
5
MAC
inData 64
2
5 MAC 16
MAC_SRCMAC
32 MAC_SRC
32
Vivado HLS
2
INLINE
6
6Vivado HLS
1 void module2(stream &inData, stream &outData) {
2 #pragma HLS INLINE3 4
Vivado HLS 3
Vivado HLS
RTL
50 2014
-
2 3 4
3 - Vivado HLS
7 CAM
ARP
noOfArpTableEntriesarpTableEntry
MAC IP
7CAM
1 class cam {2 private:3 arpTableEntry filterEntries[noOfArpTableEn-
tries];4 public:5 cam();6 bool write(arpTableEntry writeEntry);7 bool clear(ap_uint clearAddress);8 arpTableEntry compare(ap_uint
searchAddress);9 };
IPMAC
for
IP
II=1
8 CAM
1 arpTableEntry cam::compare(ap_uint searchAddress) {
2 for (uint8_t i=0;ifilterEntries[i].valid == 1 &&
searchAddress == this->filterEntries[i].ipAddress)
4 return this->filterEntries[i];5 }6 arpTableEntry temp = {0, 0, 0};7 return temp;8 }
Vivado
HLS
RTL
10GBps
RTL Vivado HLS C/C++
FPGA
C
FIFO
HLS
ping ARP IP
ARP Vivado HLS
10Gbp
50 2014 2014 51
-
FPGA
52 2014
-
FPGA
Angela Sutton [email protected]
Paul Owens FPGA [email protected]
FPGA
FPGA
Synopsys Synplify Premier
FPGA
RTL
(QoR)
Vivado
2014 53
-
###==== BEGIN Clocks {Populated from tab in SCOPE, do not edit)create_clock name {clock} [get_ports {p:clock}] period 10 waveform {0 5.0}###==== END Clocks - {Populated from tab in SCOPE, do not edit)###==== BEGIN Inputs/Outputs - {Populated from tab in SCOPE, do not edit)set_input_delay {p:porta[7:0]} 1 clock {c:clock} add_delayset_input_delay {p:portb[7:0]} 1 clock {c:clock} add_delayset_output_delay {p:porto[7:0]} .5 clock {c:clock} add_delay###==== END Inputs/Outputs - {Populated from tab in SCOPE, do not edit)###==== BEGIN Registers - {Populated from tab in SCOPE, do not edit)set_clock_groups disable asynchronous name {clock_group} group {clock} comment {Source clock clock group}
1.
2.
3.
4.
5.
(define_path_delay, define_
false_path)
Vivado
Synplify TCL
FDC
TCL: create_fdc_template
1
(.fdc)
/
Vivado
Vivado
Vivado
ISE BUFG
Synplify
get_XX all_XX
1SynplifyI/OVivado
54 2014
-
Tcl check_fdc_
query
Synplify Premier
set_option fast_synthesis 1
/ I/O
I/O
Synplify
TCL
TCL: project -run constraint_check
2
Synplify
I/O
RTL
RAMS /
DSP
QoR FPGA
RAMS /
DSP
Synplify
SynCore IP
RAM RTL
IP IP
CatalogSynopsys Synphony Model
Compiler Synopsys Design Ware
coreTools DesignWare Building
Blocks IP
DSP
RTL
2QoR
54 2014 2014 55
-
3
combina t iona l -
always
RAM
RAM
RAM
R A M
RAM RAM
(syn_ramstyle for Synplify
software)
RAM
RAM
DSP
DSP
(syn_ dspstyle for Synplify
in Vivado Design Suite ows)
DSP
SRL
select_SRL Xilinx SRL
Synplify
select_
srl QoR
syn_srl SRL
RTL
(PLL)
PLL
PLL
Synplify HDL Analyst
3
RTL
Vivado
QoR
R T L
56 2014
-
5
4
Synplify
Vivado
SLR
Virtex-7 2000T FPGA
SLR
4Synplify
TCL
(report_timing)
QoR
Synplify Premier
FDC
set_clock_route_delay {c:clka} 1.4
QoR
5
Vivado
RTL
http://www.synopsys.com/ fpga
56 2014 2014 57
-
NI
Eric Myers
Zynq SoC NI SOM
58 2014
-
1 Zynq SoCNI sbRIO-9651
UBM
2013
57%
(SOM) IHS2012
SOM 2010
2016 17.5%
9.3%
SOM
Zynq-7000 All Programmable SoC
OS
SOM
I/O
NI sbRIO-9651
SOM 1
FPGA
(HDL)
NI SOM Zynq-7020
SoC RAM
P C B
2Zynq SoC 667MHz
ARM Cortex -A9
Artix-7 FPGA
MTBF
NI
2014 59
-
2 NI SOMZynq SoC
Specications
Processor SoC
Xilinx Zynq-7020667-MHz Dual-Core ARM Cortex-A9Artix-7 FPGA Fabric
Size and Power
50.8 mm x 78.2 mm (2 in. x 3 in.)Typical Power: 3 W to 5 W
Dedicated Processor I/O
Gigabit Ethernet, USB 2.0 Host, USB 2.0Host/Device, SDHC, RS232
Memory
Nonvolatile: 512 MBDRAM: 512 MB
Operating Temperature
-40 C to 85 C Local Ambient
FPGA I/O
160 FPGA I/O PinsCongurable Peripherals: Gigabit Ethernet,RS232 x3, RS485 x2, CAN x2
CompactRIO
NI
SOM
x2USB
USBSDRS-232x2RS-
485CAN
I/O PMOD
I/O
PMOD
NI SOM
(BSP) NI
Linux Real-Time
3
USB
FPGA
NI Linux Real- Time
(OS) Linux
Linux
NI
Linux Real-Time C/
C++ Lab-VIEW Real-Time
FPGA
UBM2013
60%
OS
NI SOM
NI SOM
BSP
OS
I/O
FPGA
FPGA
Zynq SoC
NI LabVIEW
FPGA
IPLabVIEW FPGA
Lab-VIEW
I/O
HDL
LabVIEW FPGA NI
IP
HDL
IP Integration Node
DMA
FPGA
COMPACTRIO
I/O
CompactRIO NI
SOM
CompactRIO NI SOM
LabVIEW RIO
60 2014
-
Application Software 1,000 GraphicalProgramming Functions
Easy-to-Use I/OAPI Libraries
Prebuilt Thread-Safe,Low-Level Drivers
NI Linux Real-Time
Ready to RunOut of the Box
Industry-Leading Silicon
LabVIEW and Middleware
Driver API
Device Drivers
Operating System
Board Support Package (BSP)
NI RIO Embedded Hardware(CompactRIO, NI Single-Board RIO)
3 NI SOM(BSP) NI Linux Real-Time
FPGA
I/O
CompactRIO
100 C I/O
NI SOM
I/O
NI SOM
BSP RAM
FPGA
NI SOM
NI SOM
NI SOM
Optimedica
NI
SOM
Optimedica
Mike Wiltberger NI SOM
ni.com/som
Xilinx 2014 EDN
1 0
2005
2 0 1 4 7 1 -
A l l P r o g r a m m a b l e
Xi l inx , I nc .
(NASDAQ:XLNX) 2014
EDN
SoC (All Programmable
SoC)
2005 2014 EDN-China 10
10
Zynq
2014 6 26
10
EDN-China
EDN-China
EDN-China
All Programmable
1 0
2005 2014
"EDN China "
2006
13
Virtex FPGA, Kintex-7 FPGA,
ISEVivado
Zynq-7000 All Programmable SoC
60 2014 2014 61
-
62 2014
Vivado 2014.2
IP
All ProgrammableIPVivadoVivado
china.xilinx.com/vivado
Vivado2014.2 china.xilinx.com/download
VIVADO2014.2
Vivado2014.2Virtex UltraScale
Artix-7QXQ7A50T Zynq-7000 SoCXQ7Z045RF900 XA Zynq-7000 SoCXA7Z030FBG484
Virtex UltraScaleXCVU065XCVU080XCVU095XCVU125
Kintex UltraScale SSIXCKU100XCKU115 Virtex UltraScaleXCVU160XCVU440
VIVADO
Artix-7 7A50T 7A35T
PCIe IP Zynq SoC 7Z100
PCI Express IP PG054 Gen2 PCIe IP PG023Gen3 PCIe IP
Vivado IP Vivado IP Integrator DRC validate_bd_design
Vivado
2013.4
(WNS)2014.1
VIVADO
DSP
Waveform Viewer
-
62 2014 2014 63
90% 50% FFT IP 80%
MCode MultAdd 90% WinPCap 4.1.3 Windows 8.1
Vivado 2014.2
ULTRAFAST
UltraFast
Vivado
UltraFast UltraScale
DRC
IP IPI
Vivado HLS
TCL
(Tcl)
Tcl
Tcl Tcl Vivado
Tcl Tcl
Tcl
(EDA)
linting TclVivado (IDE)
Tclapp app Vivado
Tcl QuickTake
VIVADOVivado Vivado
Tcl Vivado IP IP Integrator
VIVADO
Vivado china.xilinx.com/training
-
64 2014
XAPP1206NEONZYNQ-7000 AP SOC http://china.xilinx.com/support/documentation/application_notes/xapp1206-boost-sw-performance-zynq7soc-w-neon.pdf
CPU
CPU(SIMD)
CPU
NEONZynq-7000 All Programmable SoC
ARM Cortex-A9SIMD
NEON
Haoliang Qin
Cortex-A9NEON
NEON
intrinsicsNEON
CPU
Qin
XAPP1208BITSLIP http://china.xilinx.com/support/documentation/application_notes/xapp1208-bitslip-logic.pdf
UltraScaleI/OI/O
I/O
UltraScaleI/O
I/O
7Virtex-6 FPGAI/O
Bitslip
Marc Defossez
UltraScaleBitslip
Bitslip
Bitslip7 Virtex-6 FPGA
ISERDESBitslip
7 Virtex-6 FPGA
7Virtex-6 FPGA
Bitslip
Bitslip
XAPP1203ZYNQ-7000 AP SOCIPXADC http://china.xilinx.com/support/documentation/application_notes/xapp1203-post-proc-ip-zynq-xadc.pdf
All Programmable
(WP442)
All
ProgrammableFPGAAll Programmable SoC
FPGA
. . .
-
64 2014 2014 65
Mrinal J. SarmahCathal
Murphy
Zynq-7000 All Programmable SoCIP
DSPAXI
IP
XADCVivado IP Integrator
RTL
XAPP1205ZYNQ-7000 ALL PROGRAMMABLE SOCIP INTEGRATOR http://china.xilinx.com/support/documentation/application_notes/xapp1205-high-performance-video-zynq.pdf
Zynq-7000 All Programmable SoC
(PS)
James LuceroBob Slous
Zynq SoC
(PL)AXIARM
Cortex-A9.
PLAXI
Zynq-7000 SoC
(HP)Zynq SoCHP
6432AXI3
AXI(VDMA)
844
1920 x 1080p60Hz
24AXIDMA
(VTC)
(TPG)AXIDMA
(OSD)
HDMI
IP
AXI
4AXIDMAAXI4HP
Cortex-A970%
Zynq SoC ZC702
XAPP1091KINTEX-7 FPGA2.0 http://china.xilinx.com/support/documentation/application_notes/xapp1091-k7-RTV-Engine-2-0.pdf
(FHD)LCD
NTSC/PAL
Kintex-7 FPGA
/
Bob FengKavoos Hedayati
XAPP1095ZYNQ-7000 ALL PROGRAMMA-BLE SOC2.1 http://china.xilinx.com/support/documentation/application_notes/xapp1095-zynq-rtve.pdf
Zynq-
7000 All Programmable SoC
/
Bob Feng
2.1(RTVE 2.1)Linux
v3.3APIQt