赛灵思中国通讯53期:为何使用Zynq SoC可以让企业产品利润激增

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18 Xilinx News 赛灵思 2014 Issue53 Summer 2014 请即浏览 网络版的全部精彩内容 china.xilinx.com/xcell 为何使用 Zynq SoC 可以让企业产品利润激增 Virtex UltraScale FPGA 推动 Tb 级网络不断发展 再见,DDR 你好,串行存储器 Vivado HLS 推动协议处理系统 蓬勃发展 Vivado 2014.2 版本的最新消息 FPGA 助引力波 与暗能量搜 索一臂之力

description

《赛灵思中国通讯》杂志第 53 期的封面报道从金融运营角度介绍了为何 Zynq®-7000 All Programmable SoC 比 ASIC/ASSP 器件更适合于作为平台搭建的基础,使企业能够实现多产的盈利能力的原因。 另外,本期杂志还包括了各种巧妙的设计方法,以及“How-to”技术文章,适用于不同阶段的 Xilinx 用户。

Transcript of 赛灵思中国通讯53期:为何使用Zynq SoC可以让企业产品利润激增

  • 18

    X i l i n x News 2 0 1 4 I s s u e 5 3 S u m m e r 2 0 1 4

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    16 2014 2014 17

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    22 2014 2014 23

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    30 2014

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    36 2014

  • HBM

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    (NASDAQ:XLNX)HMCC Pico Computing

    All Programmable UltraScale 15Gb/sHMC UltraScale

    64 HMC 15Gb/sPico Computing HMC IP

    15Gb/s HMC

    HMC

    HMCC HMC

    Tamara Schmitz 20nm

    FPGA IP 15Gb/s HMCUltraScale FPGA HMC

    Pico Computing HMC

    HMC

    Pico Computing CEO Jaime CumminsPico Computing HMC IP

    UltraScale HMC UltraScale

    36 2014 2014 37

  • F P G A 1 0 1

    MTBF

    38 2014

  • Adam P. Taylor [email protected]

    (MTBF)

    /

    FPGA

    2014

    UG116

    MTBF

    MTBF

    MTBF

    MTBF

    FITFIT)

    1e-9 -1

    MIL-

    HDBK-217F Bell-core/Telcordia

    SR332MTBF FIT

    1

    38 2014 2014 39

    F P G A 1 0 1

  • InfantMortality

    FailureRate

    1/MTBF

    Wear OutTime

    Constant Failure Rate

    1 -

    MTBF

    Excel

    ()

    1.0

    1.0

    MTBF

    MTBF

    t

    ( )

    MTBF

    0.37 2

    MTBF 0.37

    37%

    /

    MTBF

    0.99 MTBF

    4,361,048 497

    MTBF

    40 2014

    F P G A 1 0 1

  • 2 - MTBF0.37

    1/2 MTBF P (s) - 0.6

    One MTBF P (s) - 0.37

    Time (years)

    Pro

    bab

    ility

    1

    0.9

    0.8

    0.7

    0.6

    0.5

    0.4

    0.3

    0.2

    0.1

    00 0.5 1 1.5 2 2.5 3

    Success Probability

    1/2 MTBF P (s) - 0.6

    One MTBF P (s) - 0.37

    1

    0.9

    0.8

    0.7

    0.6

    0.5

    0.4

    0.3

    0.2

    0.1

    00 0.5 1 1.5 2 2.5 3

    Success Probability

    MTBF

    MTBF

    ECSS-Q-30-11A

    NAVSEA TE000-AB-GTP-010

    QML Q IC

    QML V IC

    1

    40 2014 2014 41

    F P G A 1 0 1

  • ! ! ! ! NJM.QSG.49646! RNM!R!)C*! RNM!W!)T*! NJM.QSG.49647! I!! L!! NJM.QSG.2:611! KBO!UYW! KBO!T

    ! ! ! ! ! tvcsfhvmbufe! ! 0! ! DSD!

    Prime Connector

    Single Interface

    Redundant Connector

    Single Interface

    Prime Connector

    Module 1 Module 2

    Module 1 Module 2

    1 - IC

    2 -

    3 -

    ( B E R

    ECC)

    2

    flash

    FRAM

    (elapsed-time counter)

    42 2014

    F P G A 1 0 1

  • ARM

    ACK

    ACK

    FIRE

    ! ! ! !

    Parity X

    N of M X

    CRC X BCH X X Hamming X X FEDReed Solomon X X CDI

    4 -

    3 - EDAC

    3

    MIL-STD 38999

    /

    4

    (NACK)

    (ACK)

    NACK

    (EMI)

    3

    Xilinx

    2014 5 27

    Multicore Association

    All Programmable

    Xilinx,

    Inc. (NASDAQ:XLNX)

    Markus Levy

    25

    SHIM MCAPI

    Tomas

    Evensen

    Zynq-7000 All Programmable SoC

    42 2014 2014 43

    F P G A 1 0 1

  • Vivado HLS

    Kimon [email protected]

    James [email protected]

    44 2014

  • Vivado HLS

    RTL

    FPGA

    FPGA

    HLS

    HLS

    Vivado

    HLS

    Vivado HLS

    ARP/ICMP

    pingARP

    IP

    Vivado HLS

    Vivado HLS

    Vivado HLS

    Vivado HLS

    C/C++

    RTL

    Vivado HLS

    2014 45

  • 1

    FIFOHLS

    Vivado HLS C++

    RTL

    Vivado HLS FIFO

    Block RAM

    RAM C

    Vivado HLS FIFO

    AXI4-Stream

    Vivado HLS

    Vivado HLS

    GUI Tcl

    FIFO

    C RTL Vivado HLS

    C

    C/C++ C/C++

    C/RTLVivado

    HLS C/C++ RTL

    RTL

    Vivado HLS

    Vivado HLS

    Vivado SDNet

    52 RTL

    Vivado SDnet

    RTL Vivado HLS

    DCM

    Vivado HLS

    Vivado HLSVivado HLS

    C/C++

    1

    Vivado HLS

    46 2014

  • 1 Vivado HLS

    1 void topLevelModule(stream &inData, stream &outData) {2 #pragma HLS dataflow interval=13 4 #pragma INTERFACE axis port=inData5 #pragma INTERFACE axis port=outData6 7 static stream modOne2modTwo;8 static stream modTwo2modThree;9 10 moduleOne(inData, modOne2modTwo);11 moduleTwo(modOne2modTwo, modTwo2modThree);12 moduleThree(modTwo2modThree, outData);13 }

    1

    streamVivado HLS

    HLS

    FIFO

    C++

    axiWordStruct 2

    2 C++

    struct axiWord { ap_uint data; ap_uint strb; ap_uint last;};

    s t r u c t A X I 4 - S t r e a m

    Vivado HLS

    pragma

    1 4

    5 Vivado HLS

    AXI4-Stream

    AXI4-Stream I/F

    Vivado HLS AX4 I/F

    AXI4-Stream I/F Vivado

    HLS

    AXI4-StreamVivado HLS

    AXI4-Stream

    7 8

    Vivado HLS

    ap_uint

    64 I/F

    C/C++

    2

    Vivado HLS

    internal

    IIII Vivado

    HLS

    >1 II=2

    Vivado

    HLS RTL

    II=1

    Vivado HLS

    46 2014 2014 47

  • II Vivado HLS

    modOne2modTwo

    3

    inData

    validBuffer

    1outData

    Vivado HLS

    Vivado HLS

    ap_uint

    2 Vivado HLS

    1II=1

    Vivado HLS

    3 Vivado HLS

    1 void dropper(stream& inData, stream& validBuffer, stream& outData) {

    2 #pragma HLS pipeline II=1 enable_flush34 static enum dState {D_IDLE = 0, D_STREAM, D_DROP} dropState;

    5 axiWord currWord = {0, 0, 0, 0};

    67 switch(dropState) {8 case D_IDLE:9 if (!validBuffer.empty() && !inData.empty()) {10 ap_uint valid = validBuffer.read();11 inData.read(currWord);12 if (valid) {13 outData.write(currWord);14 dropState = D_STREAM;15 }16 }17 else18 dropState = D_DROP;19 break;20 case D_STREAM:21 if (!inData.empty()) {22 inData.read(currWord);23 outData.write(currWord);24 if (currWord.last)25 dropState = D_IDLE;26 }27 break;28 case D_DROP:29 if (!inData.empty()) {30 inData.read(currWord);31 if (currWord.last)32 dropState = D_IDLE;33 }34 break;35 }36 }

    4

    FSM

    ap_unit 5

    axiWord

    7

    if-else

    Vivado HLS

    RTL

    48 2014

  • D_IDLE FSM 10

    11

    Vivado HLS

    4

    4

    1 void merge(stream inData[NUM_MERGE_STREAMS], stream &outData) {

    2 #pragma HLS INLINE off3 #pragma HLS pipeline II=1 enable_flush45 static enum mState{M_IDLE = 0, M_STREAM} mergeState;

    6 static ap_uint rrCtr = 0;

    7 static ap_uint streamSource = 0;

    8 axiWord inputWord = {0, 0, 0, 0};910 switch(mergeState) {11 case M_IDLE:12 bool streamEmpty[NUM_MERGE_STREAMS];13 #pragma HLS ARRAY_PARTITION variable=stream-

    Empty complete14 for (uint8_t i=0;i

  • 2 3 4

    2 -

    5 MAC

    1 if (!inData.empty()) {2 inData.read(currWord);3 switch(wordCount) { 4 case 0: 5 MAC_DST = currWord.data.range(47, 0); 6 MAC_SRC.range(15, 0) = currWord.

    data.range(63, 48); 7 break; 8 case 1:9 MAC_SRC.range(47 ,16) = currWord.

    data.range(31, 0); 10 break;11 case 2:12

    5

    MAC

    inData 64

    2

    5 MAC 16

    MAC_SRCMAC

    32 MAC_SRC

    32

    Vivado HLS

    2

    INLINE

    6

    6Vivado HLS

    1 void module2(stream &inData, stream &outData) {

    2 #pragma HLS INLINE3 4

    Vivado HLS 3

    Vivado HLS

    RTL

    50 2014

  • 2 3 4

    3 - Vivado HLS

    7 CAM

    ARP

    noOfArpTableEntriesarpTableEntry

    MAC IP

    7CAM

    1 class cam {2 private:3 arpTableEntry filterEntries[noOfArpTableEn-

    tries];4 public:5 cam();6 bool write(arpTableEntry writeEntry);7 bool clear(ap_uint clearAddress);8 arpTableEntry compare(ap_uint

    searchAddress);9 };

    IPMAC

    for

    IP

    II=1

    8 CAM

    1 arpTableEntry cam::compare(ap_uint searchAddress) {

    2 for (uint8_t i=0;ifilterEntries[i].valid == 1 &&

    searchAddress == this->filterEntries[i].ipAddress)

    4 return this->filterEntries[i];5 }6 arpTableEntry temp = {0, 0, 0};7 return temp;8 }

    Vivado

    HLS

    RTL

    10GBps

    RTL Vivado HLS C/C++

    FPGA

    C

    FIFO

    HLS

    ping ARP IP

    ARP Vivado HLS

    10Gbp

    50 2014 2014 51

  • FPGA

    52 2014

  • FPGA

    Angela Sutton [email protected]

    Paul Owens FPGA [email protected]

    FPGA

    FPGA

    Synopsys Synplify Premier

    FPGA

    RTL

    (QoR)

    Vivado

    2014 53

  • ###==== BEGIN Clocks {Populated from tab in SCOPE, do not edit)create_clock name {clock} [get_ports {p:clock}] period 10 waveform {0 5.0}###==== END Clocks - {Populated from tab in SCOPE, do not edit)###==== BEGIN Inputs/Outputs - {Populated from tab in SCOPE, do not edit)set_input_delay {p:porta[7:0]} 1 clock {c:clock} add_delayset_input_delay {p:portb[7:0]} 1 clock {c:clock} add_delayset_output_delay {p:porto[7:0]} .5 clock {c:clock} add_delay###==== END Inputs/Outputs - {Populated from tab in SCOPE, do not edit)###==== BEGIN Registers - {Populated from tab in SCOPE, do not edit)set_clock_groups disable asynchronous name {clock_group} group {clock} comment {Source clock clock group}

    1.

    2.

    3.

    4.

    5.

    (define_path_delay, define_

    false_path)

    Vivado

    Synplify TCL

    FDC

    TCL: create_fdc_template

    1

    (.fdc)

    /

    Vivado

    Vivado

    Vivado

    ISE BUFG

    Synplify

    get_XX all_XX

    1SynplifyI/OVivado

    54 2014

  • Tcl check_fdc_

    query

    Synplify Premier

    set_option fast_synthesis 1

    / I/O

    I/O

    Synplify

    TCL

    TCL: project -run constraint_check

    2

    Synplify

    I/O

    RTL

    RAMS /

    DSP

    QoR FPGA

    RAMS /

    DSP

    Synplify

    SynCore IP

    RAM RTL

    IP IP

    CatalogSynopsys Synphony Model

    Compiler Synopsys Design Ware

    coreTools DesignWare Building

    Blocks IP

    DSP

    RTL

    2QoR

    54 2014 2014 55

  • 3

    combina t iona l -

    always

    RAM

    RAM

    RAM

    R A M

    RAM RAM

    (syn_ramstyle for Synplify

    software)

    RAM

    RAM

    DSP

    DSP

    (syn_ dspstyle for Synplify

    in Vivado Design Suite ows)

    DSP

    SRL

    select_SRL Xilinx SRL

    Synplify

    select_

    srl QoR

    syn_srl SRL

    RTL

    (PLL)

    PLL

    PLL

    Synplify HDL Analyst

    3

    RTL

    Vivado

    QoR

    R T L

    56 2014

  • 5

    4

    Synplify

    Vivado

    SLR

    Virtex-7 2000T FPGA

    SLR

    4Synplify

    TCL

    (report_timing)

    QoR

    Synplify Premier

    FDC

    set_clock_route_delay {c:clka} 1.4

    QoR

    5

    Vivado

    RTL

    http://www.synopsys.com/ fpga

    56 2014 2014 57

  • NI

    Eric Myers

    [email protected]

    Zynq SoC NI SOM

    58 2014

  • 1 Zynq SoCNI sbRIO-9651

    UBM

    2013

    57%

    (SOM) IHS2012

    SOM 2010

    2016 17.5%

    9.3%

    SOM

    Zynq-7000 All Programmable SoC

    OS

    SOM

    I/O

    NI sbRIO-9651

    SOM 1

    FPGA

    (HDL)

    NI SOM Zynq-7020

    SoC RAM

    P C B

    2Zynq SoC 667MHz

    ARM Cortex -A9

    Artix-7 FPGA

    MTBF

    NI

    2014 59

  • 2 NI SOMZynq SoC

    Specications

    Processor SoC

    Xilinx Zynq-7020667-MHz Dual-Core ARM Cortex-A9Artix-7 FPGA Fabric

    Size and Power

    50.8 mm x 78.2 mm (2 in. x 3 in.)Typical Power: 3 W to 5 W

    Dedicated Processor I/O

    Gigabit Ethernet, USB 2.0 Host, USB 2.0Host/Device, SDHC, RS232

    Memory

    Nonvolatile: 512 MBDRAM: 512 MB

    Operating Temperature

    -40 C to 85 C Local Ambient

    FPGA I/O

    160 FPGA I/O PinsCongurable Peripherals: Gigabit Ethernet,RS232 x3, RS485 x2, CAN x2

    CompactRIO

    NI

    SOM

    x2USB

    USBSDRS-232x2RS-

    485CAN

    I/O PMOD

    I/O

    PMOD

    NI SOM

    (BSP) NI

    Linux Real-Time

    3

    USB

    FPGA

    NI Linux Real- Time

    (OS) Linux

    Linux

    NI

    Linux Real-Time C/

    C++ Lab-VIEW Real-Time

    FPGA

    UBM2013

    60%

    OS

    NI SOM

    NI SOM

    BSP

    OS

    I/O

    FPGA

    FPGA

    Zynq SoC

    NI LabVIEW

    FPGA

    IPLabVIEW FPGA

    Lab-VIEW

    I/O

    HDL

    LabVIEW FPGA NI

    IP

    HDL

    IP Integration Node

    DMA

    FPGA

    COMPACTRIO

    I/O

    CompactRIO NI

    SOM

    CompactRIO NI SOM

    LabVIEW RIO

    60 2014

  • Application Software 1,000 GraphicalProgramming Functions

    Easy-to-Use I/OAPI Libraries

    Prebuilt Thread-Safe,Low-Level Drivers

    NI Linux Real-Time

    Ready to RunOut of the Box

    Industry-Leading Silicon

    LabVIEW and Middleware

    Driver API

    Device Drivers

    Operating System

    Board Support Package (BSP)

    NI RIO Embedded Hardware(CompactRIO, NI Single-Board RIO)

    3 NI SOM(BSP) NI Linux Real-Time

    FPGA

    I/O

    CompactRIO

    100 C I/O

    NI SOM

    I/O

    NI SOM

    BSP RAM

    FPGA

    NI SOM

    NI SOM

    NI SOM

    Optimedica

    NI

    SOM

    Optimedica

    Mike Wiltberger NI SOM

    ni.com/som

    Xilinx 2014 EDN

    1 0

    2005

    2 0 1 4 7 1 -

    A l l P r o g r a m m a b l e

    Xi l inx , I nc .

    (NASDAQ:XLNX) 2014

    EDN

    SoC (All Programmable

    SoC)

    2005 2014 EDN-China 10

    10

    Zynq

    2014 6 26

    10

    EDN-China

    EDN-China

    EDN-China

    All Programmable

    1 0

    2005 2014

    "EDN China "

    2006

    13

    Virtex FPGA, Kintex-7 FPGA,

    ISEVivado

    Zynq-7000 All Programmable SoC

    60 2014 2014 61

  • 62 2014

    Vivado 2014.2

    IP

    All ProgrammableIPVivadoVivado

    china.xilinx.com/vivado

    Vivado2014.2 china.xilinx.com/download

    VIVADO2014.2

    Vivado2014.2Virtex UltraScale

    Artix-7QXQ7A50T Zynq-7000 SoCXQ7Z045RF900 XA Zynq-7000 SoCXA7Z030FBG484

    Virtex UltraScaleXCVU065XCVU080XCVU095XCVU125

    Kintex UltraScale SSIXCKU100XCKU115 Virtex UltraScaleXCVU160XCVU440

    VIVADO

    Artix-7 7A50T 7A35T

    PCIe IP Zynq SoC 7Z100

    PCI Express IP PG054 Gen2 PCIe IP PG023Gen3 PCIe IP

    Vivado IP Vivado IP Integrator DRC validate_bd_design

    Vivado

    2013.4

    (WNS)2014.1

    VIVADO

    DSP

    Waveform Viewer

  • 62 2014 2014 63

    90% 50% FFT IP 80%

    MCode MultAdd 90% WinPCap 4.1.3 Windows 8.1

    Vivado 2014.2

    ULTRAFAST

    UltraFast

    Vivado

    UltraFast UltraScale

    DRC

    IP IPI

    Vivado HLS

    TCL

    (Tcl)

    Tcl

    Tcl Tcl Vivado

    Tcl Tcl

    Tcl

    (EDA)

    linting TclVivado (IDE)

    Tclapp app Vivado

    Tcl QuickTake

    VIVADOVivado Vivado

    Tcl Vivado IP IP Integrator

    VIVADO

    Vivado china.xilinx.com/training

  • 64 2014

    XAPP1206NEONZYNQ-7000 AP SOC http://china.xilinx.com/support/documentation/application_notes/xapp1206-boost-sw-performance-zynq7soc-w-neon.pdf

    CPU

    CPU(SIMD)

    CPU

    NEONZynq-7000 All Programmable SoC

    ARM Cortex-A9SIMD

    NEON

    Haoliang Qin

    Cortex-A9NEON

    NEON

    intrinsicsNEON

    CPU

    Qin

    XAPP1208BITSLIP http://china.xilinx.com/support/documentation/application_notes/xapp1208-bitslip-logic.pdf

    UltraScaleI/OI/O

    I/O

    UltraScaleI/O

    I/O

    7Virtex-6 FPGAI/O

    Bitslip

    Marc Defossez

    UltraScaleBitslip

    Bitslip

    Bitslip7 Virtex-6 FPGA

    ISERDESBitslip

    7 Virtex-6 FPGA

    7Virtex-6 FPGA

    Bitslip

    Bitslip

    XAPP1203ZYNQ-7000 AP SOCIPXADC http://china.xilinx.com/support/documentation/application_notes/xapp1203-post-proc-ip-zynq-xadc.pdf

    All Programmable

    (WP442)

    All

    ProgrammableFPGAAll Programmable SoC

    FPGA

    . . .

  • 64 2014 2014 65

    Mrinal J. SarmahCathal

    Murphy

    Zynq-7000 All Programmable SoCIP

    DSPAXI

    IP

    XADCVivado IP Integrator

    RTL

    XAPP1205ZYNQ-7000 ALL PROGRAMMABLE SOCIP INTEGRATOR http://china.xilinx.com/support/documentation/application_notes/xapp1205-high-performance-video-zynq.pdf

    Zynq-7000 All Programmable SoC

    (PS)

    James LuceroBob Slous

    Zynq SoC

    (PL)AXIARM

    Cortex-A9.

    PLAXI

    Zynq-7000 SoC

    (HP)Zynq SoCHP

    6432AXI3

    AXI(VDMA)

    844

    1920 x 1080p60Hz

    24AXIDMA

    (VTC)

    (TPG)AXIDMA

    (OSD)

    HDMI

    IP

    AXI

    4AXIDMAAXI4HP

    Cortex-A970%

    Zynq SoC ZC702

    XAPP1091KINTEX-7 FPGA2.0 http://china.xilinx.com/support/documentation/application_notes/xapp1091-k7-RTV-Engine-2-0.pdf

    (FHD)LCD

    NTSC/PAL

    Kintex-7 FPGA

    /

    Bob FengKavoos Hedayati

    XAPP1095ZYNQ-7000 ALL PROGRAMMA-BLE SOC2.1 http://china.xilinx.com/support/documentation/application_notes/xapp1095-zynq-rtve.pdf

    Zynq-

    7000 All Programmable SoC

    /

    Bob Feng

    2.1(RTVE 2.1)Linux

    v3.3APIQt