5. ERROR CORRECTION IN A/D CONVERTERStimor/EC_course/chp_5.pdf · The INL of a pipeline ADC has...

1

(c) 2001- Timo Rahkonen, University of Oulu, Oulu, Finland

5. ERROR CORRECTION IN A/D CONVERTERS

2-D correction LUT

• Table filling techniques

Pipeline converters

• Gain errors in pipeline• Redundant codes• Correction kernel for pipeline

Sigma-delta converters

• MASH Σ∆ converter• Digital error correction in multi-bit sigma-delta ADCs

Others

• Histogram analysis• Errors in flash ADC• Parallel quantisers - estim. channel gain, offset & timing offset

2


2-D LOOK-UP-TABLE CORRECTION

Look-up-table based correction technique is genericand can be applied to any type of ADC - however, thestructural information can be employed to speed up thecollection of data by modelling larger than just localerrors.

If errors can be measured, they can be corrected byusing a look-up-table (LUT). To compensate dynamicerrors, we need to know how fast the signal is increas-ing or decreasing. Because of this, the memory isaddressed by both the signal and its derivative, orpresent and previous sample - the latter being the mostsimple to implement.

The LUT is normally trained by using known sinusoi-dal 1- or 2-tone test signals. The task is divided to:

• filling the data• estimating the errors

FIR

LUTADCx

dx/dt

x

dx/dt

3


TRAINING METHODS

Direct INL Mapping

The most simple way to build the correction table is toestimate or measure the INL error and store it directlyto the entry addressed by x(k), x(k-1).

INL update in the neighbourhood

To speed up the training, the measured INL result isusually updated (weighted by a certain spreading func-tion) in some neighbourhood around x(k), x(k-1) .

Base functions for INL

Direct INL mapping is slow, and if any information ofthe error is available, various states can be grouppedtogether by using base functions that model the errortypical in that type of ADC. Base functions can begaussian bumps or pyramid shapes, for example, andonly the amplitude of the base functions is searched.

x(k)

x(k-

1)

x(k)

x(k-

1)

x(k)

x(k-

1)

4


SPREADING FUNCTIONS

To speed up training, an error measured in point x,y isupdateded also in a larger region in its neighbourhood.This creates problems with entries that already havesome non-zero value and here, the following is done:

• the desired value is calculated in the center point ofupdate region

• difference (error) between table entry and the desi-red value are calculated for all table entries withinthe update region

• this error plane is smoothed with pyramid or Gaus-sian mask so that far-away points will be updatadonly little

• table values are updated with the update value

Thus the nearest points are updated towards the desiredvalue but never past is.

05

1015

20

0

510

1520

-0.5

0

0.5

05

1015

20

05

1015

20-0.05

0

0.05

0.1

0.15

error(:,:) = desired(x,y) - table entry(: ,:)

update(: ,:) = error(: ,:) * Gaussian mask(: ,:)

5


SOME LESSONS

In the example left, a 2-D LUT is trained using a 2-tone test signal and exponential spreading function. An8-bit pipeline ADC was linearised at various 3-tonesignals, and the example left shows a couple of typicalerrors:

• The training signal does not cover the corners of thetable. Left is shown a situation where a high-fre-quency test signal sweeps outside from the correc-tion area: the circled results are outside the trainingarea and cause lot of spurious components.

• Another feature can be seen in the corrected INL.The INL of a pipeline ADC has stepwise changes(top curve) which are smoothed by the exponentialspreading curve. This leaves inpulse-like INL at theboundaries as shown with a dashed circle.

• Optimum width of the Gaussian spreading functionshown left seems to be L=3.5-4 for an 8-bit flash and4-5 for an 8-bit pipeline ADC.

-150 -100 -50 0 50 100 150-5

0

5

INL

-150 -100 -50 0 50 100 150-5

0

5

CO

RR

. IN

L

x(k-1)training area

corrected signal

spreadingx xo–( )2 y yo–( )2+

L2--------------------------------------------------

exp=

6


USING BASE FUNCTIONS

The direct filling used above needs the information ofstate-wise INL. Alternatively, the entire table can befilled using a set of some base functions by optimisingthe level of harmonic and IM distortion, for example.In this case, much less data is needed.

On the left, an M sample record is taken. x and y arethe current and previous sample, respectively, and gj()is a Gaussian base function in a certain positiondepending on j. Error eH is formed as a sum of N (e.g.50) first harmonics from FFT of the measurement, andit is modelled as a sum Cγ of L base functions g() eval-uated in each time point. Now, the amplitude vectorγcan be solved in LMS sense, and note that the resultsof several test tones can be combined in the error sumsG and r.

(Friel, Hummels, Irons)

C

g1 x1 y1,( ) .. gL x1 y1,( )

: : :

g1 xM yM,( ) .. gL xM yM,( )

= γa1

:

aL

=

eH ai iωt( )cos bi iωt( )cos+( )i 1=

N

∑=

Error is taken as an inverse FFT of harmonic Fouriercoefficients (a1,b1 areerrors in the fundamental ampl)

It is modelled as a set Cγ of base base functions g()

To minimise|eH - Cγ |2, base function amplitudes

γ G 1– r⋅=

where in a case of K different test tones

G CiT Ci

i 1=

K

∑= r CiT eHi

i 1=

K

∑=

γ are solved as

7


BASE FUNC CONT...

The figure left illustrates how eH is formed as a sum ofharmonic and spurious components. The figure belowshows a grid of 3 x 6 gaussian base functions in a x-yplane. By solving γ, the amplitudes for these base func-tions are obtained.

NOTE: TABLES VS. POLYNOMIAL

To linearise ADC converters, also 3rd or 5th orderVolterra filters have been experimented. However,Tsimbinos et al. have shown that a low-order post-dis-toster is not capable of correcting all the nonlinearityerrors, as typically the nonlinearity is of very highorder.

combine these aserror eH

Model them as base functions that may beGaussian, triangular, or blocks

x

y

gk(x,y)

8


PIPELINE ADC

Redundancy

Most subranging ADCs employ some redundancy thatallready corrects interstage offset errors and errors inthe ADC decision levels.

Gain error correction

As shown in chp 3, interstage gain errors appears as anerror proportional to the state of the stages. Thus, aneasy correction algorithm exists, provided that the gainerrros can be measured.

Sample-to-sample memory

Pipeline and algorithmic converters have a built-inmemory of several samples. Depending on the circuitstructure, sample-to-sample memory may appear.

9


REDUNDANCY

In subranging converters, accurate matching of thesubconverters is impossible. Thus, each subconverterhas certain amount of redundancy to avoid clipping.Typical redundancies are

• No redundancy. In this case offset errors result inclipping of the latter stages. A common solution tothis is to use non-integer radix (e.g. interstage gainof 1.95 instead of 2.00)

• 1 extra level. This allows 1/Gain lsb offset error ininterstage summation

• 1 extra bit ( 6 dB range). This is simple to arrage andgives total of 6 dB margin for offset errors.

Redundant outputs are combined as shown on the nextslide.

Vout

Vin ideal range

needed range

offset error in residue

Vout

Vin ideal range

needed range

offset error in ADC

10


EXAMPLE: 10-B 2-STEP ADC

Suppose a 4+6 bit 2-step ADC, where the 1st stagemakes 4-b quantisation and forwards a residue voltageV2 ( abs(V2) < 64(Vr1/2) ) to the 2nd stage that makesthe fine quantisation.Now the threshold errors of the 1st ADC are studied.Depending on the level of threshold Vth1, the output ofthe 1st stage is X or X+1. Now the input voltage V2 tothe 2nd stage is either one of (G=64)

that differ by 64Vr1 which is a complete full scale ofthe latter ADC. To allow 0.5 lsb threshold errors in the1st stage, the latter stage must be able to handle resultsthat may be 64*0.5 = 32 wrong. This means excessrange of one full redundant bit. With the help of thisextra bit, the total output is either

which are equal if GVr1/Vr2 = 64 exactly. (Above Yres

= G(Vin-XVr1)/Vr2 ).

V2 64 V in X 1+( ) V r1⋅( )–( )=

V2 64 V in X V r1⋅( )–( )=

out 64 X 1+( ) G 1 V r1⋅( ) V r2⁄( )⋅( ) Y res+–=

out 64X Y res+=

ADC1 D/A

ADC2+

-

++

G=26

6+1

4

+/- Vr/2

+32

-32

ADC1

X

Vth1

Vin

X

X+1

17 = 0010001

ADC2

- 47 = 1010001

64Vr64Vr

Y = V2/Vr2

V2 = G(Vin - X Vr1)

out

-64

11


EXAMPLE CONT ...: COMBINING

It was seen, that excess dynamic range in the latterADC helps to cancel threshold errors in the 1st ADC,but the 1st DAC and interstage gain need to be veryaccurate. Next question is how to combine the results.This is simply done by weighting and summing

which can be using either signed or unsigned digits. Asan example, consider that a correct value for ADC2 is+17 (signed) or 81 (unsigned). In both cased the msbof ADC is used to decide whether X should bedecreased/increased or not.

In case of unsigned digits, this results simply in sum-ming the overlapping digital words X and Y. In case ofsigned digits, a sign extension of negative numbers isneeded. With signed digits this is commonly calledRSD (Redundant Signed Digit) error correction.

out 64 X⋅ Y+=

+32

-32

ADC1

Vth1 X

X+1

17 = 0010001

ADC2

- 47 = 1010001

-64

81 = 1010001

17 = 0010001

X = 0010

signed unsigned

Signed

0010 000000

0000 010001

X

Y

Unsigned

0010 000000

0001 010001

X

Y

0011 000000

1111 010001

X

Y

0011 000000

0000 010001

X

Y

0010 010001 0011 010001

X = 0011

0011 0100010010 010001

12


REDUNDANCY IN 1-B PIPELINE ADCS

1-bit/stage pipeline converters can be in both redun-dant and non-redundant form. The last residue is

where ci=1-2Di for 1-level and -2Di for 2-level imple-mentations. Replacing Vres0 with D0VR and assumingGi=2, we can solve for Vin:

or (-7/8 ..8/8)VR input range for 1-level implementa-tion, and

or (-15/8..15/8)VR input range for 2-level implementa-tion. Hence, redundant converter has twice as largeinput range, which is typically used as spare room forvariations and overdrive headroom.

V res0 G0 G1 G2V in c3V R+( ) c2V R+( ) c1V R+=

G0G1G2V in G0G1c3 G1c2 c1+ +( )V R+=

V in

V R--------

18--- D0 2D1 4D2 8D3 7–+ + +( )⋅=

V in

V R--------

18--- D0 2D1 4D2 8D3+ + +( )⋅=

0, +/-VR

G2

D3

Vin +

+

G1

D2

+

+

G0

D1

+

+

D0

Vres0

+/-VR

G2

D3

Vin +

+

G1

D2

+

+

G0

D1

+

+

D0

Vres0

Vin

Vres

stable

VRVin

Vres

stable

VR

Di = 0,1

Di = -1,0,1

0 1 -1 0 +1

13


AMOUNT OF REDUNDANCY INPIPELINE ADC

Due to 3-level coding, a 1-b/3-level (1.5 bit) pipelineADC has 3N possible output states, while only 2N willbe used. This creates lots of redundant states.

The redundancy is removed in the error correction thatsimply implements

As noted before, the stage outputs can be considered assigned (-1,0,1) or unsigned (0,1,2) integers, and theerror correction logic for unsigned stage outputs isshown

out 2 j 1–( ) out j⋅j 1=

M

∑=-80 -60 -40 -20 0 20 40 60 800

2

4

6

8

10

12

14TOTAL 3^6=729 CODES

NO

. OF

RE

DU

NDA

NT

STA

TE

S

OUTPUT

ave 5.69

SSSS

0,1,2LSB

LSB

0

0

MSB

0 1

0 1

0 1

0 1

0 1 1 1 1

14


DIGITAL SELF-CALIBRATION

One of the first digital correction systems was pre-sented by Karanicolas (IEEE jSSC December93).Starting from the lowest stage corrected, Vin is forcedto zero and D(i) to 0 and 1 to measure levels S1 and S2with the remaining stages of the converter. Now theoutput can simply be reconstructed by adding the dif-ference D(S1-S2) where D=0 or 1 to the result of thelatter stages.After calibrating all stages from lowest towards msb,the total output can be formed as

where X is the uncorrected output, Di is the output ofstage i, NC is the number of corrected stages andmeasure weight S1i-S2i is used instead of assumedpower of 2. Now it is also easy to use non-radix-of-2base, and base 1.93 was employed in 12 first stages toavoid missing codes due to overflowing residues.

Y X lsbs S1i S2i–( ) Di⋅i 0=

NC

∑+=

+/-Vref

x2

+/-Vref

x2

D(i) D(i+1)

S1

S2

Y X S1 S2–( )+ D⋅=

Vin

Vin=0, D=1

Vin=0, D=0

+

+

15


KARANICOLAS CONT...

Essentially, Karanicholas has used in each calibratedstage the exact weight ∆i = S1,i - S2,i instead of theassumed power of two. Alternatively, the same correc-tion can be implemented by using radix-2 weigths,which simplifies the combining of the uncorrected dataXraw, and then summing the errors εi to the correctweights. This can be done where-ever (not necessarilyon-chip) the comparator data is available, and storingthe error instead of the actual weight reduces the wordlength of the correction term εi.

Example

Actual weight of an output bit is 2.0469 instead of2.00. This corresponds to a digital value ∆ of10.0000110. The error εi can be stored as a 3-bitnumber, ∆ as an 9-bit number

∆1∆0 ∆2 ∆3

+/-Vref

x2

D(i)

Vin +

+

NT T2T

ε0

Xraw

ε1 ε2 ε3 ε4Xcorrected

Vin

msb

16


“ACCURACY BOOSTING”

Soenen&Geiger extended the technique to multi-bitstages. Here, the height of each step is measured againusing the latter stages of the pipeline, and the weight ofcode n is sum all the steps leading to it. These weightsare calculated and stored into local memories.The calibration is started from the last stage to be cali-brated, and usually, a single non-iterated calibrationcycle is sufficient. Enough resolution is needed in thelatter stages, and to maintain this, several approachescan be used:• recycle the stages so that the residue of the lsb stage

is fed as an input to the msb stage• use additional lsb stages for calibration purposes

only as in Karanicholas93• temporarily increase the gain between the calibrated

and following stages

(Soenen, Geiger: An Architecture and an algorithm forfully digital ..., IEEE TCAS-II, March 95, pp.143-153)

A/D D/A

+

-

force control

G1Vcal Vres1

A/D D/A

+

-

y2

G2 Vres2

A/D

y3

w(0)w(1):

0

w(0)w(1):

x 2N

w(0)w(1):

∆1 ∆2 ∆3

∆1+∆2

∆1+∆2+∆3

US pat 5327129

Vresi

Vini

17


CORRECTING AMPLIFIERNONLINEARITY

Plain redundancy corrects the effects of comparatorand amplifier offsets. Previous correction techniquescancel the errors caused by capacitor mismatch andfinite DC gain. Also in pipeline ADCs, the fact that DCgain varies with output voltage causes distortion, andthis can be compensated with similar table based tech-nique.

One technique is based on performing piecewise-linearmeasurements of the actual gain

(Nagaraj, US pat 6232898)

Vo

Ao

18


CORRECTION EXAMPLE

Similar technique can be applied in pipeline converterswith redundancy, where gain and Vref errors can becorrected by multiplying the (-1,0,+1) output of eachstage by a coefficient ci and summing it to the outputword:

Now measuring or estimating the step height ∆i atVin=0 (point a) may overdrive the rest of the converter,and a bias closer to switching point Vth (point b) maybe preferred. However, the calibration procedure issimilar: last corrected stage is calibrated first, and itscorrected result is used to calibrated by the next stagetowards input. The correction ci can be calculated as adifference of ∆i and ideal step height.The correction logic per stage is very simple : oneaddition of constant multiplied by -1/0/+1. A divide-by-2 may used to keep same order of magnitudefor allcoefficients ci.

Y Xraw ci Di⋅i 0=

NC

∑+=

0

D2

correction

-1 +10Di

+∆0

-∆0

c2

Vres,i

a) b)

D1 D0

Xraw

Xcorrected0.5

19


Example

On the left, measured results from a 14-bit, 300 kS/spipeline ADC are corrected. Top figures show the non-corrected spectrum and INL of the ADC, and in thefigures below, gain errors in 4 msb stages are cor-rected. In this case, SFDR improved by 16 dB (from 63to 79 dB),and the largest remaining tones are 2nd and3rd harmonics produced in the sampling switches.

See also Lee: A 12-bit 600 kS/s ..., j SSC, April 1994.Here capacitor mismatches in each stage are calibratedby measuring separately the offset for zero input, andoutput for Vref input and Di forced to 1. The differ-ence of these is directly αVref, where α is the capaci-tor mismatch ratio.

-1 +10Di +∆0

Vres,i

0 50 100-120

-100

-80

-60

-40

-20

0

55.2/63.1 dB / 8.9 bit

-1 -0.5 0 0.5 1-3

-2

-1

0

1

2

3x 10-3 INL

0 50 100-120

-100

-80

-60

-40

-20

0

60.8/79.1 dB /9.8 bit

-1 -0.5 0 0.5 1-5

0

5x 10-3 INLc

Ori

gina

lC

orre

cted

H2 image

H3 image

kHz

kHz

81 kHz

SNR / SFDR / ENOB

20


FITTING THE COEFFICIENTS

Besides by DC measuring the level heights, the correc-tion coefficients can also be fitted. Two methods areshown on this page. In both methods, ideal sine yest isfitted to measured signal y, and correction coefficientsc0-cn are searched so that instantaneous INL=y(i)-yest(i) is modelled by comparator outputs d0-dn fromn first stages. The routine below supports on-line adap-tation of a double sampling AD where even and oddsamples have different coefficients. Direct fitting onthe left above can be used for a measured datasequence, for example.

NT = length(y); mu=5e-3; modul=2;yest = fitsine(y, freq, 1/fclk); INL = y - yest;for i=1:NT

px = 1 + mod(i,modul); % 1,2,1,2,1,2,...corr = c0(px)*d0(i) +c1(px)*d1(i);err = INL(i)-corr;c0(px) = c0(px) + mu*d0(i)*err;c1(px) = c1(px) + mu*d1(i)*err;

end

D

D0 1( ) .. Dn 1( )

: : :

D0 N( ) .. Dn N( )

= c

c0

:

cn

= y

y 1( ) yest 1( )–

:

y N( ) yest N( )–

=

c DT D( ) 1– DT y( )=

Direct fitting to measured data

0

D2

INL - correction

correction

adaptation

correction

c2 mu

0.5

21


SLOW SHADOW ADC

The use of parallel and accurate but slow shadow ADChas been proposed in many papers. At every Nth sam-ple (depending on the speed of the shadow ADC) theresults of the shadow and real ADC are compared anda corrector is adapted. In the example left, the stage i(AD(i)) is adapted by comparing the results of theshadow AD (SHAD) and back-end stages (AD-BE).LMS algorithm can be used to adapt the linear correc-tor :

which also converges (although slower) without theactual multiplications:

Sonkusale, v.d. Spiegel, Nagaraj, IEEE ISCAS2001see also US pat 4903026

α i( ) α i 1–( ) µ ε D⋅ ⋅+=

β i( ) β i 1–( ) µ ε⋅+=

α i( ) α i 1–( ) µ sign ε( ) sign D( )⋅ ⋅+=

β i( ) β i 1–( ) µ sign ε( )⋅+=

AD-FE AD-BEAD(i)

αD+β

εSHAD

D

22


PIPELINE: PN TEST SIGNAL

One way to measure the interstage gain is to use aknown pseudo-random (PN) test signal. Left, it isinjected in the residue voltage of the first stage in amulti-stage sub-ranging converter. This +/- 0.25 injec-tion increases the range of the residue, and more bitsare needed in the 1st DAC.Interstage gain G0 is evaluated by correlating the resultof ADC1 with the PN sequence, taking long-term aver-

age (225 samples, this de-correlates the input signals)and scaling. This gives an estimate for G0, and itsinverse is used to scale the results of ADC1

(Siragusa&Galton, Elect.Letters March2000)

AD

C0

DA

C

G0 (8)

PN

AD

C1

-

+

-

AoAVG & inv

17-level

correlator0.25

23


SIGMA-DELTA ADCS

Σ∆ modulators have a large amount of spectrallyshaped quantization noise. Some architectures arebased on measuring and cancelling this noise withanother ADC. On the other hand, multi-bit structuresare sensitive to mixing problems: DAC non-linearitiesmix this quantization noise back to baseband, thusreducing SNR.

Quantisation error cancelling techniques

• Leslie-Singh architecture• MASH architecture

Reducing non-linear effects in multi-bit sigma-deltaconverters

• In multibit Σ∆ DA converters, dynamic element mat-ching (DEM) or trimming are the only ways toreduce non-linear effects.

• In multibit Σ∆ AD converters, either DEM, trim-ming, or digital post-correction can be used.

24


FLOWGRAPH ANALYSIS

Especially in sigma-delta converters, the transfer func-tions easily get complicated. To aid symbolic analysis,the structure can be expressed as a group of equationsthat can be symbolically solved using Maple, forexample.

Another usual trick is to avoid recursive functions, inwhich case the system can be expressed as a sum ofstate variables multiplied by FIR transfer functions. Inthe example below, the situation in the input of blockH1 can be expressed as

which after substitution and multiplying by z-2 getsinto non-recursive form shown bottom left.

WH1H2--------------- U b1V–

b2H1-------V–=

sj

si

sk

sl

s j f i si⋅ f k sk⋅ f l sl⋅+ +=fi

fk

fl

1

f i– 1 f k– f l– ..

1

1

si

s j

sk

sl

:

⋅in

0

0

=

H1 H2

-b1 -b2 Q

WU

V

Hi = aiz-1/(1-piz

-1)

calc. here

V = W+E

1 p1z 1––( ) 1 p2z 1––( )a1a2

---------------------------------------------------------W z 2– U b1z 2–b2 1 p1z 1––( )

a1----------------------------------+

– V=

25


Example

Below is a Maple code for 2nd order SD modulator:

with(linalg):

H1 := 1/(z-1); H2 := 1/(z-1); # integrator functions

Y := matrix([[ 1, 0, 0, -b1], # node 1[ -H1, 1, 0, -b2], # node 2[ 0, -H2, 1, 0], # quantizer input[ 0, 0, -K, 1] ]); # output

Z := evalm(inverse(Y)): # solve system

sig := vector([a1,a2,a3,0]): # input branchesnoi := vector([0,0,0,1]): # quant noise

Hsig := collect(simplify(evalm(Z &* sig)[4]),z);Hnoi := collect(evalm(Z &* noi)[4],z);

H112

H2 K

-b2

-b1

noisesig

a1a3a2

43

Hsig

K a3z2 a2 2a3–( )z a1 a2 a2–+ + +( )

z2 Kb2 2+( )– z K b2 b1–( ) 1+ +--------------------------------------------------------------------------------------------=

Hnoiz 1–( )2

z2 Kb2 2+( )– z K b2 b1–( ) 1+ +-------------------------------------------------------------------------------=

26


LESLIE-SINGH ARCHITECTURE

One of the first multi-bit SDMs was the L-S architec-ture, where multibit ADC but still a single-bit feedbackis used. Here, N-bit quantization is modelled as noisesource un1, and its truncation to 1-bit feedback asanother noise source un2.Now, un2 has a transfer function Hn2 = out/un2 to out-put, and it must be modelled by a similar transfer func-tion Hn2 in the digital domain :• ADC msb is used as feedback• all bits except msb (i.e. the second quantization un2)

is shaped by transfer function Hn2’(z)• the original output out and the shaped 2nd quantiza-

tion noise Hn2*(out-msb) are summed together

This cancels the effects of the 2nd quantization. Thetotal noise transfer function is

(US pat 4987416, Jan1991)

Noutz 1–( )2

z2 z– 0.5+--------------------------- un1⋅ z– 0.5+

z2 z– 0.5+--------------------------- Hn2

""z( )–

un2⋅+=

-b1 -b2

H1 H2 Kun1

un2

1

Vin1

H1 = 1 / 2(z-1), H2 = 1 / (z-1)

AD

out - msb

msb

Hn2’

outun1--------- z 1–( )2

z2 Kb2 2+( )– z 2 K 2b1 b2–( )+( ) 2⁄+----------------------------------------------------------------------------------------------=

z 1–( )2

z2 z– 0.5+---------------------------→

+

-out

outun2---------

k– 2b2z 2b2– b1+( )

2z2 2– Kb2 2+( )z 2 K 2b1 b2–( )+( )+----------------------------------------------------------------------------------------------=

z– 0.5+

z2 z– 0.5+---------------------------→

out

1

(K=b1=b2=1)

H1 H2

-b1 -b2

Hn2

27


Example.

Left is simulated results of a 2nd order L-S modulatorwith 6 bit A/D converter and 1-bit feedback. As seen,the ADC output is currupted by high noise floor. Themsb output already shows noise shaping, but afterremoving the error casued by truncating to 1 bit, thetotal output shows clear improvement. In this example,error is calculated as sign(out)-out and it is shaped withtransfer function

where a1,a2 are the integrator and b1,b2 are feedbackweights, was used to cancel the quantization error. Thiscan be broken as two FIR filters, as shown on the nextslide.

Hn2

a2K b2z a1b1 b2–( )+( )

z2 a2Kb2 2+( )– z a2K b2 a1b1–( ) 1+( )+------------------------------------------------------------------------------------------------------=

-60

-50

-40

-30

-20

-10

0

AD

C o

ut

-120

-100

-80

-60

-40

-20

0

MS

B o

ut

-60

-50

-40

-30

-20

-10

0

Err

2*H

d

0 50 100 150 200 250 300 350 400 450 500-120

-100

-80

-60

-40

-20

0

Tota

l

28


LESLIE-SINGH CONT..

Cauwenberghs98 used a slightly different partitioningfor Leslie-Singh with lossy integrators. Now, the quan-tization noise un2 of the 1-bit feedback can be com-pletely cancelled by combining the multibit and 1-bitoutput by two FIR filters:

This results nicely in

Note: the transformation left below can be used tobreak a recursive equalizer function. Now also the lat-ter 1/B function can be left away as plain B nicelyequalizes the signal arriving in port 1.

F1

z a1 p1–( )+

a1z2------------------------------- a

p1a1------–

z 2– 1a1-----z 1–+= =

F2

z p1–( ) z p2–( )

a1a2z2---------------------------------------

1 p1 p2+( )z 1– z 2–+–

a1a2-------------------------------------------------------= =

Hsig Hsa F2⋅ Hsb F1⋅+ z 2–= =

Hnoi Hna F2⋅ Hnb F1⋅+ 0= =

-b1 -b2

H1 H2 ADCun1

1

Vin1

H1 = a1 / (z-p1), H2 = a2 / (z-p2)

out1

(K=b1=b2=1)

K

un2 (1-bit quantization)

F1

F2a

b

Hsa

a1a2Den-----------= Hna

a2 z p1– a1+( )–

Den-----------------------------------------=

Hsb

Ka1a2Den

----------------= Hnb

z p1–( ) z p2–( )Den

---------------------------------------=

Den z2 a2K p1– p2–( )z p1p2 a1a2K a2K p1–+( )+ +=

A/B A

B 1/B1 1

29


MASH Σ∆M

In MASH Σ∆ modulators, low order modulators arecascaded to create a stable high-order modulator. In thefigure left, plain quantization noise n1 is extracted bysubstraction g3(x+n1)-g2x. Hence, only the quantiza-tion noise n1 is forwarded to to the 2nd stage where itis quantized and substracted from the output of the 1stADC (Actually, some linear term can also be added byvarying the ratio of g2 and g3, and this results in atradeoff between dynamic range, maximum SNR, andspurious signals generated in the 2nd ADC. In general,g2=-g3 gives largest dynamic range).

In converter 2 noise n1 sees the signal transfer functionSTF2. Now to cancel n1 from output o1, a correctorHd is needed so that STF2*Hd = NTF1. This gives adifferentiating Hd, which cancels n1 completely andcauses further noiseshaping to n2. As a net result, thesystem behaves as a higher order modulator.

H1(z)

H2(z)

n1

n2+

-

k1

k2

Hd(z)

+

-

o1

o2

O1 ST F1 S⋅ NT F1 N1⋅+=

O2 ST F2 N1⋅ NT F2 N2⋅+=

OUT ST F1 S⋅ NT F1 Hd ST F2⋅–( ) N1⋅ Hd– NT F2 N2⋅ ⋅+=

s

NT F1 N1⋅ Hd ST F2 N1⋅ ⋅=

Hd

NT F1ST F2---------------= = Nth order differentiation

Hence also N2 is further differentiated

out

g3

g2

ggn1 only

x

30


Example

Supposing 2nd order modulators similar to L-S exam-ple (b1=b2=-1 and b3=b4=-1), k1=k2=1, g3=1 andg2=-1, the transfer functions on the left can be drawn.

Here, the nominator of O2/S is roughly 0 and nomina-tor of O2/N1 is roughly k2Den1. Now

which cancels n1 in OUT and leaves

However, the cancellation of N1 is sensitive to the val-ues of g2,g3, k1, and k2, as well as lossy integrators inH1 and H2. To correct these errors, Hd(z) needs to bean adaptable FIR filter, and some adaptation metricsare studied next.

Hd

NT F1ST F2---------------

2 z 1–( )2

Den1---------------------- Den2

k2--------------⋅ 2 z 1–( )2= = =

OUTN2

------------- Hd2 z 1–( )2

Den2----------------------⋅ 4 z 1–( )4

Den2----------------------= =

O1S

-------k1

Den1--------------=

O1N1------- 2 z 1–( )2

Den1----------------------=

O2S

-------k2 g2 k1 g3⋅+( )⋅

Den1 Den2⋅------------------------------------------ 0≈=

O2N1-------

k2 2g3z2 2 g2b2 2g3–( )z 2g3 2g2b2– g2b1+( )+ +( )⋅Den1 Den2⋅

--------------------------------------------------------------------------------------------------------------------------------------=

O2N2------- 2 z 1–( )2

Den2----------------------=

Den1 2z2 2k1b2 4+( )z– 2 k1 2b2 b1–( )+( )+=

2z2 2z– 1+( )≈

Den2 2z2 2k2b4 4+( )z– 2 k2 2b4 b3–( )+( )+=

2z2 2z– 1+( )≈

31


ADAPTING THE COMBINER

To adapt the equalizer Hd(z) in a MASH ADC, the fol-lowing methods can be used:

• Off-line calibration. A pseudorandom (PN) 2-levelin-band test signal can be used to adapt Hd(z).

• On-line PN signal can be added in to input and usedfor

• Blind adaptation. Here, the total amount of out-of-band noise is minimised by adapting Hd(z). Thisworks if input signal is bandlimited so that any out-of-band deterministic components are below noisefloor (Cauwenberghs).

• Out-of-band pilot signal. A pilot is summed to the n1quantization noise e.g. by modulating its threshold,and the residual (non-cancelled) pilot in the output isused as an error to adapt Hd.

Temes et al.: TCAS-II

H1(z)

H2(z)

n1+pilot

n2+

-

k1

k2

Hd(z)

+

-

o1

o2

s out

g3

g2

ggn1 only

AAF Hc

32


ADAPTING MASH ...

Blind adaptation based on out-of-band noise soundstempting, but it suffers from• correlation between the quantization noise and the

input signal.• out-of-band blockers must be filtered, so the selecti-

vity of the digital filters can not be fully employed.• as signal itself is not measured, the gain can not be

adapted.

Left is the implementation presented in Part II paperbelow. Analog errors are a modelled as a leakage pathHeq(z), that is adapted so that a PN test signal ts disap-pears from the output. Hence, Heq is a normal LMSfilter which is adapted by correlating out with ts

see Temes et al.: Adaptive Digital Correction of Ana-log Errors in MASH ADC’s, Parts I-II, IEEE TCAS-II,July 2000.

-b1 -b2

H1 H2 Kqun1+ts

1

Vin1

H1 = a1 / (z-p1)

1

K=b1=b2=1

a

1-z-1 1-z-1

z-N

unM

Heq(z)

H2 = a2 / (z-p2)

Digitize quantisation noise

out

33


MULTIBIT Σ∆ ADC

Especially at low oversampling ratios, a multibit feed-back in a Σ∆ ADC is often desired, as with it

• Total SNR improves 6 dB/bit• Quantizer gain is more stable, resulting in stable

NTF and SNR• As stability is better, more agressive loop filters can

be used

But• INL in the feedback DAC causes distortion and

mixes shaped quantisation noise back down.• Linearity of the DAC must match the total require-

ments.

There are three ways to correct this• employ DEM in the feedback DAC• employ trimming in the feedback DAC (requires e.g.

12 bit linearity from a 3-bit DAC)• employ digital correction after conversion

LOOPFILTER

DAC

3

INL

34


SPECTRAL EFFECTS OF DACNONLINEARITY

Nonlinear feedback causes distortion in the output.Even though the distortion itself were not harmful, itspreads the quantisation noise spectra.

Even order INL (a) is worst, as it both widens thequantisation noise spectra and rectifies it to DC, thusfilling the baseband and causing DC offset, It also cre-ates even harmonics.

Odd order nonlinearity does not rectify, but the widen-ing of quantisation noise spectra is enough to fill thepassband with excess noise. It also creates odd har-monics, but not DC offset.

a)

b)

Quantization noise

Rectified noise

Quantization noise

Noise3

code

INL

a) Even order

a) Odd order

Offset

35

(C) 1999- Timo Rahkonen, University of Oulu, Oulu, Finland

SHAPING OF NONLINEARITIES

The most usual way to tackle D/A nonlinerity is toshape the nonlinearity away from signal band usinge.g. a DWA algorithm. In the enclosed code and thenext figure, 1st order quantization error noise shapingis used to clean up the baseband spectrum. It is seenthat high order (L > 2) modulators would also requirea high order shaping for the errors: at high OSR, theperformance is limited by inadequate shaping of theerrors. Higher order shaping is possible but also morecomplex to implement.

Matlab code for the next plot:

OSR = 10.^(0:0.05:2);

figure(900)chs = ['rgbkcy'];maxs = 120;v = [1 100 0 maxs];err = 0.01;

for L=1:6 tmp = sqrt(1.5*(2*L+1))*OSR.^(L+0.5)/(pi^L); ch = chs(L); for N=1:5 M = 2^N; snr = (2^N - 1)*tmp; SNR = 20*log10(snr); mask = SNR > maxs; SNR = SNR.*(1-mask)+maxs*mask; snrdem = sqrt(3*M*OSR.^3)/(pi*err*(1-1/M)); SNRDEM = 6.02*log(snrdem)/log(2); subplot(3,2,L) semilogx(OSR,SNR,OSR,SNRDEM,':') hold on end title(['N=' int2str(L)]) hold off axis(v) grid ylabel('SNR dB'), xlabel('OSR')end

36


020406080100

120

L=1

SNR dB

020406080100

120

L=2

SNR dB

020406080100

120

L=3

SNR dB

020406080100

120

L=4

SNR dB

110

100

020406080100

120

L=5

SNR dB

OS

R

020406080100

120

L=6

SNR dB

NB

=

5 1

DE

MD

EM

DE

MD

EM

DE

MD

EM

110

100

OS

R

110

100

OS

R1

1010

0O

SR

110

100

OS

R1

1010

0O

SR

37


LUT CORRECTION OF MULTIBITSIGMA-DELTA ADCS

Instead of shaping the DAC errors they can also becompletely cancelled. This can be done by storing theactual and measured weights of the feedback DAC in alook-up-table (LUT) and using either

• a trim DAC parallel to the main DAC. Here, the cor-rected linearity should match the required averallperformance (12 bits in the figure).

or

• a digital corrector, where error propagation Hn fromDAC to output is modelled with a similar transferfunction Hn’. Here, Hn’ is very important, if Hn isnarrowband, but in some cases it can be replaced bysimple delaying. Temes et al. have used for Hn’ adigital replica of the SDM, which imitates Hn andalso noise-shapes quantization errors, in which casethe output word length can be reduced.

LOOPFILTER

DAC

3

13

INL

DAC

LUT Hn’

A

B

12

Hn

Vin

38


CALIBRATING MULTIBIT DAC

The simplest form to calibrate the errors in the DAC isto configure (portions of) the modulator to a 1-bit Σ∆ADC and use the feedback DAC as a signal source.Now the DC levels generated by the m-bit DAC aremeasured using heavy averaging and the errors com-pared to ideal levels are stored into the LUT.

After calibration, the test feedback is disconnected andthe LUT is connected as shown in the previous slide.

For on-line calibration, a separate 1-bit SDM can beused to measure the feedback unit elements one at atime. To maintain full output range, one redundant ele-ment is needed, and for the correction, the sum of unitelement errors must be built.

LOOPFILTER

DAC

INL

LUT

1-bit feedback during calibration

AVG

scan all levels

m

DC in

0

LOOPFILTER

DACm

LUT

Hn

ADCupdate

1 redundantunit elementat a time

39


BACKGROUND CALIBRATION USINGHISTOGRAMS

Previous adaptation requires a known test signal. As analternative, a background calibration based on analys-ing amplitude histograms is studied. The basic idea is:

• assume continuous and smooth amplitude distri-butions

• estimate (filter) the ideal histogram• calculate the difference between the measured and

estimated histogram• recognise discontinuities caused by ADC nonlineari-

ties

Left is shown the amplitude pdf for a 1-tone sinusoid.In a case of multitone test signal, the pdf approachesGaussian pdf.

(see Elbornsson: Blind Estimation and Error Correc-tion in a CMOS ADC. IEEE 2000)

A-A-A

A

A-A

-150 -100 -50 0 50 100 1500

50

100

150

200

-150 -100 -50 0 50 100 1500

50

100

150

200

0 +1-1

0 +1 -1 00 +1 -1

MSB

MSB-1

40


-1-0

.8-0

.6-0

.4-0

.20

0.2

0.4

0.6

0.8

10

50

100

150

200

INPUT PDF

HIS

TO

GR

AM

AN

ALY

SIS

-1-0

.8-0

.6-0

.4-0

.20

0.2

0.4

0.6

0.8

1-2-1

012

INL1

-1-0

.8-0

.6-0

.4-0

.20

0.2

0.4

0.6

0.8

10

50

100

150

200

PDF1

-1-0

.8-0

.6-0

.4-0

.20

0.2

0.4

0.6

0.8

1-2-1

012

INL2

-1-0

.8-0

.6-0

.4-0

.20

0.2

0.4

0.6

0.8

10

50

100

150

200

PDF2

MIS

SIN

G O

R N

AR

RO

W C

OD

ES

NO

N-M

ON

OT

ON

ICIT

Y

41


MISSING OR NARROW CODE

Positive h in INL function causes missing or narrower-than-usual codes. INL step size can be estimated by

If N2 goes to zero or faster collecting of the histogramis desired, several adjacent bins can be combined. Ife.g. two bins on both sides of the step are collected,then

Example:

N1 = N3 = 100, N2 = 0, and N4 = 50 gives h=1.5. Thesituation shown left suggests h = 0.85.

hN1 N2–

N1---------------------=

h 2N1 N3+( ) N2 N4+( )–

N1 N3+( )-----------------------------------------------------------⋅=

Bin

ary

digi

ts

N1

N2

N1

N2

N4N3

h

bit change

42


NON-MONOTONICITY OR WIDE CODE

Negative h in INL function causes missing or nar-rower-than-usual codes. INL step size can be estimatedby

where N1 < 2N2. If the expected non-monotonicity islarger than 1 lsb (h<-1) or faster collecting of the histo-gram is desired, several adjacent bins can be com-bined. If e.g. two bins on both sides of the step arecollected, then

Example:

N1 = 200, N3 = 150, N2 = N4 = 100 gives h=-1.5. Thesituation shown left suggests h = -0.7.

hN2 N1–

N2---------------------=

h 2N2 N4+( ) N1 N3+( )–

N2 N4+( )-----------------------------------------------------------⋅=

Bin

ary

digi

ts

N1

N2

N1 N2 N4N3

h

Bit change

43


HISTOGRAM CORRECTION INPIPELINE ADC

It is not necessary to measure the entire histogram.Instead hits in the closes bins around transitions of astage output can be measured, and based on thesenumber of hits, a correction coefficient can be calcu-lated.In pipeline converters, two succeeding stage changetheir state in the same bin. Thus the total error is a sumof errors in two succeeding stages, and e.g. the correc-tion coefficient for MSB stage must be calculated fromthe errors measured both at MSB and MSB-1 transitionpoints:

Cmsb hmsb 2hmsb 1–+=

-150 -100 -50 0 50 100 1500

50

100

150

200

-150 -100 -50 0 50 100 1500

50

100

150

200

0 +1-1

0 +1 -1 00 +1 -1

MSB

MSB-1

N1N2

N1N2

44

(C) 1999- Timo Rahkonen, University of Oulu, Oulu, Finland

ERRORS IN FLASH CONVERTERS

Structure

Resistor string, comparators, thermometer coding,lin-to-bin coding

Bubbles in thermometer coding

• Minimize clock skew• Employ hi-priority coding to find only the highest

set flip-flop. Usually not complete, but width=3• Employ Gray-coded output to minise the effect of

bubbles

Metastability of comparators

During sampling, the comparator is connected to aflip-flop with positive feedback whose output is

Thus, for small enough vi0 the output may not reachfull logic levels during the sampling period and thestate of the comparator is indefinite. This can be

cured by

• Multiple synchronizer stages• Force buffers to make always a decision

Time constants of the resistor string

Different signal amplitudes are delayed by differrentamount. This causes distortion.

In single-ended structure input feedthrough to refer-ence string causes signal-dependent thresholds andhence mixing.

See papers by Steyaert

vo t( ) vi0 t τ⁄( )exp⋅=

45


RC TIME CONSTANTS IN FLASH ADC

Left is a structure of a flash ADC: constant bias currentsources and resistor strings are used to create level-shifted versions of differential input signals, and cross-connected comparators are used to sense the amplitudelevel.Now parasitic capacitive loading of the resistor stringcauses displacement currents that cause hystereticerrors in the comparator levels. This causes odd orderhamonics.

This phenomena has been analysed using a disstributedRC model for the resistor string in

Boni, Morandi, Harmonic Distortion in High-SpeedDifferential A/D Converters, IEEE TCAS-II March 98

vinp vinm2N-11

v(x) = vinp - vbe - x R (Ib + ierr)

46


BOOTSTRAPING THE R-STRING

One way to minimise the capacitive loading of theresistor string is to bootstrap the capacitance: a poly1shield under the poly2 resistor follows the voltage vari-ations in the resistor string. Thus, no displacement cur-rents are flowing in the capacitors and the R-string anymore, and distortion may be reduced by10 - 15 dB..

vinp vinm2N-11

metal contacts

poly2 resistor

poly1 shield

silicon

v(x) = vinp - vbe - x R (Ib + ierr)

vboot = vinp - vbe

47


CORRECTION OF INTERLEAVED ADCONVERTERS

As noted before, both offset, gain and timing mis-matches in interleaved A/D converters cause spurioussignals. Blind correction methods for these have beenstudied e.g. by Elbornsson, Eklund, and Gustafsson.

Offset cancellation

This is easily done by collecting DC average values ofeach channel, calculating the differences of these, andsubstracting these from output results. A PN choppercan be used to randomize the input and speed up theaveraging.

Time skew cancellation

Provided that input bandwidth is limited to fs/6, timingerrors can be estimated by collecting the squared dif-ferences of adjacent samples. Wideband noise affectsthe estimated results and it too must be estimatedsomehow.

5. ERROR CORRECTION IN A/D CONVERTERStimor/EC_course/chp_5.pdf · The INL of a pipeline ADC has...

Documents

Transcript of 5. ERROR CORRECTION IN A/D CONVERTERStimor/EC_course/chp_5.pdf · The INL of a pipeline ADC has...