第3章 計算機組織 (Update)

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1 3章 計算機組織 中央處理器 主記憶體 執行程式 輸出入周邊設備 儲存裝置 3-2 電腦基礎元件 真空管 電晶體 積體電路 超大型積體電路

Transcript of 第3章 計算機組織 (Update)

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2. (CeBIT) (COMPUTEX TAIPEI) (COMDEX FALL) 3-3 3-42 3. 3CComputer()Communication() Consumer electronics() 3-5 ()(Arithmetic LogicUnit, ALU)(Control UnitCU)(Memory Unit, MU)(Input Unit)(Output Unit) 3-63 4. 3-7 () decode/ /execute quot;Aquot;11000001 1 10 0 0 00 1 11 00 00 01 0 10 0 00 01 A 01 00 00 01 3-8 4 5. (AND)(OR)(Exclusive OR,XOR)11000001110000101(0000 0001)2(0000 0010)11000011 3-9 3-105 6. 3-11CPUCPU80286803868048680586 (Pentium)PentiumIIIIIIV(P4)CPUCPUMIPSMFLOPSGFLOTSMHz(Hertz)(Megahertz, MHz)3-12 6 7. (clock)CPU400MHzCPU1/(400*106)=1/(4*108)2.510-92.5(ns)CPU2.5(ns)12 3-13 CPU (Random Access MemoryRAM)3-147 8. CPU(bus)(data bus)(control bus)(address bus) 3-15CPUCPU1616324(byte)CPU(Word) 3-16 8 9. CPUCPU1000 0000 0000 0000 0000 11113(0000 0011) ? 1 10 00 0 000 0 000 0 000 0 000 1111 CPU 2 0 000 0 011 ? 3-17 20 2201MBCPU 32232=4GB CPU 3-189 10. operand 3-19 3-20 10 11. Steps of a machine cycleThe CPU uses repeatingmachine cycles toexecute instructions inthe program, one by one,from beginning to end.A simplified cycle canconsist of three steps:fetch, decode, andexecute. 3-21Example: adding two integersContents of memory and register before execution 3-22 11 12. PCProgram CounterIInstruction Register 3-23 Example: first operationContents of memory and registers after first operation 3-24 12 13. Example: second operationContents of memory and registers after second operation 3-25Example: third operationContents of memory and registers after third operation 3-2613 14. Example: fourth operationContents of memory and registers after fourth operation 3-27(pipelining) 3-2814 15. CPUCPU () ( ) KBMBGB3-29 ( ) CPUCPU CPU CPU2.X1. 3-30 15 16. (address)1(Byte)1KB210=1024 (2 ) (1 6 ) 0 0 00 0 00 0 0 0 0000 0 11 10 0 10 0 00 0 00 0 0 1 0010 10 0 00 0 10 0 00 0 00 0 1 0 0020 10 0 00 1 0 1 11 1 11 11 0 13FD1 1 11 1 11 11 03FE1 1 11 1 11 11 13FF 3-31 3-32 16 17. Note:Memory addresses are defined usingunsigned binary integers. 3-33ExampleA computer has 128 MB of memory. Each wordin this computer is 8 bytes. How many bits areneeded to address any single word in memory? Solution The memory address space is 128 MB, whichmeans 227. However, each word is 8 (23) bytes,which means that you have 224 words. Thismeans you need log2 224 or 24 bits, to addresseach word. 3-34 17 18. 3-35Memory hierarchy Small amount of high-speed memory: register Moderate amount of medium-speed memory: cache memory Large amount of low-speed memory: main memory. 3-3618 19. (Main Memory) (Secondary Memory) (Main Memory) CPU (Internal Memory) (Read Only Memory,ROM) (Static Random Access Memory,SRAM) (Dynamic Random Access Memory,DRAM) (Secondary memory) (Externalmemory) 3-37RAMRandom Access MemorySRAMStatic RAMDRAMDynamic RAMROMRead-Only MemoryPROMProgrammable ROMEPROMErasable Programmable ROMEEPROMElectronically ErasableProgrammable ROM 3-38 19 20. ROM ROM 3-39 PROM (Programmable ROM) ROM( ) EEPROM (Electrically Erase PROM) ROM Flash Memory Flash ROM (Basic Input/Output System, BIOS) MP3 3-40 20 21. BIOSBIOS Basic Input/Output System, BIOS() BIOSROM boot strap loader BIOS 3-41 (Static Random Access Memory, SRAM) (Dynamic Random Access Memory, DRAM) (10~15ns) SRAM DRAM CPU (cache memory) 3-4221 22. (DRAM)CPUDRAM(cache memory)CPUCPUCPUDRAM Cache DRAM CPU 3-43Cache Cache memory is placed between the CPU and main memory.At any time cache memory contains a copy of a portion of mainmemory.80-20 rule: It has been observed that most computers typicallyspend 80% of the time accessing only 20% of the data. Cachememory can hold this 20% data to make access faster at least80 % of the time. 3-4422 23. (Dynamic Random Access Memory, DRAM)(SRAM) (60-70ns) DRAMRAM DRAM D RAM ACPU B A B 3-45ROMSRAMDRAMROM > SRAM > DRAM > ROM < SRAM < DRAM < ROM > SRAM > DRAM > 3-46 23 24. CMOSCMOSCMOS 3-47 CPU 3-48 24 25. Connecting I/O devices to the busesA controller handles the I/O operations between theCPU/memory and the much slower I/O devices.FireWire and USB are common controllers. 3-49 USBUSBUniversal Serial BusUSB 2.0480MBUSB 1.01.5MBUSB 1.112MB 3-5025 26. USB 3-51IEEE 1394IEEE 1394 Apple FireWireSonyi.Link / IEEE 1394400MBIEEE 1394b1GB USBPC 3-52 26 27. Isolated I/O addressing There are two methods to handle the addressing of I/O devices: isolated I/O and memory-mapped I/O The instructions used to read/write memory are different from the instructions used to read/write input/output device 3-53Memory-mapped I/O addressing CPU treats each register in the input/output controller as a word in memory. In other words, CPU does not have separate instructions for transferring data from memory or input/output device 3-5427 28. Programmed I/O When the CPU encounters an I/O instruction, it waits for the I/O device and does nothing else until the data transfer is complete. The CPU constantly checks the status of the I/O device until the I/O device is ready. The big issue is that the CPU time is wasted by checking the status of the I/O device. 3-55Interrupt-driven I/O The CPU informs the I/O device that a data transfer is going to happen, but it does not test the status of the I/O device continuously. The I/O device informs (interrupts) the CPU when it is ready. During the time, the CPU cab do other jobs. The CPU time is wasted. 3-5628 29. (Interrupt) interrupt request, IRQ () I/O 3-57(DMA) (Direct Memory Access, DMA) CPU () DMA I/O CPU D MA I/O () 3-5829 30. Direct Memory Access (DMA)DMA transfers a large block of data between a high speed I/Odevice, such as a disk, and memory directly. 3-59 3-60 30 31. PS2USB 3-61PS2USB 3-6231 32. TIFFBMPGIFPCXdpidot perinch3-63 monitor CRT Cathode Ray Tube LCDLiquid Crystal Display3-64 32 33. dpidot per inch 3-65ZipMO3-66 33 34. Hard Disk 3-6701 3-68 34 35. 111 3-69000 3-70 35 36. 3-71(Sony)(Philips)CD-ROMCD 650MBDVD(Digital Versatile Disk) 4.7GB 17GBCD(CD-ROMCR-RCR-RWVCD) 150KBDVD(DVD-ROMDVD-RDVD-RWDVD-Video) 1350KB3-72 36 37. organic dyematerial 3-73Compact DiscRecordableCD-R10 0 1 3-7437 38. 00110 1 3-75 , 4 3-7638 39. , 3 IDM (Integrated Device Manufacturer, ) IDM , , , , IBMIntel 3-77Fabless IDM , , , Fabless, , 3-7839 40. , , , , Fabless , , (VIA) (Ali) (Realtek) 3-79Design House Design House IC ,, 34, IC , IC, , ,, IDM , Fabless Design House , IDM 3-80 40 41. IDM IC , , , IDM , , IDM , 1987 , (TSMC, Taiwan Semiconductor Manufacturing Company) () , 3-81 , Fabless Design House IDM , , Foundary 3-8241 42. , , , , , IC , , , , IDM 3-83 , IDM , , , 5 , , , 3-8442