256 ENTREES / SORTIES DIGITALES PCI 104-DIO · 2018. 10. 12. · +54 Readload STB 624 Groupe 5 RO...

Module intégré PCI 104

256 E/S digitales programmables par ports de 32 voies

8 bus séries haute vitesse PCM (NRZL + clock)

Relecture et comparaison de trame

Synchronisation entre les canaux

Liaisons différentielles RS 485

Haute densité / haute fiabilité

Espace mémoire 32 bits / 33MHz

Développée pour le milieu industriel nécessitant des contraintes fortes sur le temps réel, la carte PCI 104-DIO permet la gestion de 256 entrées / sorties digitales.

Les 8 groupes de 32 voies utilisent des liaisons séries synchrones avec relecture et comparaison des données transmises.

La trame PCM utilisée est encodée en NRZL + horloge sur lignes différentielles RS 485.

Les données sont écrites et relues en quelques microsecondes avec une synchronisation inférieure à 1µs entre canaux.

La carte PCI 104-DIO peut piloter 8 borniers de type STB 624.

9 rue Georges Besse – BP 47 – 78330 FONTENAY LE FLEURY – FRANCE

Tél.:(33) 1 30 58 90 09 fax:(33) 1 30 58 21 33 http://www.adas.fr

256 ENTREES / SORTIES DIGITALES PCI 104-DIO

PCI 104-DIO

SPÉCIFICATIONS (t = 25°C)TYPE ENTREES/SORTIES DIGITALES ENTREES / SORTIES - Nombre de E/S 256- Voies 8 x 32 E/S - Bus Série Question / Réponse - Wave NRZL + CLK (PCM) - Coupleurs Transcepteur RS 485 Optimizé pour réseaux PROFIBUS - Timing

Ecriture + Lecture # 15µs Lecture seulement # 10 µsSynchro (charge) < 1µs

Longueur entre carte & STB 624 8 m max INTERFACE PCI- Bus PCI 33 MHz - Transferts 32 bits dans l'espace mémoire ALIMENTATION - Tension + 5V / TBD ; + 3,3V / TBD PRESENTATION- Dimensions PCi 104 form factor (3,775 x 3,550 inchs) - Connecteur E/S Interne 4 x HE 10/20pts males - Connecteur E/S Externe 8 x DE9S ENVIRONNEMENT- Température de fonctionnement - 20°C à + 70° C - Température de stockage - 25°C à + 85° C- Humidité relative 90 % (sans condensation) NORMES EUROPEENNES EMC - EN 61326 - EN 55011 Class A CE Compliance ROHS - 2002/95/EC

COMMENT COMMANDER? PCI 104-DIO

ACCESSOIRES - Bornier STB STB624- Câble WR243

1 26/22

PCI 104-DIO – Rev. A – Edition 1 – 26/25

1

TRACEABILITY FORM

DOCUMENT FOLLOW-UP

Title: Titre : PCI 104-DIO

Documentation française Edition: 1 (Document creation - Création du document)

Revised

Approved

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by B. THOUËNON

B. THOUËNON

D. PIMONT

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Warning: Unless otherwise stated, this revision overwrites the previous one, which must be destroyed, along with any copies given to your collaborators.

Avertissement : En l’absence d’indication contraire, cette nouvelle édition annule et remplace l’édition précédente qui doit être détruite, ainsi que les copies faites à vos collaborateurs.

Edition Edition

Nature of the modifications (key words) Nature des évolutions (mots clés)

Written Rédigé

Revised/ApprovedRevu/Approuvé

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DOCUMENT ARCHIVEDDOCUMENT ARCHIVE No Yes on

Δ ed. .. [ ] = Document input/output (Entrée/sortie modification de la documentation) # ed. .. [ ] = Board new function input/output (Entrée/sortie nouvelle fonctionnalité du produit)

DSQ - 4.5.a - Indice F - 98/41 T.S.V.P.


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NOTES :

!

ATTENTION

CETTE CARTE UTILISE LES ALIMENTATIONS PCI 5V ET 3,3V


3

PCI 104-DIO

SOMMAIRE

Chapitre A Présentation .........................................4

A.1. Câblage et interconnexion......................................................4

Chapitre B Interface PCI .........................................5

B.1. Avertissements........................................................................5

B.2. Littérature.................................................................................5

B.3. Registres de configuration PCI ..............................................6

Chapitre C Cartographie PCI 104-DIO .................10

Chapitre D Fonctionnement .................................14

D.1. Principe d’échanges..............................................................14

D.2. Synoptique d’un canal ..........................................................15

Chapitre E Alimentation .......................................16

Chapitre F Mise en oeuvre ...................................17

F.1. Installation..............................................................................17

F.2. Sélection du numéro de carte ..............................................17

Chapitre G Connectique .......................................18

Chapitre H Borniers de conditionnement ...........20

Annexe .............................................................21

PLAN DE CONFIGURATION ...................................................................21

PLAN D’ÉQUIPEMENT ..........................................................................21

RÉGISTRES DE CONFIGURATION PCI.....................................................21


4

Chapitre A Présentation

La carte PCI 104-DIO est une carte PCI 104 qui possède les ressources suivantes :

Gestion de 256 Entrées / Sorties digitales en 8 groupes de 32 voies

Transmission PCM en NRZL + Horloge Sureté de fonctionnement par relecture automatique des

données Synchronisation des changements d’état Etat connu à la MST (Mise sous tension)

De conception moderne et de haute technologie, la carte PCI 104-DIO s’intègre dans toutes les machines répondant à cette norme.

A.1. Câblage et interconnexion

Si le lecteur le souhaite, des exemples applicatifs d’interconnexions sont donnés au chapitre Autres Services « Câblage & Configuration » de notre site internet.


5

Chapitre B Interface PCI

B.1. Avertissements

La carte PCI 104-DIO est une carte qui s’insère dans une machine possédant des connecteurs PCI 32 bits à la norme PCI 104. Elle présente de ce fait toutes les caractéristiques liées à cet environnement.

PCI 104 spécification Version 1.0

Novembre 2003 L’interface PCI est assurée par un composant spécialisé : AMCC S5335

B.2. Littérature Nous recommandons vivement au lecteur de se procurer la littérature suivante :

PCI HARDWARE and SOFTWARE

Architecture et Design Written by Edward SOLARI et George WILLSE

Edit. : ANNA BOOKS

ET

AMCC

PCI CONTROLLERS S5335

DATA BOOK


6

B.3. Registres de configuration PCI

PCI Configuration Space Header

0004080C1014181C2024282C3034383C

31 2324 16 15 8 7

LATENCY TIMER

INTERRUPT PINMIN_GNTMAX_LAT INTERRUPT LINE

EXPANSION ROM BASE ADDRESS

HEADER TYPE = 0BASE ADDRESS REGISTER #0BASE ADDRESS REGISTER #1BASE ADDRESS REGISTER #2BASE ADDRESS REGISTER #3BASE ADDRESS REGISTER #4BASE ADDRESS REGISTER #5

RESERVED = 0'sRESERVED = 0's

RESERVED = 0'sRESERVED = 0's

BISTREV ID

CACHE LINE SIZE

VENDOR IDCOMMAND

DEVICE ID

CLASS CODESTATUS

00

LEGEND

Note: Some registers are a combination of the above. See individual sectionsfor full description.

EPROM IS DATA SOURCE (READ ONLY)

CONTROL FUNCTION

EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT)

EPROM INITIALIZED RAM (CAN BE ALTERED FROM ADD-ON PORT)

HARD-WIRED TO ZEROES


7

Pour la carte PCI 104-DIO, les registres sont configurés comme suit à la mise sous tension :

03 02 01 00

885B 10E8

0 0

0 0A

FFFFFFC0H

FFFFFF80H

00

FFFF0001H

00 00 01 0B

00

00

00

00

00

00

00

3CH

38H

34H

30H

2CH

28H

24H

20H

1CH

18H

14H

10H

08H

04H

00H

D31 D0

0CH

ETAT A LA MST (Mise sous tension)

00

FF 0

PCI 104-DIO – Rev. A – Edition 1 – 26/25 8

885B 10E8

0 0

FF 0 00 0A

FFFFFFC0H

FFFFFF80H

00

00

00

00

00

00

FFFFF0001H

00

00

00 00 01 0B

D31 D0

3CH

38H

34H

30H

2CH

28H

24H

20H

1CH

18H

10H

0CH

08H

04H

00H

64Ko

EPROM of BOOT

AMCC at Power-up

16D Words

PCI OPERATION REGISTER

00H

Abreviations

04H

08H

0CH

10H

14H

18H

20H

24H

28H

2CH

30H

34H

38H

3CH

NU PCI 104-DIO

NU PCI 104-DIO

NU PCI 104-DIO

NU PCI 104-DIO

Incoming Mailbox Register 1

NU PCI 104-DIO

NU PCI 104-DIO

NU PCI 104-DIO

NU PCI 104-DIO

NU PCI 104-DIO

NU PCI 104-DIO

NU PCI 104-DIO

NU PCI 104-DIO

Mailbox Empty/Full status

Interrupt Control/Status Register

Bus Master Control/Status Register

IMB1

MBEF

INTCSR

MCSR

CONFIGURATION PCI 104-DIO

00

PCI CONFIGURATION REGISTER

14H

1CH

D31 D0 Base +0 Lecture/Ecriture locales PCI 104-DIO Groupe 0 R/W +4 Lecture/Ecriture locales PCI 104-DIO Groupe 1 R/W +8 Lecture/Ecriture locales PCI 104-DIO Groupe 2 R/W +C Lecture/Ecriture locales PCI 104-DIO Groupe 3 R/W +10 Lecture/Ecriture locales PCI 104-DIO Groupe 4 R/W +14 Lecture/Ecriture locales PCI 104-DIO Groupe 5 R/W +18 Lecture/Ecriture locales PCI 104-DIO Groupe 6 R/W +1C Lecture/Ecriture locales PCI 104-DIO Groupe 7 R/W +20 Readback STB 624 Groupe 0 RO +24 Readback STB 624 Groupe 1 RO +28 Readback STB 624 Groupe 2 RO +2C Readback STB 624 Groupe 3 RO +30 Readback STB 624 Groupe 4 RO +34 Readback STB 624 Groupe 5 RO +38 Readback STB 624 Groupe 6 RO +3C Readback STB 624 Groupe 7 RO +40 Readload STB 624 Groupe 0 RO +44 Readload STB 624 Groupe 1 RO +48 Readload STB 624 Groupe 2 RO +4C Readload STB 624 Groupe 3 RO +50 Readload STB 624 Groupe 4 RO +54 Readload STB 624 Groupe 5 RO +58 Readload STB 624 Groupe 6 RO +5C Readload STB 624 Groupe 7 RO

Défaut groupe Busy groupe Mask IT G +60 7 0 7 0 7 0

0 C1C0 R/W

Cde chargt Groupe +64

7 0 WO

Cde relecture sortie groupe +68

7 0 WO

+6C Cde Initialisation Générale (8 groupes simultanés) WO

PCI 104-DIO – Rev. A – Edition 1 – 26/25 9

Seuls les registres « PCI Opération Register » sont utilisés. Le registre MCSR (3CH) Il sert à initialiser la carte PCI 104-DIO (initialisation logiciel). Le bit D24 du registre positionné à « 1 » réinitialise la carte PCI 104-DIO. Le registre IMB1 (10H) Il est écrit par la carte PCI 104-DIO lorsqu’un défaut apparaît. (Ecriture dans la Mailbox 1 de la valeur FFFFFFFFH). Le registre MBEF (34H) Il s’agit du registre de status des Mailbox. Lorsque la carte PCI 104-DIO écrit dans la Mailbox 1, le registre MBEF passe à la valeur 000F0000H. Le fait de lire le registre IMB1 (10H) remet le registre de status MBEF à la valeur 0. Le registre INTCSR (38H) Il sert à gérer les interruptions (facultatif). La source d’interruption ne peut être que l’incoming Mailbox 1. Les bits D12 à D8 et les bits D17 à D23 sont les seuls utiles dans l’utilisation de la carte PCI 104-DIO (mode esclave).


10

Chapitre C Cartographie PCI 104-DIO

D31 D0 Base +0 Lecture/Ecriture locales PCI 104-DIO Groupe 0 R/W +4 Lecture/Ecriture locales PCI 104-DIO Groupe 1 R/W +8 Lecture/Ecriture locales PCI 104-DIO Groupe 2 R/W +C Lecture/Ecriture locales PCI 104-DIO Groupe 3 R/W +10 Lecture/Ecriture locales PCI 104-DIO Groupe 4 R/W +14 Lecture/Ecriture locales PCI 104-DIO Groupe 5 R/W +18 Lecture/Ecriture locales PCI 104-DIO Groupe 6 R/W +1C Lecture/Ecriture locales PCI 104-DIO Groupe 7 R/W +20 Readback STB 624 Groupe 0 RO +24 Readback STB 624 Groupe 1 RO +28 Readback STB 624 Groupe 2 RO +2C Readback STB 624 Groupe 3 RO +30 Readback STB 624 Groupe 4 RO +34 Readback STB 624 Groupe 5 RO +38 Readback STB 624 Groupe 6 RO +3C Readback STB 624 Groupe 7 RO +40 Readload STB 624 Groupe 0 RO +44 Readload STB 624 Groupe 1 RO +48 Readload STB 624 Groupe 2 RO +4C Readload STB 624 Groupe 3 RO +50 Readload STB 624 Groupe 4 RO +54 Readload STB 624 Groupe 5 RO +58 Readload STB 624 Groupe 6 RO +5C Readload STB 624 Groupe 7 RO

Défaut groupe Busy groupe Mask IT G +60 7 0 7 0 7 0

0 C1C0 R/W

Cde chargement Groupe +64 7 0 WO

Cde relecture sortie groupe +68

7 0 WO

+6C Cde Initialisation Générale (8 groupes simultanés) 32 WO

Nota : RW Lecture / Ecriture RO Lecture uniquement WO Ecriture uniquement


11

>>>Registres de commande – Adresses base +0H à base +1CH

Accès 32 bits Registre d’écriture de bits de groupe avec possibilité de relecture locale. Le fait d’écriture dans un registre transfère le mot vers le bornier considéré.

>>>Registres readback STB – Adresses base +20H à base +3CH Accès 32 bits Registre de lecture des mots en retour de bornier, suite à une écriture de mots en base +0H à 1FH, la valeur lue est la valeur chargée sur le STB 624 dans le registre tampon avant le chargement.

>>>Registres readload STB – Adresse base +40H à +5CH Accès 32 bits Registre de lecture des mots en retour de bornier, suite à une commande de relecture base + 68H, la valeur lue est la valeur de sortie du STB 624.

>>>Registres de contrôle – Adresse base +60H Accès 32 bits

D31 D24 D23 D16 D15 D8 D7 D2 D1 D0

7 Défaut Groupe 0 7 Busy Groupe 0 7 Mask IT Groupe 0 0 C1 C0

Bits D0 à D1 : Les deux signaux C0 – C1 de codage de l’adresse PCI 104 de la carte sont lisibles par ces 2 bits

C1 C0

0 0 Carte emplacement 1 (switch S1 sur position 1) 0 1 Carte emplacement 2 (switch S1 sur position 2) 1 0 Carte emplacement 3 (switch S1 sur position 3) 1 1 Carte emplacement 4 (switch S1 sur position 4)

Bits D2 à D7 : Non utilisés, lus à zéro


12

Bits D8 à D15 : Masque Interruption des groupes D8 à D15 correspondent respectivement aux groupes 0 à 7. Lorsqu’un défaut apparaît, une interruption peut être générée si le masque du groupe correpondant est à « 1 ». Bits D16 à D23 : Bits signalant l’occupation (Busy) du groupe correspondant. D16 à D23 correspondent respectivement aux groupes 0 à 7. Les bits « Busy » passent à « 1 » lors de l’écriture des registres de groupe, (base +0 à +1CH), lors de commande de readbacks (base +48H), ou d’initialisation (base +4CH). Les bits « Busy » repassent à « 0 » en fin de séquence (c’est-à-dire lorsque l’information trame retour est validée). Bits D24 à D31 : Bits signalant un défaut sur le groupe correspondant. D24 à D31 correspondent respectivement aux groupes 0 à 7. Les défauts sont caractérisés par deux événements

- Le bornier STB ne répond pas - La trame retour ne correspond pas à la trame envoi lors de

l’écriture d’un groupe


13

>>>Registres de commande de chargement des STB 624 – base +64H

Accès 32 bits – Seuls les 8 bits D7 => D0 sont utiles

D31 D8 D7 D0

G7 G0

Un bit à « 1 » permet de changer le mot du groupe correspondant sur le bornier STB 624. On peut ainsi changer les sorties des borniers STB 624 de manière isochrones ; les valeurs ayant été transférées lors des écritures dans les registres Base +0 à +1CH. La commande de chargement est mémorisée et différée si le transfert du mot n’est pas terminé (Busy).

>>>Registres de commande de Relecture des sorties – base +68H Accès 32 bits – Seuls les 8 bits D7 => D0 sont utiles

D31 D8 D7 D0

G7 G0

Un bit à « 1 » permet de lancer la lecture de l’état des sorties du STB 624 correspondant au groupe. La donnée est disponible lorsque le status Busy du groupe est repositionné à « 0 ». L’information lue est la valeur en sortie du STB 624.

>>>Commande d’initialisation générale – Base +6CH Accès 32 bits Une écriture fictive à cette adresse réinitialise la carte PCI 104-DIO. Les valeurs sont transmises aux borniers STB 624 puis chargées. Les sorties puissances sont à l’état repos.


14

Chapitre D Fonctionnement

D.1. Principe d’échanges La carte PCI 104-DIO est conçue pour gérer les borniers STB 624. La carte PCI 104-DIO comporte 8 groupes de 32 bits soit 256 entrées/sorties TORs. Ces 256 bits de commande I/O répartis en 8 groupes de 32 bits sont transmis vers 8 borniers STB 624 comportant chacun 32 voies de commutation de puissance. Chaque groupe est indépendant. Lors d’une écriture 32 bits dans le registre (base +0H à +1CH) correspondant, le mot de 32 bits est transféré sous forme de trame série PCM (NRZL + CLK) vers le bornier STB 624. La trame transmise vers le bornier STB 624 est mémorisée par celui-ci et est renvoyée vers la carte PCI 104-DIO. Chaque trame transmise est comparée à son écho, si la comparaison n’est pas valide, un défaut est signalé. L’écho est chargé dans le registre base +20 à +3CH. Les trames mémorisées dans le bornier STB 624 seront chargées dans les registres de sorties lors de la commande de chargement (load). Les voies peuvent donc être isochrones. Une commande de relecture des registres de sorties peut être effectuée afin de vérifier l’état de chaque bit au plus près du process. Les valeurs relues sont chargées dans les registres base +40H à +5CH. Une commande d’initialisation permet de mettre les borniers STB 624 à l’état repos (commande de puissance non active). Cette commande transfère simultanément une trame « 0 » dans chaque groupe ; le chargement des registres de sortie est automatique. Les registres de la carte PCI 104-DIO sont détaillés dans le chapitre C.


15

D.2. Synoptique d’un canal

GROUPE 0

Interface

PCI

Comparateur Trames

Data à

MUX 4 :1

MUX 4 :1

PROM

Désérialisation

Sérialisation

Défaut

à

3,3V

3,3V LD (31:0)

LD (31:0)

PCI 104

+5V

GROUPES 1 A 7

Clock

Synchro écriture

Synchro lecture

+ chargement

PCM = NRZL + CLK

Registre sortie

Registre entrée Registre readback

Commandes

CLK REQ IDsel GNT

Registre readload

à

0

1CH

20H

3CH

40H

5CH


16

Chapitre E Alimentation

La carte PCI 104-DIO nécessite les tensions + 3,3V/A et + 5V/A issues du Bus PCI 104.


17

Chapitre F Mise en oeuvre

F.1. Installation

Avant toute chose, l’opérateur prendra connaissance du document consultable en ligne sur notre site internet au chapitre Autres Services « Mise en Œuvre » :

GENERAL INSTRUCTIONS FOR IMPLEMENTING ADAS PRODUCTS

INSTRUCTIONS GENERALES DE MISE EN OEUVRE DES PRODUITS ADAS

La carte PCI 104-DIO devra être installée dans un châssis équipé PCI 104. Les cartes doivent être enlevées ou insérées dans le châssis hors tension. Veiller aux problèmes d'électricité statique lorsque la carte est sortie de son sachet antistatique.

F.2. Sélection du numéro de carte Le switch permet de sélectionner la position de la carte dans l’emplacement prévu sur le PCI 104

Carte emplacement 1 Switch en position 1 Carte emplacement 2 Switch en position 2 Carte emplacement 3 Switch en position 3 Carte emplacement 4 Switch en position 4

1 2 3

4


18

Chapitre G Connectique Les entrées / sorties des liaisons séries s’effectuent par 4 connecteurs HE10P / 20 pts. CONNECTEURS CANAUX

P1 Canal 0 (V0 / V31) ; Canal 1 (V32 / V63) P2 Canal 2 (V64 / V95) ; Canal 3 (V96 / V127) P3 Canal 4 (V128 / V159) ; Canal 5 (V160 / V191) P4 Canal 6 (V192 / V223) ; Canal 7 (V224 / V255)

HE10P / 20 pts

BROCHE SIGNAL BROCHE SIGNAL 1 CLK2 (-) 2 SR2 (-) 3 CLK2 (+) 4 SR2 (+) 5 0V 6 DATA2 (-) 7 SW2 (-) 8 DATA2 (+) 9 SW2 (+) 10 CLK1 (-) 11 SR1 (-) 12 CLK1 (+) 13 SR1 (-) 14 0V 15 DATA1 (-) 16 SW1 (-) 17 DATA1 (+) 18 SW1 (+) 19 NC 20 NC


19

Equivalence en DE 9S d’un canal

DE9S

BROCHE SIGNAL BROCHE SIGNAL

1 SYN WRITE (+)

6 DATA (+)

2 SYN WRITE (-)

7 DATA (-)

3 GND

8 SYN READ (+)

4 CLK (+)

9 SYN READ (-)

5 CLK (-)


20

Chapitre H Borniers de conditionnement

La carte PCI 104-DIO a été étudiée pour être couplée au bornier STB 624. Une carte PCI 104-DIO peut gérer 8 borniers STB 624 soit 256 sorties relais.


21

Annexe

PLAN DE CONFIGURATION

PLAN D’EQUIPEMENT

REGISTRES DE CONFIGURATION PCI

PCI 104-DIO

22

NOTE AU LECTEUR Ce chapitre est laissé volontairement en anglais afin de garder les termes utilisés dans la norme PCI.

Configuration Abbreviation Register NameAddress Offset

00h–01h VID Vendor Identification02h–03h DID Device Identification04h–05h PCICMD PCI Command Register06h–07h PCISTS PCI Status Register08h RID Revision Identification Register09h–0Bh CLCD Class Code Register0Ch CALN Cache Line Size Register0Dh LAT Master Latency Timer0Eh HDR Header Type0Fh BIST Built-in Self-test10h–27h BADR0-BADR5 Base Address Registers (0-5)28h–2Fh — Reserved30h EXROM Expansion ROM Base Address34h–3Bh — Reserved3Ch INTLN Interrupt Line3Dh INTPIN Interrupt Pin3Eh MINGNT Minimum Grant3Fh MAXLAT Maximum Latency40h–FFh — Not used

PCI CONFIGURATION REGISTERSEach PCI bus device contains a unique 256-byte region called its configuration header space. Portions of thisconfiguration header are mandatory in order for a PCI agent to be in full compliance with the PCI specification.This section describes each of the configuration space fields—its address, default values, initialization options,and bit definitions—and also provides an explanation of its intended usage.

PCI 104-DIO

23

VENDOR IDENTIFICATION REGISTER (VID)Register Name: Vendor IdentificationAddress Offset: 00h-01hPower-up value: 10E8h (AMCC, Applied Micro

Circuits Corp.)Boot-load: External nvRAM offset

040h-41hAttribute: Read Only (RO)Size: 16 bits

The VID register contains the vendor identificationnumber. This number is assigned by the PCI SpecialInterest Group and is intended to uniquely identifyany PCI device. Write operations from the PCI inter-face have no effect on this register. After reset isremoved, this field can be boot-loaded from the ex-ternal non-volatile device (if present and valid) so thatother legitimate PCI SIG members can substitute theirvendor identification number for this field.

Bit Description

15 010E8h

Vendor Identification Register (RO)

15:0 Vendor Identification Number: This is a 16 bit-value assigned to AMCC.

PCI 104-DIO

24

PCI CONFIGURATION REGISTERS

DEVICE IDENTIFICATION REGISTER (DID) Register Name: Device Identification Address Offset: 02h-03h Power-up value: 4750h (ASCII hex for ‘GP’,

General Purpose) Boot-load: External nvRAM offset

042h-43h Attribute: Read Only Size: 16 bits

15 0

Device Identification Register (RO)

8850

Bit Description

15:0 Device Identification Number: This is a 16-bit value initially assigned by AMCC to ADAS applications for PCI 104-DIO card.

The DID register contains the vendor-assigned deviseidentification number. This number is generated by AMCCin compliance with the conditions of the PCI specification.Write operations from the PCI interface have no effect onthis register. After reset is removed, this field can be boot-loaded from the external non-volatile device (if present andvalid) so that other legitimate PCI SIG members cansubstitute their own device identification number for thisfield.

PCI 104-DIO

25

PCI COMMAND REGISTERRegister Name: PCI CommandAddress Offset: 04h-05hPower-up value: 0000hBoot-load: not usedAttribute: Read/Write (R/W on 6 bits,

Only for all others)Size: 16 bits

This 16-bit register contains the PCI Command. Thefunction of this register is defined by the PCI specifi-cation and its implementation is required of all PCIdevices. Only six of the ten fields are used by thisdevice; those which are not used are hardwired to 0.The definitions for all fields are provided here forcompleteness.

15 0

Reserved = 00's

Fast Back-to-BackSERREWait Cycle EnableParity Error EnablePalette SnoopMemory Write and InvalidateSpecial Cycle EnableBus Master EnableMemory AccessI/O Access Enable

X 00 X 0 0 0 XXX

123456789

PCI 104-DIO

26

15:10 Reserved. Equals all 0’s.

9 Fast Back-to-Back Enable. The S5933 does not support this function. This bit must be set to zero.This bit is cleared to a 0 upon RESET#.

8 System Error Enable. When this bit is set to 1, it permits the S5933 controller to drive the open drainoutput pin, SERR#. This bit is cleared to 0 upon RESET#. The SERR# pin driven active normallysignifies a parity error on the address/control bus.

7 Wait Cycle Enable. This bit controls whether this device does address/data stepping. Since the S5933controller never uses stepping, it is hardwired to 0.

6 Parity Error Enable. This bit, when set to a one, allows this controller to check for parity errors. Whena parity error is detected, the PCI bus signal PERR# is asserted. This bit is cleared (parity testingdisabled) upon the assertion of RESET#.

5 Palette Snoop Enable. This bit is not supported by the S5933 controller and is hardwired to 0. Thisfeature is used solely for PCI-based VGA devices.

4 Memory Write and Invalidate Enable. This bit allows certain Bus Master devices to use the MemoryWrite and Invalidate PCI bus command when set to 1. When set to 0, masters must use the MemoryWrite command instead. The S5933 controller does not support this command when operated as amaster and therefore it is hardwired to 0.

3 Special Cycle Enable. Devices which are capable of monitoring special cycles can do so when thisbit is set to 1. The S5933 controller does not monitor (or generate) special cycles and this bit ishardwired to 0.

2 Bus Master Enable. This bit, when set to a one, allows the S5933 controller to function as a bus master.This bit is initialized to 0 upon the assertion of signal pin RESET#.

1 Memory Space Enable. This bit allows the S5933 controller to decode and respond as a target formemory regions that may be defined in one of the five base address registers. This bit is initializedto 0 upon the assertion of signal pin RESET#.

0 I/O Space Enable. This bit allows the S5933 controller to decode and respond as a target to I/O cycleswhich are to regions defined by any one of the five base address registers. This bit is initialized to 0upon the assertion of signal pin RESET#.

Bit Description

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27

PCI STATUS REGISTER (PCISTS)

Register Name: PCI Status

Address Offset: 06h-07h

Power-up value: 0080hBoot-load: not usedAttribute: Read Only (RO), Read/Write

Clear (R/WC)Size: 16 bits

7 0

X00XXX

6

XX

Reserved (RO)

Signaled Target Abort (R/WC)Received Target Abort (R/WC)Received Master Abort (R/WC)Signaled System Error (R/WC)Detected Parity Error (R/WC)

0

15 14 13 12 11 10 9 8

Reserved (RO) = 00's

Fast Back-to-Back (RO)Data Parity Reported (R/WC)

DEVSEL# Timing Status (RO) 0 0 = Fast (S5933) 0 1 = Medium 1 0 = Slow 1 1 = Reserved

This 16-bit register contains the PCI status informa-tion. The function of this register is defined by thePCI specification and its implementation is requiredof all PCI devices. Only some of the bits are used bythis device; those which are not used are hardwiredto 0. Most status bits within this register are desig-nated as “write clear,” meaning that in order to cleara given bit, the bit must be written as a 1. All bitswritten with a 0 are left unchanged. These bits areidentified in Figure 4 as (R/WC). Those which areRead Only are shown as (RO) in Figure 4.

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Bit Description

15 Detected Parity Error. This bit is set whenever a parity error is detected. It functions independentlyfrom the state of Command Register Bit 6. This bit may be cleared by writing a 1 to this location.

14 Signaled System Error. This bit is set whenever the device asserts the signal SERR#. This bit can bereset by writing a 1 to this location.

13 Received Master Abort. This bit is set whenever a bus master abort occurs. This bit can be reset bywriting a 1 to this location.

12 Received Target Abort. This bit is set whenever this device has one of its own initiated cyclesterminated by the currently addressed target. This bit can be reset by writing a 1 to this location.

11 Signaled Target Abort. This bit is set whenever this device aborts a cycle when addressed as a target.This bit can be reset by writing a 1 to this location.

10:9 Device Select Timing. These bits are read-only and define the signal behavior of DEVSEL# from thisdevice when accessed as a target.

8 Data Parity Reported. This bit is set upon the detection of a data parity error for a transfer involvingthe S5933 device as the master. The Parity Error Enable bit (D6 of the Command Register) must beset in order for this bit to be set. Once set, it can only be cleared by either writing a 1 to this locationor by the assertion of the signal RESET#.

7 Fast Back-to-back Capable. When equal to 1, this indicates that the device can accept fast back-to-back cycles as a target.

6:0 Reserved. Equal all 0’s.

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29

REVISION IDENTIFICATION REGISTER (RID)Register Name: Revision IdentificationAddress Offset: 08hPower-up value: 00hBoot-load: External nvRAM/EPROM offset

048hAttribute: Read OnlySize: 8 bits

The RID register contains the revision identificationnumber. This field is initially cleared. Write operationsfrom the PCI interface have no effect on this register.After reset is removed, this field can be boot-loadedfrom the external non-volatile device (if present andvalid) so that another value may be used.

Bit Description

7:0 Revision Identification Number. Initialized to zeros, this register may be loaded to the value in non-volatile memory at offset 048h.

7 000h

Revision Identification Number (RO)

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CLASS CODE REGISTER (CLCD)Register Name: Class CodeAddress Offset: 09h-0BhPower-up value: FF0000hBoot-load: External nvRAM offset

049h-4BhAttribute: Read OnlySize: 24 bits

This 24-bit, read-only register is divided into threeone-byte fields: the base class resides at location0Bh, the sub-class at 0Ah, and the programming in-terface at 09h. The default setting for the base classis all ones (FFh), which indicates that the devicedoes not fit into the thirteen base classes defined inthe PCI Local Bus Specification. It is possible, how-ever, through use of the external non-volatilememory, to implement one of the defined class codesdescribed in Table 7 below.

For devices that fall within the seven defined classcodes, sub-classes are also assigned. Tables 8through 20 describe each of the sub-class codes forbase codes 00h through 0Ch, respectively.

7 0Sub-Class

7070Base Class Prog I/F

(Bit)(Offset)@09h@0Ah@0Bh

Base-Class Description

00h Early, pre-2.0 PCI specification devices

01h Mass storage controller

02h Network controller

03h Display controller

04h Multimedia device

05h Memory controller

06h Bridge device

07h Simple communication controller

08h Base system peripherals

09h Input devices

0Ah Docking stations

0Bh Processors

0Ch Serial bus controllers

0D-FEh Reserved

FFh Device does not fit defined class codes (default)

Sub-Class Prog I/F Description

00h 00h All devices other than VGA

01h 00h VGA-compatible device

PCI 104-DIO

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00h 00h RAM memory controller

01h 00h Flash memory controller

80h 00h Other memory controller


00h 00h SCSI controller

01h xxh IDE controller

02h 00h Floppy disk controller

03h 00h IPI controller

04h 00h RAID controller

80h 00h Other mass storage controller


00h 00h Ethernet controller

01h 00h Token ring controller

02h 00h FDDI controller

03h 00h ATM controller

80h 00h Other network controller


00h 00h VGA-compatible controller

00h 01h 8514 compatible controller

01h 00h XGA controller

80h 00h Other display controller


00h 00h Video device

01h 00h Audio device

80h 00h Other multimedia device

PCI 104-DIO

32


00h 00h Host/PCI bridge

01h 00h PCI/ISA bridge

02h 00h PCI/EISA bridge

03h 00h PCI/Micro Channel bridge

04h 00h PCI/PCI bridge

05h 00h PCI/PCMCIA bridge

06h 00h NuBus bridge

07h 00h CardBus bridge

80h 00h Other bridge type


00h 00h Generic XT compatible serial controller

01h 16450 compatible serial controller

02h 16550 compatible serial controller

01h 00h Parallel port

01h Bidirectional parallel port

02h ECP 1.X compliant parallel port

80h 00h Other communications device


00h 00h Generic 8259 PIC

01h ISA PIC

02h EISA PIC

01h 00h Generic 8237 DMA controller

01h ISA DMA controller

02h EISA DMA controller

02h 00h Generic 8254 system timer

01h ISA system timer

02h EISA system timers (2 timers)

03h 00h Generic RTC controller

01h ISA RTC controller

80h 00h Other system peripheral

PCI 104-DIO

33


00h 00h Keyboard controller

01h 00h Digitizer (Pen)

02h 00h Mouse controller

80h 00h Other input controller


00h 00h Generic docking station

80h 00h Other type of docking station


00h 00h Intel386™

01h 00h Intel486™

02h 00h Pentium™

10h 00h Alpha™

40h 00h Co-processor


00 00h FireWire™ (IEEE 1394)

01h 00h ACCESS.bus

02h 00h SSA

PCI 104-DIO

34

CACHE LINE SIZE REGISTER (CALN)Register Name: Cache Line SizeAddress Offset: 0ChPower-up value: 00h, hardwiredBoot-load: not usedAttribute: Read OnlySize: 8 bits

This register is hardwired to 0. The cache line con-figuration register is used by the system to define thecache line size in doubleword (64-bit) increments.This controller does not use the “Memory Write andInvalidate” PCI bus cycle commands when operatingin the bus master mode, and therefore does not inter-nally require this register. When operating in the tar-get mode, this controller does not have theconnections necessary to “snoop” the PCI bus andaccordingly cannot employ this register in the detec-tion of burst transfers that cross a line boundary.

7 000h

Cache Line Size (RO)

LATENCY TIMER REGISTER (LAT)Register Name: Latency TimerAddress Offset: 0DhPower-up value: 00hBoot-load: External nvRAM offset

04DhAttribute: Read/Write, bits 7:3;

Read Only bits 2:0Size: 8 bits

The latency timer register has meaning only whenthis controller is used as a bus master and pertains tothe number of PCI bus clocks that this master will beguaranteed. The nonzero value for this register isinternally decremented after this device has beengranted the bus and has begun to assert FRAME#.Prior to this latency timer count reaching zero, thisdevice can ignore the removal of the bus grant andmay continue the use of the bus for data transfers.

7 0

Latency Timer value (R/W)# of clocks x 8

0

1

0

2

0

3

X

4

X

5

X

6

XX

Bit

Value

PCI 104-DIO

35

HEADER TYPE REGISTER (HDR)Register Name: Header TypeAddress Offset: 0EhPower-up value: 00hBoot-load: External nvRAM offset

04EhAttribute: Read OnlySize: 8 bits

This register consists of two fields: Bits 6:0 define theformat for bytes 10h through 3Fh of the device con-figuration header, and bit 7 establishes whether thisdevice represents a single function (bit 7 = 0) or amultifunction (bit 7 = 1) PCI bus agent. The S5933 isa single function PCI device.

7 0

Single/Multi-function device (Read Only)0 = single function1 = multi-function

123456

X

Bit

Value00h

Format field (Read Only)

PCI 104-DIO

36

BUILT-IN SELF-TEST REGISTER (BIST)Register Name: Built-in Self-TestAddress Offset: 0FhPower-up value: 00hBoot-load: External nvRAM/EPROM

offset 04FhAttribute: D7, D5-0 Read Only, D6 as

PCI bus write onlySize: 8 bits

The Built-In Self-Test (BIST) register permits theimplementation of custom, user-specific diagnostics.This register has four fields as depicted in Figure 10.Bit 7, when set signifies that this device supports abuilt-in self test. When bit 7 is set, writing a 1 to bit 6will commence the self test. In actuality, writing a 1 tobit 6 produces an interrupt to the Add-On interface.Bit 6 will remain set until cleared by a write operationto this register from the Add-On bus interface. Whenbit 6 is reset it is interpreted as completion of the self-test and an error is indicated by a non-zero value forthe completion code (bits 3:0).

Bit Description

7 BIST Capable. This bit indicates that the Add-On device supports a built-in self-test when a one isreturned. A zero should be returned if this self test feature is not desired. This field is read onlyfrom the PCI interface.

6 Start BIST. Writing a 1 to this bit indicates that the self-test should commence. This bit can only bewritten when bit 7 is a 1. When bit 6 becomes set, an interrupt is issued to the Add-On interface. Otherthan through the reset pin, Bit 6 can only be cleared by a write to this element from the Add-On businterface as outlined in Section 6.5. The PCI bus specification requires that this bit be cleared within2 seconds after being set, or the device will be failed.

5:4 Reserved. These bits are reserved. This field will always return zeros.

3:0 Completion Code. This field provides a method for detailing a device-specific error. It is consideredvalid when the Start BIST field (bit 6) changes from 1 to 0. An all-zero value for the completion codeindicates successful completion.

7 0

X

1

X

2

X

3

X

4

0

5

0

6

0X

Bit

Value

User definedCompletion Code (RO)

Reserved (RO)

Start BIST (WO)

BIST Capable (RO)

PCI 104-DIO

37

BASE ADDRESS REGISTERS (BADR)Register Name: Base AddressAddress Offset: 10h, 14h, 18h, 1Ch, 20h, 24hPower-up value: FFFFFFC1h for offset 10h;

00000000h for all othersBoot-load: External nvRAM offset

050h, 54h, 58h, 5Ch, 60h(BADR0-4)

Attribute: high bits Read/Write; low bitsRead Only

Size: 32 bits

The base address registers provide a mechanism forassigning memory or I/O space for the Add-On func-tion. The actual location(s) the Add-On function is torespond to is determined by first interrogating theseregisters to ascertain the size or space desired, andthen writing the high-order field of each register toplace it physically in the system’s address space. Bitzero of each field is used to select whether the spacerequired is to be decoded as memory (bit 0 = 0) or I/O(bit 0 = 1). Since this PCI controller has 16 DWORDsof internal operating registers, the Base AddressRegister at offset 10h is assigned to them. The re-maining five base address registers can only be usedby boot-loading them from the external nvRAM inter-face. BADR5 register is not implemented and will re-turn all 0’s.

Determining Base Address SizeThe address space defined by a given base addressregister is determined by writing all 1s to a givenbase address register from the PCI bus and thenreading that register back. The number of 0s returnedstarting from D4 for memory space and D2 for I/Ospace toward the high-order bits reveals the amountof address space desired. Tables 23 and 24 list thepossible returned values and their corresponding sizefor both memory and I/O, respectively. Included inthe table are the nvRAM/EPROM boot values whichcorrespond to a given assigned size. A register re-turning all zeros is disabled.

Assigning the Base Address

After a base address has been sized as described inthe preceding paragraph, the region associated withthat base address register (the high order one bits)can physically locate it in memory (or I/O) space. Forexample, the first base address register returnsFFFFFFC1h indicating an I/O space (D0=1) and isthen written with the value 00000300h. This meansthat the controller’s internal registers can be selectedfor I/O addresses between 00000300h through0000033Fh, in this example. The base address valuemust be on a natural binary boundary for the requiredsize (example 300h, 340h, 380h etc.; 338h would notbe allowable).

31 0

X

1

0

2 Bit

Value

I/O Space Indicator (RO)Reserved (RO)

Programmable (R/W)

31 0

X

1

X

2

X

3

X

4 Bit

Value

Memory Space Indicator (RO)Type (RO) 00-locate anywhere (32) 01-below 1 MB 10-locate anywhere (64) 11-reserved

Programmable (R/W)

Prefetchable (RO)

PCI 104-DIO

38

31:4 Base Address Location. These bits are used to position the decoded region in memory space. Onlybits which return a 1 after being written as 1 are usable for this purpose. Except for Base AddressRegister 0, these bits are individually enabled by the contents sourced from the external boot memory.

3 Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cachableregions can only be located within the region altered through PCI bus memory writes. This bit, whenset, also implies that all read operations will return the data associated for all bytes regardless of theByte Enables. Memory space which cannot support this behavior should leave this bit in the zerostate. For Base Addresses 1 through 4, this bit is set by the Reset pin and later initialized by theexternal boot memory (if present). Base Address Register 0 always has this bit set to 0. This bit is readonly from the PCI interface.

2:1 Memory Type. These two bits identify whether the memory space is 32 or 64 bits wide and if the spacelocation is restricted to be within the first megabyte of memory space. The table below describes theencoding:

Bits Description2 10 0 Region is 32 bits wide and can be located anywhere in 32 bit memory space.

0 1 Region is 32 bits wide and must be mapped below the first MByte of memory space.

1 0 Region is 64 bits wide and can be mapped anywhere within 64 bit memory space.(Not supported by this controller.)

1 1 Reserved. (Not supported by this controller.)

1 The 64-bit memory space is not supported by this controller, so bit 2 should not be set. The onlymeaningful option is whether it is desired to position memory space anywhere within 32-bit memoryspace or restrain it to the first megabyte. For Base Addresses 1 through 5, this bit is set by the resetpin and later initialized by the external boot memory (if present).

0 Space Indicator = 0. When set to 0, this bit identifies a base address region as a memory space andthe remaining bits in the base address register are defined as shown in Table 22a.

Bit Description

Bit Description

31:2 Base Address Location. These bits are used to position the decoded region in I/O space. Only bitswhich return a “1” after being written as “1” are usable for this purpose. Except for Base Address 0,these bits are individually enabled by the contents sourced from the external boot memory (EPROMor nvRAM).

1 Reserved. This bit should be zero. (Note: disabled Base Address Registers will return all zeros for theentire register location, bits 31 through 0).

0 Space Indicator = 1. When one this bit identifies a base address region as an I/O space and theremaining bits in the base address register have the definition as shown in Table 11b.

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39

Response Size in bytes [EPROM boot value] 1

00000000h none - disabled 00000000h orBIOS missing 2,3

FFFFFFF0h 16 bytes (4 DWORDs) FFFFFFF0h

FFFFFFE0h 32 bytes (8 DWORDs) FFFFFFE0h

FFFFFFC0h 64 bytes (16 DWORDs) FFFFFFC0h

FFFFFF80h 128 bytes (32 DWORDs) FFFFFF80h


FFFFFE00h 512 bytes (128 DWORDs) FFFFFE00h

FFFFFC00h 1K bytes (256 DWORDs) FFFFFC00h

FFFFF800h 2K bytes (512 DWORDs) FFFFF800h

FFFFF000h 4K bytes (1K DWORDs) FFFFF000h

FFFFE000h 8K bytes (2K DWORDs) FFFFE000h

FFFFC000h 16K bytes (4K DWORDs) FFFFC000h

FFFF8000h 32K bytes (8K DWORDs) FFFF8000h


FFFE0000h 128K bytes (32K DWORDs) FFFE0000h

FFFC0000h 256K bytes (64K DWORDs) FFFC0000h

FFF80000h 512K bytes (128K DWORDs) FFF80000h

FFF00000h 1M bytes (256K DWORDs) FFF00000h

FFE00000h 2M bytes (512K DWORDs) FFE00000h

FFC00000h 4M bytes (1M DWORDs) FFC00000h

FF800000h 8M bytes (2M DWORDs) FF800000h

FF000000h 16M bytes (4M DWORDs) FF000000h

FE000000h 32M bytes (8M DWORDs) FE000000h

FC000000h 64M bytes (16M DWORDs) FC000000h

F8000000h 128M bytes (32M DWORDs) F8000000h

F0000000h 256M bytes (64M DWORDs) F0000000h

E0000000h 512M bytes (128M DWORDs) E0000000h

1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation).2. Bits D3, D2 and D1 may be set to indicate other attributes for the memory space. See text for details.3. BADR5 register is not implemented and will return all 0’s.

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Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or

BIOS missing 3

FFFFFFFDh 4 bytes (1 DWORDs) FFFFFFFDh



FFFFFFE1h 32 bytes (8 DWORDs) FFFFFFE1h

FFFFFFC1h 64 bytes (16 DWORDs) FFFFFFC1h 4



4. Base Address Register 0 (at offset) 10h powers up as FFFFFFC1h. This default assignment allows usage without an external bootmemory. Should an EPROM or nvRAM be used, the base address can be boot loaded to become a memory space (FFFFFFC0h orFFFFFFC2h).

PCI 104-DIO

41

EXPANSION ROM BASE ADDRESSREGISTER (XROM)

Register Name: Expansion ROM Base AddressAddress Offset: 30hPower-up value: 00000000hBoot-load: External nvRAM offset

70hAttribute: bits 31:11, bit 0 Read/Write; bits

10:1 Read OnlySize: 32 bits

31 0

00

110 Bit

Value

Address Decode Enable (RW) 0=Disabled 1=EnabledReserved (RO)Programmable (R/W)

11

The expansion base address ROM register providesa mechanism for assigning a space within physicalmemory for an expansion ROM. Access from the PCIbus to the memory space defined by this register willcause one or more accesses to the S5933 control-lers’ external BIOS ROM (or nvRAM) interface. SincePCI bus accesses to the ROM may be 32 bits wide,repeated operations to the ROM are generated bythe S5933 and the wider data is assembled internalto the S5933 controller and then transferred to thePCI bus by the S5933.

Bit Description

31:11 Expansion ROM Base Address Location. These bits are used to position the decoded region inmemory space. Only bits which return a 1 after being written as 1 are usable for this purpose. Thesebits are individually enabled by the contents sourced from the external boot memory (EPROM ornvRAM). The desired size for the ROM memory is determined by writing all ones to this register andthen reading back the contents. The number of bits returned as zeros, in order from least significantto most significant bit, indicates the size of the expansion ROM. This controller limits the expansionROM area to 64K bytes. The allowable returned values after all ones are written to this register areshown in Table 26.

10:1 Reserved. All zeros.

0 Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit.When this bit is set, the decoder is enabled; when this bit is zero, the decoder is disabled. It is requiredthat the PCI command register also have the memory decode enabled for this bit to have an effect.

Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or

BIOS missing

FFFFF801h 2K bytes (512 DWORDs) FFFFF801h

FFFFF001h 4K bytes (1K DWORDs) FFFFF001h

FFFFE001h 8K bytes (2K DWORDs) FFFFE001h

FFFFC001h 16K bytes (4K DWORDs) FFFFC001h



PCI 104-DIO

42

INTERRUPT LINE REGISTER (INTLN)Register Name: Interrupt LineAddress Offset: 3ChPower-up value: FFhBoot-load: External nvRAM offset

7ChAttribute: Read/WriteSize: 8 bit

This register indicates the interrupt routing for theS5933 controller. The ultimate value for this registeris system-architecture specific. For x86 based PCs,the values in this register correspond with the estab-lished interrupt numbers associated with the dual8259 controllers used in those machines. In x86-based PC systems, the values of 0 to 15 correspondwith the IRQ numbers 0 through 15, and the valuesfrom 16 to 254 are reserved. The value of 255 (thecontroller’s default power-up value) signifies either“unknown” or “no connection” for the system inter-rupt. This register is boot-loaded from the externalboot memory, if present, and may be written by thePCI interface.

7 01

FFh

5 Bit

Value

6 4 23

INTERRUPT PIN REGISTER (INTPIN)Register Name: Interrupt PinAddress Offset: 3DhPower-up value: 01hBoot-load: External nvRAM offset

7DhAttribute: Read OnlySize: 8 bits

7 015 Bit

Value

6 4 23

0 0000 XXX

Reserved (all zeroes-RO)

Pin Number 0 0 0 None0 0 1 INTA#0 1 0 INTB#0 1 1 INTC#1 0 0 INTD# 1 0 1 Reserved1 1 X Reserved

This register identifies which PCI interrupt, if any, isconnected to the controller’s PCI interrupt pins. Theallowable values are 0 (no interrupts), 1 (INTA#), 2(INTB#), 3 (INTC#), and 4 (INTD#). The defaultpower-up value assumes INTA#.

PCI 104-DIO

43

MINIMUM GRANT REGISTER (MINGNT)Register Name: Minimum Grant

Address Offset: 3EhPower-up value: 00hBoot-load: External nvRAM offset

7EhAttribute: Read OnlySize: 8 bits

This register may be optionally used by bus mastersto specify how long a burst period the device needs.A value of zero indicates that the bus master has nostringent requirement. The units defined by the leastsignificant bit are in 250-ns increments. This registeris treated as “information only” and has no furtherimplementation within this device.

Values other than zero are possible when an externalboot memory is used.

7 0

Value x 250ns (RO)00-no requirement01-FFh

123456

0

bit

value0 0 0 0 0 0 0

PCI 104-DIO

44

MAXIMUM LATENCY REGISTER (MAXLAT)

Register Name: Maximum LatencyAddress Offset: 3FhPower-up value: 00hBoot-load: External nvRAM offset

7FhAttribute: Read OnlySize: 8 bits

This register may be optionally used by bus mastersto specify how often this device needs PCI bus ac-cess. A value of zero indicates that the bus masterhas no stringent requirement. The units defined bythe least significant bit are in 250-ns increments. Thisregister is treated as “information only” and has nofurther implementation within this device.

Values other than zero are possible when an externalboot memory is used.

7 0

Value x 250ns (RO)00-no requirement01-FFh

123456

0

bit

value0 0 0 0 0 0 0

PCI 104-DIO

45

PCI BUS OPERATION REGISTERS

Address Offset Abbreviation Register Name

00h OMB1 Outgoing Mailbox Register 1



0Ch OMB4 Outgoing Mailbox Register 4

10h IMB1 Incoming Mailbox Register 1



1Ch IMB4 Incoming Mailbox Register 4

20h FIFO FIFO Register port (bidirectional)

24h MWAR Master Write Address Register

28h MWTC Master Write Transfer Count Register

2Ch MRAR Master Read Address Register

30h MRTC Master Read Transfer Count Register

34h MBEF Mailbox Empty/Full Status

38h INTCSR Interrupt Control/Status Register

3Ch MCSR Bus Master Control/Status Register

PCI BUS OPERATION REGISTERSThe PCI bus operation registers are mapped as 16 consecutive DWORD registers located at the address space(I/O or memory) specified by the Base Address Register 0. These locations are the primary method of communi-cation between the PCI and Add-On buses. Data, software-defined commands and command parameters can beeither exchanged through the mailboxes, transferred through the FIFO in blocks under program control, ortransferred using the FIFOs under Bus Master control. Table 1 lists the PCI Bus Operation Registers.

PCI 104-DIO

46

OUTGOING MAILBOX REGISTERS (OMB)Register Names: Outgoing Mailboxes 1-4

PCI Address Offset: 00h, 04h, 08h, 0Ch

Power-up value: XXXXXXXXh

Attribute: Read/Write

Size: 32 bits

These four DWORD registers provide a method forsending command or parameter data to the Add-Onsystem. PCI bus operations to these registers maybe in any width (byte, word, or DWORD). Writing tothese registers can be a source for Add-On bus inter-rupts (if desired) by enabling their interrupt genera-tion through the use of the Add-On’s interrupt control/status register.

INCOMING MAILBOX REGISTERS (IMB)Register Names: Incoming Mailboxes 1-4

PCI Address Offset: 10h, 14h, 18h, 1Ch


Attribute: Read Only

Size: 32 bits

These four DWORD registers provide a method forreceiving user defined data from the Add-On system.PCI bus read operations to these registers may be inany width (byte, word, or DWORD). Only read opera-tions are supported. Reading from these registers canoptionally cause an Add-On bus interrupt (if desired)by enabling their interrupt generation through the useof the Add-On’s interrupt control/status register.

Mailbox 4, byte 3 only exists as device pins on theS5933 devices when used with a serial nonvolatilememory.

This location provides access to the bidirectionalFIFO. Separate registers are used when readingfrom or writing to the FIFO. Accordingly, it is not pos-sible to read what was written to this location. TheFIFO registers are implicitly involved in all bus masteroperations and, as such, should not be accessedduring active bus master transfers. When operatingupon the FIFOs with software program transfers in-volving word or byte operations, the sequenceof the FIFO should be established as described un-der FIFO Endian Conversion Management in order topreserve the internal FIFO data ordering and flagmanagement. The FIFO’s fullness may be observedby reading the master control- status registerorMCSR register.

FIFO REGISTER PORT (FIFO)

Register Name: FIFO Port

PCI Address Offset: 20h


Attribute: Read/Write

Size: 32 bits

PCI 104-DIO

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PCI CONTROLLED BUS MASTER WRITEADDRESS REGISTER (MWAR)Register Name: Master Write AddressPCI Address Offset: 24hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

This register is used to establish the PCI address fordata moving from the Add-On bus to the PCI busduring PCI bus memory write operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MWTC, and must begin on a DWORD boundary.This DWORD boundary starting constraint is placedupon this controller’s PCI bus master transfers sothat byte lane alignment can be maintained betweenthe S5933 controller’s internal FIFO data path, theAdd-On interface, and the PCI bus.

Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.

After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.

The Master Write Address Register is continually up-dated during the transfer process and will always bepointing to the next unwritten location. Reading ofthis register during a transfer process (done when theS5933 controller is functioning as a target, i.e. not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master write transfers, the two leastsignificant bits presented on the PCI bus pinsAD[31:0] will always be zero. This identifies to thetarget memory that the burst address sequence willbe in a linear order rather than in an Intel 486 orPentium™ cache line fill sequence. Also, the PCI busaddress bit A1 will always be zero when this control-ler is the bus master. This signifies to the target thatthe S5933 controller is burst capable and that thetarget should not arbitrarily disconnect after the firstdata phase of this operation.

Under certain circumstances, MWAR can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.

31 0

0

1

0

2 Bit

Value

DWORD Address (RO)

Write Transfer Address (R/W)

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PCI CONTROLLED BUS MASTER WRITETRANSFER COUNT REGISTER (MWTC)Register Name: Master Write Transfer CountPCI Address Offset: 28hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

The master write transfer count register is used toconvey to the S5933 controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIwrite operation until the transfer count reaches zero.

Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.

Under certain circumstances, MWTC can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.

31 025 Bit

Value

Transfer Count in Bytes (R/W)Reserved = O's (RO)

26

00

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PCI CONTROLLED BUS MASTER READADDRESS REGISTER (MRAR)Register Name: Master Read AddressPCI Address Offset: 2ChPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

This register is used to establish the PCI address fordata moving to the Add-On bus from the PCI busduring PCI bus memory read operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MRTC (Section 5.7) and must begin on a DWORDboundary. This DWORD boundary starting constraintis placed upon this controller’s PCI bus master trans-fers so that byte lane alignment can be maintainedbetween the S5933 controller’s internal FIFO datapath, the Add-On interface and the PCI bus.

Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.

After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.

The Master Read Address Register is continually up-dated during the transfer process and will always bepointing to the next unread location. Reading of thisregister during a transfer process (done when theS5933 controller is functioning as a target—i.e., not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master read transfers, the two leastsignificant bits presented on the PCI bus AD[31:0]will always be zero. This identifies to the targetmemory that the burst address sequence will be in alinear order rather than in an Intel 486 or Pentium™cache line fill sequence. Also, the PCI bus addressbit A1 will always be zero when this controller is thebus master. This signifies to the target that the con-troller is burst capable and that the target should notarbitrarily disconnect after the first data phase of thisoperation.

Under certain circumstances, MRAR can be ac-cessed from the Add-On bus instead of the PCI bus.

31 0

0

1

0

2 Bit

Value

DWORD Address (RO)

Read Transfer Address (R/W)

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PCI CONTROLLED BUS MASTER READTRANSFER COUNT REGISTER (MRTC)

Register Name: Master Read Transfer CountPCI Address Offset: 30hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

The master read transfer count register is used toconvey to the PCI controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIread operation until the transfer count reaches zero.Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.

Under certain circumstances, MRTC can be ac-cessed from the Add-On bus instead of the PCI bus.

31 025 Bit

Value

Transfer Count in Bytes (R/W)Reserved = 0's (RO)

26

00

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MAILBOX EMPTY FULL/STATUSREGISTER (MBEF)

Register Name: Mailbox Empty/Full Status

PCI Address Offset: 34h

Power-up value: 00000000h

Attribute: Read Only

Size: 32 bits

This register provides empty/full visibility of each bytewithin the mailboxes. The empty/full status for theOutgoing mailboxes is displayed on the low-order 16bits and the empty/full status for the Incoming mail-boxes is presented on the high-order 16 bits. A valueof 1 signifies that a given mailbox has been written byone bus interface but has not yet been read by thecorresponding destination interface. A PCI bus in-coming mailbox is defined as one in which data trav-els from the Add-On bus into the PCI bus, and anoutgoing mailbox is defined as one where data trav-els out from the PCI bus to the Add-On interface.

31 015 Bit

Value

Outgoing MailboxStatus (RO)Incoming Mailbox Status (RO)

16

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Bit Description

31:16 Incoming Mailbox Status. This field indicates which incoming mailbox registers have been writtenby the Add-On interface but have not yet been read by the PCI bus. Each bit location corre-sponds to a specific byte within one of the four incoming mailboxes. A value of one for each bitsignifies that the specified mailbox byte is full, and a value of zero signifies empty. The mappingof these status bits to bytes within each mailbox is as follows:

Bit 31 = Incoming mailbox 4 byte 3Bit 30 = Incoming mailbox 4 byte 2Bit 29 = Incoming mailbox 4 byte 1Bit 28 = Incoming mailbox 4 byte 0Bit 27 = Incoming mailbox 3 byte 3Bit 26 = Incoming mailbox 3 byte 2Bit 25 = Incoming mailbox 3 byte 1Bit 24 = Incoming mailbox 3 byte 0Bit 23 = Incoming mailbox 2 byte 3Bit 22 = Incoming mailbox 2 byte 2Bit 21 = Incoming mailbox 2 byte 1Bit 20 = Incoming mailbox 2 byte 0Bit 19 = Incoming mailbox 1 byte 3Bit 18 = Incoming mailbox 1 byte 2Bit 17 = Incoming mailbox 1 byte 1Bit 16 = Incoming mailbox 1 byte 0

15:00 Outgoing Mailbox Status. This field indicates which out going mail box registers have been writtenby the PCI bus interface but have not yet been read by the Add-On bus. Each bit location correspondsto a specific byte within one of the four outgoing mailboxes. A value of one for each bit signifies thatthe specified mailbox byte is full, and a value of zero signifies empty. The mapping of these statusbits to bytes within each mailbox is as follows:

Bit 15 = Outgoing mailbox 4 byte 3Bit 14 = Outgoing mailbox 4 byte 2Bit 13 = Outgoing mailbox 4 byte 1Bit 12 = Outgoing mailbox 4 byte 0Bit 11 = Outgoing mailbox 3 byte 3Bit 10 = Outgoing mailbox 3 byte 2Bit 09 = Outgoing mailbox 3 byte 1Bit 08 = Outgoing mailbox 3 byte 0Bit 07 = Outgoing mailbox 2 byte 3Bit 06 = Outgoing mailbox 2 byte 2Bit 05 = Outgoing mailbox 2 byte 1Bit 04 = Outgoing Mailbox 2 byte 0Bit 03 = Outgoing Mailbox 1 byte 3Bit 02 = Outgoing Mailbox 1 byte 2Bit 01 = Outgoing Mailbox 1 byte 1Bit 00 = Outgoing Mailbox 1 byte 0

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INTERRUPT CONTROL/STATUSREGISTER (INTCSR)

Register Name: Interrupt Control and StatusPCI Address Offset: 38hPower-up value: 00000000hAttribute: Read/Write (R/W),

Read/Write_One_Clear (R/WC)Size: 32 bits

This register provides the method for choosing whichconditions are to produce an interrupt on the PCI businterface, a method for viewing the cause of the inter-rupt, and a method for acknowledging (removing) theinterrupt’s assertion.

Interrupt sources:

• Write Transfer Terminal Count = zero

• Read Transfer Terminal Count = zero

• One of the Outgoing mailboxes (1,2,3 or 4)becomes empty

• One of the Incoming mailboxes (1,2,3 or 4)becomes full.

• Target Abort

• Master Abort

31 015 14 12 8 4 Bit

Value16212324

FIFO and Endian Control 0

Read TransferComplete (R/WC)

Write Transfer Complete (R/WC)

Incoming Mailbox Interrupt (R/WC)

Outgoing Mailbox Interrupt (R/WC)

Interrupt Asserted (RO)

Target Abort (R/WC)

Master Abort (R/WC)

0 0 0 0

D4-D0 Outgoing Mailbox (Goes empty)

D4=Enable Interrrupt

D3-D2=Mailbox #

0 0=Mailbox 10 1=Mailbox 21 0=Mailbox 31 1=Mailbox 4

D1-D0=Byte #

0 0=Byte 00 1=Byte 11 0=Byte 21 1=Byte 3

D12-D8 Incoming Mailbox (R/W)(Becomes full)

D12=Enable Interrupt

D11-D10=Mailbox

0 0=Mailbox 10 1=Mailbox 21 0=Mailbox 31 1=Mailbox 4

D9-D8=Byte #0 0=Byte 00 1=Byte 11 0=Byte 21 1=Byte 3

Interrupt on WriteTransfer Complete

Interrupt on ReadTransfer Complete

Interrupt Source (R/W)Enable & Selection

Actual Interrupt Interrupt Selection

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0011

0 NO CONVERSION (DEFAULT)1 16 BIT ENDIAN CONV.0 32 BIT ENDIAN CONV.1 64 BIT ENDIAN CONV

FIFO ADVANCE CONTROLPCI INTERFACE 0 0 BYTE 0 (DEFAULT)0 1 BYTE 11 0 BYTE 21 1 BYTE 3

FIFO ADVANCE CONTROLADD-ON INTERFACE 0 0 BYTE 0 (DEFAULT)0 1 BYTE 11 0 BYTE 21 1 BYTE 3

OUTBOUND FIFO PCI ADD-ON DWORD TOGGLE0 = BYTES 0-3 (DEFAULT)1 = BYTE 4-7 (NOTE1)

INBOUND FIFO ADD-ON PCI DWORD TOGGLE0 = BYTES 0-3 (DEFAULT)1 = BYTE 4-7

NOTE 1: D24 and D25 MUST BE ALSO "1"

31 30 29 28 27 26 25 24

1

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Bit Description

31:24 FIFO and Endian Control.

23 Interrupt asserted. This read only status bit indicates that one or more of the four possible interruptconditions is present. This bit is nothing more than the ORing of the interrupt conditions describedby bits 19 through 16 of this register.

22 Reserved. Always zero.

21 Target Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa target abort during a PCI bus cycle while the S5933 was the current bus master. This bit operatesas read or write one clear. A write to this bit with the data of “one” will cause this bit to be reset, a writeto this bit with the data of “zero” will not change the state of this bit.

20 Master Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa Master Abort on the PCI bus. A master abort occurs when there is no target response to a PCI buscycle. This bit operates as read or write one clear. A write to this bit with the data of “one” will causethis bit be reset, a write to this bit with the data of “zero” will not change the state of this bit.

19 Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data from the PCI bus to the Add-On. Thisinterrupt will occur when the Master Read Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.

18 Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. Thisinterrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.

17 Incoming Mailbox Interrupt. This bit is set when the mailbox selected by bits 12 through 8 of thisregister are written by the Add-On interface. This bit operates as read or write one clear. A write tothis bit with the data of “one” will cause this bit to be reset; a write to this bit with the data as “zero”will not change the state of this bit.

16 Outgoing Mailbox Interrupt. This bit is set when the mailbox selected by bits 4 through 0 of this registeris read by the Add-On interface. This bit operates as read or write one clear. A write to this bit withthe data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not changethe state of this bit.

15 Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the readtransfer count reaches zero. This bit is read/write.

14 Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the writetransfer count reaches zero. This bit is read/write.


12 Enable incoming mailbox interrupt. This bit allows a write from the incoming mailbox register identifiedby bits 11 through 8 to produce a PCI interface interrupt. This bit is read/write.

11:10 Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to bethe source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.

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9:8 Incoming Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits10 and 11 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]bselects byte 2, and [11]b selects byte 3. This field is read/write.

7:5 Reserved, Always zero.

4 Enable outgoing mailbox interrupt. This bit allows a read by the Add-On of the outgoing mailboxregister identified by bits 3 through 0 to produce a PCI interface interrupt. This bit is read/write.

3:2 Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be thesource for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2,[10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.

1:0 Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selectsbyte 2, and [11]b selects byte 3. This field is read/write.

Bit Description

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MASTER CONTROL/STATUSREGISTER (MCSR)

Register Name: Master Control/StatusPCI Address Offset: 3ChPower-up value: 000000E6hAttribute: Read/Write, Read Only,

Write OnlySize: 32 bits

This register provides for overall control of this de-vice. It is used to enable bus mastering for both datadirections as well as providing a method to performsoftware resets.

The following PCI bus controls are available:

• Write Priority over Read

• Read Priority over Write

• Write Transfer Enable

• Write master requests on 4 or more FIFO wordsavailable (full)

• Read transfer enable

• Read master requests on 4 or more FIFOavailable (empty)

• Assert reset to Add-On

• Reset Add-On to PCI FIFO flags

• Reset PCI to Add-On FIFO flags

• Reset mailbox empty full status flags

• Write external non-volatile memory

The following PCI interface status flags are provided:

• PCI to Add-On FIFO FULL

• PCI to Add-On FIFO has four or more emptylocations

• PCI to Add-On FIFO EMPTY

• Add-On to PCI FIFO FULL

• Add-On to PCI FIFO has four or more wordsloaded

• Add-On to PCI FIFO EMPTY

• PCI to Add-On Transfer Count = Zero

• Add-On to PCI Transfer Count = Zero

31 29 27 24 23 014 12 10 8 7 6 515 Bit

Value

FIFO STATUS (RO)D5=Add-on to PCI FIFO EmptyD4=Add-on to PCI FIFO 4+ WordsD3=Add-on to PCI FIFO FullD2=PCI to Add-on FIFO EmptyD1=PCI to Add-on FIFO 4+SpacesD0=PCI to Add-on FIFO Full

D7=Add-on to PCI Transfer Countequals zero (R0)

D6=PCI to Add-on Transfer Countequals zero (R0)

160

Write Transfer Control (R/W)(PCI memory writes)

D10=Write Transfer EnableD9=FIFO Management SchemeD8=Write vs Read Priority

Reset Controls (R/WC)D27=Mailbox Flags ResetD26=Add-on to PCI FIFO Status Flags ResetD25=PCI to Add-on FIFO Status Flags ResetD24=Add-On Reset nv operation address/data

Memory Read MultipleEnable = 1Disable = 0

Read Transfer Control (R/W) (PCI memory reads)

D14=Read Transfer EnableD13=FIFO Management SchemeD12=Read vs. Write Priority

nvRAM Access Ctrl

0 0

Control Status

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Bit Description

31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatilememory. Write operations are achieved by a sequence of byte operations involving these bits and the8-bit field of bits 23 through 16. The sequence requires that the low-order address, high order address,and then a data byte are loaded in order. Bit 31 of this field acts as a combined enable and ready forthe access to the external memory. D31 must be written to a 1 before an access can begin, andsubsequent accesses must wait for bit D31 to become zero (ready).

D31 D30 D29 W/R

0 X X W Inactive

1 0 0 W Load low address byte

1 0 1 W Load high address byte

1 1 0 W Begin write

1 1 1 W Begin read

0 X X R Ready

1 X X R Busy

Cautionary note: The nonvolatile memory interface is also available for access by the Add-Oninterface. Accesses by both the Add-On and PCI bus to the nv memory are not directly supportedby the S5933 device. Software must be designed to prevent the simultaneous access of nvmemory to prevent data corruption within the memory and provide for accurate data retrieval.

28 FIFO loop back mode.

27 Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY).It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Sincereading of this bit will always produce zeros, this bit is write only.

26 Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Add-On to PCI (Bus mastermemory writes) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFOFour Plus word flag to reset. It is not necessary to write this bit as zero because it is used internallyto produce a reset pulse. Since reading of this bit will always produce zeros, this bit is write only.

25 PCI to Add-On FIFO Status Reset. Writing a one to this bit causes the PCI to Add-On (Busmaster memory reads) FIFO empty flag to set indicating empty and the FIFO FULL flag to resetand the FIFO Four Plus words available flag to set. It is not necessary to write this bit as zerobecause it is used internally to produce a reset pulse. Since reading of this bit will always producezeros, this bit is write only.

24 Add-On pin reset. Writing a one to this bit causes the reset output pin to become active. Writing azero to this pin is necessary to remove the assertion of reset. This register bit is read/write.

23:16 Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and29 of this register to access the external non-volatile memory. The contents written are either lowaddress, high address, or data as defined by bits 30 and 29. This register will contain the externalnon-volatile memory data when the proper read sequence for bits 31 through 29 is performed.

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Bit Description

15 Enable memory read multiple during S5933 bus mastering mode.

14 Read Transfer Enable. This bit must be set to a one for S5933 PCI bus master read transfers totake place. Writing a zero to this location will suspend an active transfer. An active transfer is onein which the transfer count is not zero.

13 Read FIFO management scheme. When set to a 1, this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more vacant FIFO locations to fill. Once the controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevacant FIFO word.

12 Read versus Write priority. This bit controls the priority of read transfers over write transfers.When set to a 1 with bit D8 as zero this indicates that read transfers always have priority overwrite transfers; when set to a one with D8 as one, this indicates that transfer priorities willalternate equally between read and writes.


10 Write Transfer Enable. This bit must be set to a one for PCI bus master write transfers to takeplace. Writing a zero to this location will suspend an active transfer. An active transfer is one inwhich the transfer count is not zero.

9 Write FIFO management scheme. When set to a one this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more FIFO locations filled. Once the S5933 controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevalid FIFO word.

8 Write versus Read priority. This bit controls the priority of write transfers over read transfers.When set to a one with bit D12 as zero this indicates that write transfers always have priority overread transfers; when set to a one with D12 as one, this indicates that transfer priorities willalternate equally between writes and reads.

7 Add-On to PCI Transfer Count Equal Zero (RO). This bit is a one to signify that the write transfercount is all zeros.

6 PCI to Add-On Transfer Count Equals Zero (RO). This bit is a one to signify that the read transfercount is all zeros.

5 Add-On to PCI FIFO Empty. This bit is a one when the Add-On to PCI bus FIFO is completelyempty.

4 Add-On to PCI 4+ words. This bit is a one when there are four or more FIFO words valid withinthe Add-On to PCI bus FIFO.

3 Add-On to PCI FIFO Full. This bit is a one when the Add-On to PCI bus FIFO is completely full.

2 PCI to Add-On FIFO Empty. This bit is a one when the PCI bus to Add-On FIFO is completelyempty.

1 PCI to Add-On FIFO 4+ spaces. This bit signifies that there are at least four empty words withinthe PCI to Add-On FIFO.

0 PCI to Add-On FIFO Full. This bit is a one when the PCI bus to Add-On FIFO is completely full.

256 ENTREES / SORTIES DIGITALES PCI 104-DIO · 2018. 10. 12. · +54 Readload STB 624 Groupe 5 RO...

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Transcript of 256 ENTREES / SORTIES DIGITALES PCI 104-DIO · 2018. 10. 12. · +54 Readload STB 624 Groupe 5 RO...