253508

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Hindawi Publishing CorporationAdvances in Power ElectronicsVolume 2010, Article ID 253508, 9 pagesdoi:10.1155/2010/253508

Research ArticleOne Clock-Cycle Response 0.5 μmCMOSDual-Mode ΣΔDC-DCBypass Boost Converter Stable overWide RESR LCVariations

NeerajA. Keskar1 and Gabriel A. Rincon-Mora 2

1 DC-DC Controllers, Texas Instruments, Manchester, NH 03054, USA 2 Georgia Tech Analog, Power, and Energy IC Research Laboratory, School of ECE, Georgia Institute of Technology,

Atlanta, GA 30332, USA

Correspondence should be addressed to Neeraj A. Keskar, [email protected] 29 April 2009; Accepted 21 January 2010

Academic Editor: Vassilios G. Agelidis

Copyright © 2010 N. A. Keskar and G. A. Rinc on-Mora. This is an open access article distributed under the Creative CommonsAttribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work isproperly cited.

Power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-packageenvironments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. Thefrequency-compensation network, however, limits speed and regulation performance because it must cater to all combinationsof filter capacitor C O , inductor L, and C O’s equivalent series resistance RESR resulting from tolerance and modal design targets. Assuch, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios, even if the likelihood of occurrence of the latter is considerably high and the former substantially low. Sigma-delta (ΣΔ) control, whichaddresses this issue in buck converters by easing its compensation requirements and off ering one-cycle transient response, has notbeen able to simultaneously achieve high bandwidth, high accuracy, and wide RESR LC compliance in boost converters. This paperpresents a dual-mode ΣΔ boost bypass converter, which by using a high-bandwidth bypass path only during transient load-dumpevents was experimentally 1.41 to 6 times faster than the state of the art in current-mode ΣΔ boost supplies, and this without any compromise in RESR LC compliance range (0–50 mΩ, 1–30 μH, and 1–350 μF).

1. Introduction

In portable applications like cellular phones, PDAs, andthe like, integrated BiCMOS and CMOS switching dc-dcsupply circuits reduce cost, size, component count, and

design complexity (from a user’s perspective). One of thecritical bottlenecks in obtaining a fully integrated solution,however, is the frequency-compensation circuit, which isdesigned around off -chip power LC filter devices to obtainoptimal performance [1]. The fact is mode-rich state-of-the-art applications, manufacturing tolerances, and parameterdrifts expose dc-dc converter integrated circuits (ICs) towide variations in output capacitance C O, power inductanceL, and C O’s equivalent series resistance RESR , inducingconsiderable changes in loop-gain and transient response,compromising feedback stability or transient response. Asa result, to guarantee stability and high bandwidth with afixed on-chip frequency-compensation circuit, the design

necessarily constrains RESR LC values within a narrow targetrange [1]. This is especially detrimental in compact high-performance multiple input-output converters [2, 3], wherethe on-chip or in-package LC filter is variable by design todynamically accommodate the diverse loading conditions of

the system.Unclocked or asynchronous sigma-delta (ΣΔ) buck con-

verters [4–8] are self-compensating and free of the speed-stability tradeoff s of most dc-dc converters because thecontrol loop in these converters resembles current-modecontrol by indirectly sensing the inductor current ripple viathe ripple voltage it drops across C O’s RESR . In other words,the ESR voltage mostly sets the terminal ripple voltage of C O,impressing the inductor ripple current information on theoutput voltage and achieving current-mode-like control. Theresulting single-pole-like response yields higher bandwidthand more explicit control over the output ripple voltage[7].

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2 Advances in Power Electronics

Extending this technique and its benefits to boostconverters, which are popular in portable electronics forboosting battery voltages to 3.3–5 V, is not straightforwardbecause the inductor current does not fully flow to C O.Consequently, in realizing ΣΔ control in boost converters,the feedback circuit must explicitly sense and mix inductor

current with the sensed output voltage [9]. Such techniques,however, resurrect the limiting speed-stability tradeoff s ΣΔcontrol averted in buck converters in the first place, forcingthe designer to adjust current and voltage gains thereby reducing the loop bandwidth in order to accommodatelarge RESR LC filter values.

This paper presents a dual-mode boost ΣΔ bypasscontroller IC that overcomes the aforementioned speed-stability compromise by introducing a high-speed bypassmode (and circuit) that engages only during transient load-dump events, achieving both high bandwidth and wideRESR LC compliance. To this end, Section 2 first reviewsand discusses the stability requirements of ΣΔ convertersand their resulting transient response to fast load dumps.Section 3 then describes the proposed dual-mode techniqueand the design of its IC-prototype embodiment, followed by experimental results in Section 4; Section 5 draws relevantconclusions.

2. ΣΔConverters

2.1. ΣΔ Control in Buck Converters. A ΣΔ buck converter,as shown in Figure 1, controls the frequency and duty cycleof PMOS switch S M by comparing rippling output voltagev O via sensed voltage v S against dc reference V REF withcomparator CPV . Operationally, ac inductor ripple current

il flows into C O and its RERS (which is relatively largein these converters at 100–250 mΩ to ensure its voltage—v esr— overwhelms ac capacitor voltage v c) [7] as capacitordisplacement current ic, forcing ac output ripple voltage v o tomimic il (v o≈ v esr =il RESR ). As a result, in regulating v o, theconverter also regulates il , which in the process simplifies thefrequency response of the converter to that of a single-polesystem, as in current-mode control, guaranteeing stability,irrespective of RESR LC values.

In a positive load-step transient event, when load currentiO suddenly rises, comparator CPV detects the voltage droopthe now larger iO induces on v O and consequently switchesS M on indefinitely (i.e., at 100% duty cycle) until v O returns

within CPV ’s predefined hysteretic window limits, that is,within an acceptably low margin of V REF. During S M ’s ontime, the inductor voltage being nearly constant at V IN −V O,inductor current iL slews in a single switching cycle untilit fully supplies iO and recharges C O back to V REF [8]. Inother words, only the inductor and capacitor slew-rate limitsand second-order delays across the comparator and switchset the response time (eff ective bandwidth) of the system.Note a negative load dump undergoes a similar but reversedresponse.

2.2. ΣΔ Control in Boost Converters. Unlike buck converters,ac inductor ripple current il in boost converters does not

flow completely to output capacitor C O because reverse-biased diode D (shown in Figure 2) temporarily disconnectsL from v O (and C O) when switch S M conducts all of iL toground. The resulting ac ripple voltage in v O does not fully reflect the behavior of il , as it does in buck converters withnonnegligible RESR values, which means that ΣΔ control in

boost converters cannot rely on v O alone [9]. The negativefeedback loop in a boosting supply must therefore sense,scale, and mix iL with v O explicitly (e.g., mix iLRI g mi andv O g mv into RS as scaled sum v SUM) to achieve current-mode-like control characteristics. A hysteretic comparator thenmodulates S M ’s frequency and duty cycle based on how thescaled sum (v SUM) of the ripples compares against a user-defined hysteresis window. Note the voltage feedback loopmodulates the eff ective inductor reference current v I.REF/RI ,which is also the average inductor current I L (or low-passfiltered —LPF— version of iL) to whatever is necessary tofully supply iO.

Within the context of averaged small-signal analysis, therelatively high-gain, low-bandwidth voltage control loop (V Loop) of the system eff ectively embeds a higher bandwidth,lower gain current loop (I Loop), as shown Figure 3 [10].At low frequencies, below low-pass filter pole pLPF, iLRI

nearly equals v I.REF and the gain of the current loop ispractically zero, but increasing with frequency until reachingits highest possible gain at frequencies past pLPF. The currentloop’s gain again drops at high frequencies, past the complex LC double poles, when the ac voltage across L decreases.Given that iL is, for all practical purposes, regulated tohigher frequencies and therefore is a current source to theouter voltage loop at moderate-to-high frequencies, C O andeff ective load resistance RO set the dominant low-frequency pole of the system while L and RO invoke right-half planezero z RHP [11].

For stable conditions to prevail, the unity-gain frequency of the voltage loop (i.e., the system — f V.0 dB—) must fallbelow z RHP and iL must remain a current source (i.e., currentloop must stay closed with considerable loop gain) for thefrequency range of interest to the voltage loop [10]. Assuch, f V.0 dB must stay below both z RHP and current-loopbandwidth f I.0 dB:

f 0dBV ≈g mv D

M

2πRI g miC O<< f 0dBI ≈

RI g miRS MV O2πL

, (1)

f 0dBV ≈

g mv D

M

2πRI g miC O < z RHP =

D M V O

2πLI L , (2)

or

LI LV OC O

=LI O

C OV OD M

<RI g mi

g mv , (3)

where D M is the duty-cycle of S M , D M is (1−D M ), and M is

the modulator gain. Note that z RHP and f I.0 dB shift to lowerfrequencies with increasing inductance values, which meansthat f V.0 dB must also decrease accordingly, in an ideal case.LPF pole pLPF, whose location indicates the lowest frequency at which the current loop is closed, must also be below

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Advances in Power Electronics 3

V IN S M

D

iL

L

RESR

C Ov c

ic

iO

L o a d

LC filter v GM

v O

R1

R2

CPv +

−

v S

V REF

Figure 1: Circuit schematic of a switching ΣΔ buck converter.

iLRI

RI

g mv

v I .REF

v SUM g mi

iL

++−

+−

−C O

K I = g miRSK V = g mv RS

iOiD L P F

RESR

L

o a d

I-Loop

V -Loop

V GM

v O

ic

RS

V IN

S M

D

L

iL

v PH

V REF

Figure 2: Circuit schematic of a switching ΣΔ boost converter.

the worst-case value of f V.0 dB to ensure there is enough gainfor iL to remain a current source:

pLPF

<f V.0 dB| min =

D M

2V O

2πLI L. (4)

Ultimately, the system responds to a load dump at the speedof the voltage loop, whose bandwidth is f V.0 dB, allowingswitch S M to cycle multiple times before restoring v O back to its target window. LPF pole pLPF limits the extent to whichiL naturally responds to a load dump by allowing moderate-to-high frequency ac error-correcting signals through thecurrent loop. In other words, the current loop limits (whileattempting to regulate) the rising and falling rates of averageiL below iL’s maximum possible slew-rates of V IN /L and(v O – V IN )/L. Because f V.0 dB and pLPF both decrease withincreasing L, with the former also decreasing with decreasingC O, the worst-case LC combination, from the perspective of stability, occurs at the highest L and lowest C O, the condition

for which gains RI g miRS and g mv RS and pole pLPF are adjustedand transient-response performance over the entire LC filterrange is sacrificed.

3. ProposedDual-ModeΣΔController IC

The proposed ΣΔ boost controller IC in Figure 4 overcomesthe transient-response degradation associated with theworst-case LC combination by bypassing the main voltageloop (and its f V.0 dB) with a fast (and lower low-frequency loop gain) feed-forward path only during transient events.The stability requirements of the main loop set the acceptableRESR LC range for the system while the high-bandwidth

g mv +−

V REF+−

v SUM M d m

RS

i1

RI

GI D M

−I L

Z Ov O

++

id

g mi

I Loop V Loop

Figure 3: Small-signal equivalent control diagram of switching ΣΔboost converter at moderate-to-high frequencies.

bypass path allows the system to respond in one cycle at themaximum possible inductor current slew rate, the responseof which is similar to ΣΔ buck converters. The transientimprovement is achieved on chip (i.e., without an off -chipfrequency compensation circuit) and without sacrificing LCcompliance.

3.1. Steady-State and Bypass Operation. The basic objectiveof the bypass mode is to override nominal equivalent averageinductor current reference I L(nom) (v I.REF/RI ) to a highervalue almost instantly only during load dumps and allow thebypass voltage loop to control and limit how much of theextra current in L flows to v O. Initially, during steady-stateconditions, the bypass circuit is inactive and load currentiO and S M ’s average off duty cycle D

M (i.e., one minus S M ’saverage on duty cycle D M ) set the nominal average inductorcurrent I L(nom) required to support a given iO, which ishigher than iO because S M steers a portion of iL away fromv O to ground according to D M :

I L(nom) = I OD M

= I O1 − D M

. (5)

In the bypass mode, however, independent loops regulate iL

to a value higher than I L(nom) and sensed output voltage v Sto V REF, as depicted in the equivalent circuit of Figure 5.

The current loop, which modulates switching frequency f SW and S M ’s duty cycle d M , has higher bandwidth andappears as a current source for frequencies of interest to thelower bandwidth bypass voltage loop controlling auxiliary switch S A. In the bypass mode, inductor current iL isregulated at a value I PK or V PK /RI that is greater thanI L(nom) (i.e., I L required to support I O). This means, unlessotherwise limited, average diode current I D is now higher

than I O, as a result of which C O recharges quickly. Oncev O is back within the hysteretic window limit of bypasscomparator CPB and about to surpass its upper boundary,CPB and S A divert excess current away from D through S A

until iO again discharges v O to CPB’s lower window limit.The switching cycle repeats as average inductor current IL

gradually drops back to I L(nom), at which point the bypassloop stops switching and S A remains open. Note as long asI L exceeds I L(nom), the bypass voltage loop, by independently regulating v O with higher loop gain than the current loop,ensures that the voltage inputs of summing comparator CPS

are virtually short-circuited (i.e., v S ≈ V REF), as shown inFigure 6, allowing CPS to regulate iL exclusively.

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+K I

K V

−

+−

V REF

V REF+

−

V REF−

+

CPs

CPT

CPB

Bypass voltage

loop

Bypass current loop

Mode transition

V I.REF

LPFRI

iL

V IN

LS A

v GA

v GM S M

C O

iD

RESR R1

R2

ic

iO

v O

L o a d

v S

Figure 4: Simplified schematic of the proposed dual-mode ΣΔ

boost converter.

−

R1

R2

CPB

Bypass voltage

loopBypasscurrent

loopV REF−

+

I REG = D M I L ≈ D M

v I.REF

RI

I D = I O = D M I L(nom)

V PK

RI ≈ I PK I L I L(nom)

RESR

C O

S A

ic

DiO v O

v S

iD

v GAiREG

V IN

L o a d

Figure 5: Equivalent circuit of the proposed ΣΔ converter in thebypass mode.

With respect to stability, as already mentioned, the unity-gain frequency of the current loop ( f I.0 dB) must exceed thatof the bypass voltage loop ( f B.0 dB) so the inductor appears

as a current source in the voltage loop, eliminating thecomplex conjugate pair associated with LC in the voltageloop [12]. Because the unity-gain bandwidth of a ΣΔ loopis its switching frequency, S M ’s switching frequency ( f I.0 dB)must exceed that of S A ( f B.0 dB). Therefore, since f I.0 dB

depends on the rising and falling rates of iLRI as it traversesCPS’s hysteretic current window H I ,

f I.0 dB =

H I

RI

−1 L

V IN +

L

V O − V IN

−1

=V IN (V O − V IN )RI

V OH I L

(6)

RI

iLRI

From CPT

V PK = I PK RI

RF C F

v I.REF

CPS

K I

K V

−+

−

+

iLΔ current loop

Powerstage

Virtual short due tobypass voltage loop

+−

Figure 6: Simplified conceptual circuit schematic of the dual-modeΣΔ converter in bypass mode, as the bypass loop virtually shorts v Sand V REF and the current loop regulates iL to v I.REF/RI .

and f B.0 dB on how fast excess iD (i.e., D M I L – I D) and I O

charge and discharge output capacitor C O between CPB’shysteretic voltage window H V ,

f B.0 dB =H V (R1 + R2)

R2

−1C OI O

+C O

D M I L − I O

−1

,

(7)

to force f I.0 dB to be greater than f B.0 dB, C O must exceed

C O ≥

H I

H V

I OL

V ORI D

M

R2

R1 + R2

≡ C O(min), (8)

where the R1-R2 divider represents the eff ect of the resistivefeedback factor on H V and C O(min) the minimum stable

output capacitance.

3.2. Transient Response and Mode Transition. During apositive load-dump event, when I O suddenly rises and v Odroops in response, as shown in Figure 7, the dual-modeconverter enters its bypass mode, raising iL to peak value I PK

(or V PK /RI ) in a single switching cycle of S M . Subsequently v O (or v S) is pulled back to V REF (R1+R2)/R2 (or V REF) ina single switching cycle of S A. Transient-detect comparatorCPT in Figure 4 perceives the load dump and engages thebypass mode by sensing when v S drops below V REF by apreset threshold value of ΔV BP (e.g., 2.5% of V REF) (afterthe delay the comparator requires to switch: t d ). Then,

CPT clamps v I.REF to peak voltage V PK , the value of whichsets the maximum current the circuit can drive. Switch S M

therefore remains closed (t t.M (on)) until iL reaches V PK /RI

(I PK ), the new value of v I.REF/RI . After S M resumes switchingand regulating iL about I PK , S A remains open and allowsall diode current iD to flow to v O until C O recharges to(V REF+H V /2)·(R1+R2)/R2. Beyond this point, CPB and S A

regulate v S about V REF by switching S A, in other words, by steering excess inductor current away from C O.

Ultimately, output voltage v O droops in response to loaddump ΔiO until iL reaches I PK . First, excess current ΔiO

discharges C O during delay t d while v S reaches V REF − ΔV BP .Then, while S M raises iL from iL(avg) (or V REF/RI or I L(nom)1) to

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v GA

iO

iL

v O ΔV BP

Δv O

v I.REF /RI

V IN /L I L(nom)1

I L(nom)2

ΔiO

I O2

I O1

I PK

H v R1 + R2

R2

t d

t t.M (on) Time

Figure 7: Transient-response performance when presented withfast load-steps (positive and negative).

V I.OS

RI.OS

I I.OS

RF v I.REF

C F

CPS

ΣΔ current loop

Powerstage

+ −iL

iLRI

RI

Virtual short due tobypass voltage loop

K I

K V

−+

−+

Figure 8: Equivalent converter circuit in bypass mode with addedoff set voltage V I.OS to ensure that v I.REF /RI is slightly below iL(avg) .

I PK (or V PK /RI ), iD is zero and full load current I O discharges

C O, yielding a total variation (Δv O) of

Δv O = ΔV BP +

I OC O

t t.M (on)

= ΔV BP +

I OC O

I PK − I L(nom)1

L

V IN

= ΔV BP +

I OC O

(V PK − v I.REF)L

RI V IN .

(9)

Note that the ratio of L and C O sets the dominant part of Δv O.

Once sensed output voltage v S is within the hysteretic

voltage window of CPB, to transition back to steady state,iL(avg) must somehow fall back to whatever value (I L(nom)) isnecessary to sustain I O , reducing to zero the amount of excesscurrent iL that bypass comparator CPB steers away fromv O through S A. To that end, introducing a series negativeoff set voltage V I.OS, as shown in Figure 8, ensures that iL isalways above its target (i.e., iL(avg) is greater than v I .REF/RI ),forcing the loop to gradually decrease both iL(avg) and theexcess current. Finally, when iL is low enough to be able tofully supply iO, and the excess current (D

M I L–I O) is zero, thebypass loop stops switching (i.e., disengages), which meansthat the main voltage loop now regulates v O via S M (Figure 4)to its target. In other words, henceforth, iL(avg) equals I L(nom).

v I.REF

+V I.OS / 2

−V I.OS / 2

Current-loop Voltage-loop

V R E F

(5V/V )

ADV

ADI

(8V/V )iL

L RS

S M

SD

iO v O

S A

RESR

C O

RI (50mΩ)

ADS CP M

CPT

CPB

(140mV)

(140mV)

V V.OS (50mV)

g miRS = 2.8V/V g mv RS = 5.3V/V

g mi

g mv L o a d

V IN

R1

(76K)

R2

(24K)

v S

+−

−+

+

+

−

−

+

−

+

−

+

−

+

−

+ −

+−

+− −

+

+−

+

−

+−

Figure 9: 0.5 μm CMOS circuit embodiment of the proposed dual-mode ΣΔ bypass boost converter.

Power switch (S A)Power switch (S A)

Drivers + deadtime

Comparators + digital

Bias

Decoupling caps

Amplifiers

V IN

V O

I O

RESR LC space

ηpeak

I Q

Δv O (5.6 μH,

53 μF, 0.1–1A)

Process

Die size

2.7–4.2 V

5 V ± 5%

0–1A

0–50mΩ1–30 μH

1–350 μF

93%

1.5 mA

0.23 V

0.5 μm

CMOS

(1.9 × 2.6)

mm2

Figure 10: Die photograph and performance summary.

Note that the transition is continuous, allowing S A to stopswitching without incurring irregularities in S M .

During a negative load dump, when iO suddenly drops, asalso shown in Figure 7, iL(avg) automatically exceeds its new steady-state target and v O rises above its target. As a result,

bypass comparator CPB engages and diverts current away from v O until v S again drops to V REF–H V /2 (in one cycle of S A). The circuit gradually transitions back to steady state inthe same manner as described earlier, through V I.OS.

4. Experimental Results andDiscussion

4.1. IC Design. The proposed dual-mode ΣΔ bypass con-verter was designed, fabricated, and evaluated using a 0.5μm,5 V CMOS process. The circuit embodiment of the converter,as shown in Figure 9, employs a diff erential-signal processingscheme to attenuate the eff ects of substrate noise on thehigh-bandwidth ΣΔ loops [10]. For simplicity, series resistor

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40

30

20

10100

101

102

C a p a c i t a

n c e( μ F )

C a p a c i t o r E S R ( m Ω )

10

5

10

15

20

25

30

I n d u c t

a n c e ( μ H )

iL (0.5A/div)

v O (20mV/div)

V IN = 2.7 V,

I O = 1 A

L = 5.6 μH,

C = 53 μF

Proposed ΣΔ

State-of-the-art ΣΔ

Figure 11: Nominal steady-state snapshot of inductor current iL

and output voltage v O ripples (inset) for the proposed solution andexperimental RESR LCstability space forboth the proposeddual-andstate-of-the-art single-mode boost ΣΔ converters.

RI senses iL with the understanding more power efficienttechniques are possible and recommended [13]. Current-sense amplifier ADI , which monitors the voltage across RI ,includes an internal RC filter that generates diff erentialcurrent reference v I.REF. Diff erential preamplifier ADV buff ersand amplifies sensed output voltage v S by 5V/V to decreasethe eff ects of off sets and hysteretic window limits in posterioramplifiers and comparators on v S and v O (i.e., improveaccuracy); ADV drives diff erential summing amplifier ADS,bypass hysteretic comparator CPB, and transient-detecthysteretic comparator CPB.

For ease of design and reliability, main, bypass, andtransient-detect comparators CP M , CPB, and CPT adoptthe same circuit architecture, which is designed to yield ahysteretic window of 140 mV. The bypass threshold voltage(ΔV BP ) is composed of half the comparator hystereticwindow plus an additional off set of 50mV (V V.OS) thatis added between CPB and CPT . Diff erential current-senseamplifier ADI includes a 40 mV off set voltage (V I.OS) at itsoutput to ensure iL is below its target by V I.OS/RI during thebypass mode, to gradually transition back to steady state aftera load dump. The designed off sets are sufficiently large to

dwarf the transistor mismatch-induced off sets in ADI , CPB,and CPT and ensure that the polarities of V V.OS and V I.OS

remain unchanged across process and temperature corners.In the absence of deep-N or buried layer isolation

structures, the bulk of a single PMOS transistor servingthe function of auxiliary switch S A could not be connectedto the highest potential (v O) because of latch-up concerns.Whenever the switching node flies above v O following theturn-off of S M , S A’s body diode can conduct engagingthe parasitic vertical PNP transistor present, channelingconsiderable current to the substrate. A second PMOS deviceis therefore added in series to use its reverse-biased body diode to block the foregoing current. And during normal

operating conditions, when v O is higher than V IN , as thebody diode of the first blocks the current of the second.

The proposed ΣΔ controller 0.5 μm IC was designed tosupply power from a 2.7–4.2 V Li-Ion battery and drive a 0-1Aloadat5V ± 5% with as widean RESR LC range as possible(0–50 mΩ, 1–30 μH, and 1–350 μL was achieved). The total

silicon surface area the IC occupied was 1.9 × 2.6 mm(Figure 10). The peak efficiency of the converter was 93% at0.4A with a biasing quiescent current of 1.5 mA. The totaloutput voltage variation of the converter in response to a0.1–1A load dump (ΔiO) with 5mΩ, 5.6 μH, and 53 μF of RESR LC was 200 mV, which constitutes a 4x improvementover its nonbypassed counterpart under similar conditions(800 mV).

4.2. LC Compliance. The measured RESR LC space for whichthe converter was stable is 0–50 mΩ, 1–30μH, and 1–350 μF, as illustrated in Figure 11. This range was determinedby subjecting the converter to 0.1–1A load dumps with

100 nanoseconds rise and fall times. The stability limitwas observed as a loss of regulation for the proposed ΣΔ

converter in the bypass mode, as the bypass loop was nolonger able to control the loop, and subharmonic oscillationsfor the nonbypassed (state-of-the-art) ΣΔ boost converter[14].

The stability limits for both converters, with and withoutthe bypass path, are reached when their respective current-loop bandwidths ( f I.0 dB) approach their voltage-loop coun-terparts ( f B.0 dB and f V.0 dB), as that is when L ceases to bea current source for the voltage loop, be the main loop,or the bypass loop. As a result, because f V.0 dB and f B.0 dB

increase with decreasing C O and increasing I O and f I.0 dB and

RHP zero z RHP decrease with increasing L and decreasingV IN , the highest L-I O(30 μH–1A) and lowest C O-V IN (12 μF-2.7 V) combination constitutes worst-case conditions. SinceRESR essentially introduces a left-half plane zero in thevoltage loop, increasing RESR also increases f V.0 dB and f B.0 dB,which means that the above-mentioned limits along with thehighest RESR value (50 mΩ) describe the worst-case stability point of the converter. In other words, C O(min) increases withincreasing L, I O, and RESR and decreasing V IN .

The maximum capacitance was limited to 350 μF as apractical limit for the intended portable application space(the circuit is stable at higher C O values). Similarly, themaximum RESR value was limited to 50 mΩ to keep the

output voltage ripple acceptably low under a 1 A load.Under these conditions and constraints, the stability spacesfor the proposed and the state-of-the-art converters areapproximately equal in “volume.”

4.3. Transient Load-Dump Performance. As shown inFigure 12(a), the transient-response variation of v O (Δv O) inresponse to 0.1–1A load dumps (ΔiO) with 100 nanosecondsrise and fall times under 2.7 V, 5.6μH, 53 μF, and 5mΩof V IN , L, C O, and RESR was 200 mV for the proposeddual-mode scheme and 800 mV for its single-mode state-of-the-art counterpart. While the proposed converterresponds by increasing iL above its target (to I PK or V PK /RI )

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0

1

2

3

4−1

−0.8

−0.6

−0.4

−0.2

0

0.20.4

V o l t a g e ( V )

C u r r e n t ( A )

0 0.2 0.4 0.6 0.8 1

Time (ms)

Proposed

State-of-the-art

Proposed

State-of-the-art v O

iL

V IN = 2.7 , L = 5.6 μH, C = 53 μF

(a)

−1

−0.5

0

0.5

1

1.5

2

2.5−0.2

0

0.2

0.4

0.6

V o l t a g e ( V )

C u r r e n t ( A )

0 0.5 1 1.5 2

Time (ms)

Proposed

State-of-the-art

Proposed

State-of-the-artv O

iL

V IN = 2.7 , L = 5.6 μH, C = 53 μF

(b)

Figure 12: Measured transient performance of the proposed dual-mode and state-of-the-art single-mode ΣΔ boost converters in response

to (a) 0.1–1A and (b) 1–0.1 A load steps.

0

0.5

1

1.5

2

2.5

3

3.5

−0.8

−0.6

−0.4

−0.2

0

0.2

V o l t a g e Δ v O

( V )

C u r r e n t i L

( A )

0 0.05 0.1 0.15

Time (ms)

Increasing L

Increasing L

v O

iL

30 μH15 μH

5.6 μH

30 μH

15 μH

5.6 μH

Figure 13: Measured eff ects of L on the transient performance of the proposed dual-mode ΣΔ bypass boost in response to 0.1–1 Aload dumps, C O = 53 μF.

in one switching cycle of S M , the state-of-the-art circuit

increases iL gradually, pulling v O back to regulation inseveral cycles of S M , which is why the proposed solutionexhibits a fourfold improvement over its predecessor.In a negative load-step (Figure 12(b)), while the excessinductor current is immediately bypassed by switch S A in theproposed converter keeping the output voltage overshootlow (<75 mV), the excess inductor energy causes a largevoltage overshoot (600 mV) in the state-of-the-art converter.

Decreasing (increasing) L increases (decreases) the rateat which iL responds to a load dump, as shown inFigure 13, thereby decreasing (increasing) the time v Oslews (reducing Δv O). Similarly, increasing (decreasing)C O decreases (increases) v O’s droop rate in response to

0

0.5

1

1.5

2

2.5

3

3.5

−1

−0.8

−0.6

−0.4

−0.2

0

0.2

V o l t a g e Δ v O

( V )

C u r r e n t i L ( A )

0 0.05 0.1 0.15

Time (ms)

Increasing C O

Increasing C O

v O

iL

26 μF

11 μF

53 μF

26 μF

11 μF

53 μF

Figure 14: Measured eff ects of C O on the transient performance of the proposed dual-mode ΣΔ bypass boost converter in response to0.1–1A load dumps.

a load dump (Figure 14). Note that increasing (decreas-

ing) C O also increases (decreases) the delay time betweenthe load step and the onset of bypass threshold voltageΔV BP (t d ) (Figure 7),whichis why the onset of iL rising shiftswith C O.

Although transient-response performance for the pro-posed dual-mode scheme improves with decreasing L, thesame is not true for the single-mode converter whose iL

response time is limited by the bandwidth of the loop,not L’s slew rate. As a result, as illustrated in Figure 15,the percentage improvement that the dual-mode enjoysover its single-mode counterpart increases with decreasingL: 6- and 1.43-fold improvement at 1 μH–36 μF and 30 μH–36 μF, respectively.

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0

0.2

0.4

0.60.8

1

1.2

1.4

1.6

1.8

T r a n s i e n t v o l t a g e Δ v O

( V )

1 10 100

Capacitance C O (μF)

V IN = 2.7 V, V O = 5 V

1 μH, state-of-the-art

1 μH, proposed


10 μH, proposed


15 μH, proposed

Δv O = 5%

ΔV BP = 120mV

Figure 15: Measured transient output voltage variation Δv O undervarious LC combinations in response to 0.1–1 A load dumps (ΔiO)

for the proposed dual-mode and state-of-the-art single-mode ΣΔconverters.

0

1

2

3

4

5

60

1

2

3

−0.4

−0.3

−0.2

−0.1

0

0.1

0.2

C u r r e n t ( A )

V o l t a g e ( V )

V o l t a g e ( V )

0 1 32 4

Time (ms)

Load current iO

Δv O (300mV)

Switch S A’sgate voltage v GA

Bypass

mode

Output

voltage v O140mV Main

mode

Inductor current iLI PK

1.1 A

V IN = 2.7 , L = 15 μH, C O = 53 μF

Figure 16: Measured steady state to bypass and back transitions inresponse to positive 0.1–0.6 A load dumps (positiveΔiO).

Increasing C O decreases v O’s transient droop in bothconverter cases, except that bypass threshold voltage ΔV BP

eff ectively limits the extent to which a larger C O decreasesΔv O in the proposed scheme. In the limit, increasing C O tosuch an extent that Δv O is less than ΔV BP would preventthe bypass mode from ever engaging. As a result, theperformance improvement in Δv O is lower between the

0

1

2

3

4

5

60

0.5

1

1.5

2−0.4

−0.2

0

0.2

0.4

C u r r e n t ( A )

V o l t a g e ( V )

V o l t a g e ( V )

0 1 32 4

Time (ms)

Load current iO

Switch S A’sgate

voltage v GA

Bypass

mode

Output voltage v O

140mVMainmode

Inductor current iL

I L(nom)1.3 A

V IN = 2.7 , L = 15 μH, C O = 53 μF

Figure 17: Measured steady state to bypass and back transitions inresponse to negative 0.6–0.1 A load dumps (negativeΔiO).

75

77

79

81

83

87

85

89

91

93

95

E ffi c i e n c y

( % )

0 0.2 0.4 0.6 0.8 1

Load current (A)

L = 15 μH

V IN = 2.7 V

V IN = 3.3 V

V IN = 4.2 V

Figure 18: Measured steady-state efficiency Vs. Load current I O forthe proposed converter.

proposed and state-of-the-art solutions at higher C O values:Δv O for the proposed and state of the art asymptotically converge as C O increases.

4.4. Mode Transition. Figures 16 and 17 illustrate how theproposed dual-mode ΣΔ bypass boost converter transitionsfrom steady state to bypass mode and back in response topositive and negative 0.1–0.6A load dumps with an LC com-bination of 15 μH and 53 μF. As designed, the bypass mode

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ripple is larger at ±70mV (±(H V /2)·(R1 + R2)/(R2 ADV ) ≈

±140 mV/2) or ±1.4% than the steady-state counterpart,which is at ±15 mV or ±0.3%. During a positive load dump(Figure 16), when iO suddenly rises, a load-induced dropin v O exceeding the ΔV BP limit engages the bypass modeand increases iL to 2.5A (I PK ) in one switching cycle of

S M . As determined by off

set VI.OS , the circuit then takesapproximately 2.5 ms to gradually decrease iL back to its new target of roughly 1.3A, at which point S A stops switchingand the converter is back in steady state. During a negativeload dump (Figure 17), iL is automatically above its targetand S A consequently starts diverting some of iL back to V IN

almost immediately, until 2.5 ms later, when iL drops to itsnew target.

The main drawbacks of the auxiliary bypass path arethe silicon real estate, power, and switching noise associatedwith power switch S A. The latter two shortcomings, however,are more often than not inconsequential because they only occur during transient events, which are typically sporadic,short, and seldom occur without significantly aff ecting thesteady-state power efficiency (Figure 18). The prominentdisadvantage of the proposed solution is therefore additionalsilicon real estate for S A because it carries substantial current.The transient-performance benefits of S A and the bypasspath that drives it, however, off set this cost.

5. Conclusion

A dual-mode ΣΔ bypass boost dc-dc controller 0.5μmCMOS IC that is stable for an RESR LC filter range of 0–50 mΩ, 1–30 μH, and 1–350 μF and responds to positiveand negative load dumps in one switching cycle has beenproposed, designed, fabricated, and evaluated. The drivingfeature of the foregoing solution is a robust on-chip (i.e.,smooth transitioning) ΣΔ bypass path that responds only during transient load dumps. While the converter increasesinductor current iL in one switching cycle in response to asudden rise in load current iO and uses it to quickly slew output capacitor C O back to its target, it also limits how much of iL flows to C O in the case of a negative load dump,when iO drops, limiting the total transient variation of outputvoltage v O and therefore improving accuracy performance.The transient-response benefits of the proposed scheme, ascompared to state-of-the-art single-mode ΣΔ converters, arethe highest at low values of L (e.g., 6x at 1 μH and 1.41x or

40% improvement at 30 μH) because L limits how fast iL risesand falls to its targets. The main drawback of the proposedtechnique is the additional silicon real estate required forauxiliary power switch S A, which is partially (and oftencompletely) off set by its improved accuracy performance.In summary, the proposed dual-mode ΣΔ bypass boostconverter is fast, widely LC compliant (robust), and easily implementable.

Acknowledgment

This work was supported by Texas Instruments.

References

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