2017/4/27 电源管理.
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2017/4/27 2017/4/27 2 PCB Lyaout LDO 20s /
2017/4/27 LDO 20s / Vout+10V current will flow to the output
Minimum load requirement is 1.5mA. Although it isnt mentioned in
the data sheets, the 267x requires a minimum load current.This part
has a boot-strapped output stage. The lower supply rail of the FET
driver and its bias network are connected to the switch pin.A
maximum boost voltage of approximately 9.4V is set by two 5V zeners
that are connected to the base of the NPN follower. A similar clamp
is connected directly across the FET driver to further add
protection. When Vin>10V+Vsw, current will flow from the PNP
through the zeners and out the switch pin. During normal operation,
this current is absorbed by the output load. During very light load
conditions, the regulator will skip several cycles, and for most of
the time, the inductor is discharged.As a result, the switch pin
voltage remains at Vout most of the time.Under this condition,
current from the PNP flows through the zeners and out the switch
pin when Vin>10V+Vout.If the output load current is less than
1mA, current from the zeners will pull Vout above its regulated
value.To ensure this doesnt happen, keep a minimum load of 1.5mA on
the output 2017/4/27 LM267X EMI Reduction The LM267X regulators
tend to have very fast rising and falling switching waveforms Good
for efficiency High frequencies can cause EMI problems Slowing down
the gate drive reduces EMI. Adding a snubber on the schottky
reduces EMI The LM267X can also be effected by EMI so good
bypassing is required Slowing down Switch turn on
2017/4/27 Slowing down Switch turn on Add 10ohm resistor Add 10ohms
in series with Cboost capacitor Reduces peak gate current through
driver Slows gate turn on Reduces high frequency EMI This method
slows down the turn-on of the output NFET. Adding 10ohms in series
with Cboost reduces the peak current that charges the gate.It
doesnt reduce the final value of the gate voltage, so I2R losses of
the switch dont increase. By reducing the gate drive, the output
switch rise time increases, and this reduces high frequency
components in the switch waveform. Schottky Snubber Reduces EMI
cause by reverse recovery currents
2017/4/27 Schottky Snubber Reduces EMI cause by reverse recovery
currents Series 47ohm resistor and 1nF cap in parallel with
schottky good values to start. 10-100ohms nF Another source of EMI
is large, narrow current spikes that flow through the output switch
when the the switch first turns on.This spikes are due to reverse
recovery current in the output diode.When the switch turns on, the
diode is reverse-biased by several volts in less than
20ns.Depending on the diode, this can produce a current spike of
several hundred milliamps with a pulse width of about 20-30ns.To
reduce this current spike, slow down the rate that the diode is
reverse biased by placing an RC snubber across it.In this example a
1nF and 47W are used to de-Q the switch node. 2017/4/27 Bypassing
LM267X A single pin supplies Vin to the ICs control circuitry and
output stage - output stage creates large current pulses As noise
increases at this pin, erroneous operation can result Higher
currents become more of a problem LM2671/2/4/5 require no special
bypassing LM2670/3/6/7/8/9 may require high frequency bypassing
Place uF ceramic bypass cap across Vin and GND pins EMI is also a
concern for input supply bypassing.The 276x uses a single pin to
supply input voltage to the control section and the output stage.As
a result, very large current pulses can appear at the VIN pin,
especially in the 3 and 5A parts. Without proper bypassing, this
will generate large, high frequency voltage transients that will
disrupt the 279x control circuits.Therefore, for the 3 and 5A
parts, we recommend placing a 0.47 to 2.2uF cap directly across the
VIN and GND pins. Board Layout Guidelines
2017/4/27 Board Layout Guidelines Web Resources on board layout.
Buck Regulator Schematic
2017/4/27 Buck Regulator Schematic SIMPLIFIED SCHEMATIC TRUE
SCHEMATIC The two schematic above illustrate the differences in the
considerations between component selection and board layout.Board
layout requires a clear understanding of electromagnetics.The
parasitics may not be a concern at all frequencies.At DC, only
resistance is a concern.At the switching frequency, the parasitics
at the switch node and high AC current paths are a concern.And for
frequencies associated with the switching edges, ALL the parasitics
are a concern. As current levels increase, the effect of the
parasitics will also increase. In this section we will establish
certain rules to help you successfully design a working power
supply.The example will be a boost regulator, but the rules will
extend to any topology. Trace inductance is x nH/cm has no meaning
in a board layout
Inductance is always defined in a closed path PARALLEL RETURN LOOP
TWISTED PAIR INDUCTANCE REDUCES The AC Current Traces Buck
Regulator Current flow
2017/4/27 The AC Current Traces Buck Regulator Current flow Figure
a: switch closed Figure b: switch open Figure c: Large AC current
path The first step is to understand where the high current AC
traces will be.The schematics above illustrate the current flow in
a buck regulator when the control switch is open and closed.It
illustrates where the AC current flows in the circuit.These traces
require special attention when laying out the board.If the
parasitic inductances and resistances get too large relative to the
current level, the noise generated in the system will cause
problems in the operation of the control circuitry and generate
significant EMI. The same process can be used for other
topologies.For a boost, the high AC currents are through the
switch, diode, and output capacitor.For a flyback, both primary and
secondary current paths have high AC currents. Grounding First Rule
Board Layout - Ground Isnt
2017/4/27 Grounding First Rule Board Layout - Ground Isnt Avoid
letting AC currents flow in the main ground plane. Run separate
traces Use single point ground for all sensitive circuitry Seperate
analog and power grounds A ground plane can only be a true
reference if no current is allowed to flow.And keeping a clean
ground is one of the keys to a good board.The following slides will
illustrate how to design to minimize the effects of board
parasitics. Ground Vin Ground ? Ground Vout Bypassing Monlithic
Switchers
2017/4/27 Bypassing Monlithic Switchers A single pin supplies Vin
to the ICs control circuitry and output stage - output stage
creates large current pulses As noise increases at this pin,
erroneous operation can result Higher currents become more of a
problem LM2671/2/4/5 require no special bypassing LM2670/3/6/7/8/9
may require high frequency bypassing Place uF ceramic bypass cap
across Vin and GND pins If the impedance from the bulk capacitor to
the switch is high, a local cermaic bypass capacitor, Cinx, can be
used to reduce switching edge noise.This capacitor recommended on
high current monolithic switchers. The 276xSIMPLE SWITCHER uses a
single pin to supply input voltage to the control section and the
power stage. Without proper bypassing, there will be large, high
frequency voltage transients that will disrupt the LM267x control
circuits.Therefore, for the 3 and 5A parts, we recommend placing a
0.47 to 2.2uF cap directly across the VIN and GND pins. For
aswitching controller with an external FET, the supply voltage can
be kelvin connected to the input capacitor or bypassed by a RC
circuit. Switch Node Voltage swings from Vin to Ground at fsw.
Solutions:
2017/4/27 Switch Node Voltage swings from Vin to Ground at fsw.
Very high dV/dt node! Electrostatic radiator Solutions: Avoid
creating an antenna Keep inductor very close to FETs Make switch
node short Put on multiple layers Avoid capacitive coupling to
ground Avoid coupling to signal paths B A The switch node is one of
the greatest noise sources in any switching power supply.The size
of the switch node should be minimized within the limitations of
the current rating and number of components connected to it.If
making a trade-off between getting the rectifier closer to the
control switch or the inductor closer, make the rectifier closer.At
least in this way the trace going to the inductor is carrying DC
current. This is one trace which should not have a ground plane
underneath it.Eliminating the ground plane eliminates capacitive
(capacitance A) coupling and very high frequency current spikes.
The faster the rise time of the switcher, the more critical this
design becomes.Faster rise times mean more current through the
capacitance and more EMI. Bottom View External capacitor from gate
to source reduces gate glitch
2017/4/27 FET Drivers High side gate Place drivers close to power
FETs Minimize loop area of gate drives Low side gate External
capacitor from gate to source reduces gate glitch All MOSFETs have
large capacitances between gate, source, and drain.The purpose of
the driver is to maintain the correct voltage on the gate of the
FET.In the diagram above, the parasitics shown are inductance and
resistance.However, resistance in the traces is not nearly as
important as the inductance of the traces.The inductances result in
a large impedance when trying to drive the FET on in 10ns.In
general, keep the drivers close to the FETs.However, first priority
is on good layout for the power train components and good grounding
technique. The scope photo above shows a phenomenon known as gate
glitch.When the high side FET turns on, it creates a very fast
dV/dt across the low side FET.The capacitances between drain to
gate and gate to source create a voltage divider and result in a
transient voltage on the gate of the low side FET.At this point,
the low side FET tries to turn on.The driver is responsible for
keeping the gate off, but can not do it.In mild cases, efficiency
is reduced.In severe cases, the FETs short the input to ground and
blow up.In certain cases, even shorting the gate to the source
still results in a glitch because of the impedances of the bond
wires inside the FET.In many cases, this problem can be eliminated
by adding some capacitance from gate to source in order to ensure
that the capacitive voltage divider has a low voltage from gate to
source.We recommend this design method with our LM2722 and LM2724
FET drivers.Another solution is to drive the gate below ground as
can be done with the LM5110 drivers. - FB FB/COMP network not close
to device
Close to noise sources UNSTABLE! - Isense Isense traces not
parallel Poor current sensing
= wrong D.C. Layout Gate drive trace too long Not parallel to SW
trace SW node
Top FET gate drives Examples are for approximately 10oC temp Rise.
Wider is Better!
Some examples: 1A, 1 Oz Cu, Trace Width = 12 mils Min. 5A, Oz Cu,
Trace Width = 240 mils Min. 20A, Oz Cu, Trace width = 1275 mils
Min. Lots of width required for high currents with light weight
copper planes. Examples are for approximately 10oC temp Rise. Wider
is Better! For microvias design for 1A/via For 14 mil diameter or
larger, 2A/via
Via Considerations: For microvias design for 1A/via For 14 mil
diameter or larger, 2A/via For 40 mil diameter or larger, 5A/via
For better heat spreading, allow viasto fill with solder Leave
copper path between clusters of vias Design Inner Planes Get Badly
Cut By Vias Microvias 1A/via
2017/4/27 Design Microvias 1A/via >20 mil diameter, 2A/via Inner
Planes Get Badly Cut By Vias Leave spacings Make sure that the vias
being used to route power are spaced to allow current flow in
intermediate layers. Layout Parallel signal trace with its
return
2017/4/27 Layout Parallel signal trace with its return High gate
and switch pin Current sense + and pins Feedback resistors at IC
Keep hi-Z paths short and use narrow traces By paralleling a signal
trace with its return, the inductive loop is minimized.This reduces
parasitic impedances.This includes the high side FET gate drive and
the return connected to the source of the FET.It should be noted
that some controllers may pull the high side FET to ground, and as
a result the return trace, ground, is not as critical.An example is
the LM The LM2642 has a floating drive where this does apply. At
the right, the proper layout for feedback resistors is
shown.Firgure b shows a case for a fixed output voltage where the
resistors are internal to the regulator.Figure d shows a case with
external feedback resistors.We keep the feedback resistors close to
the high impedance node, the feedback pin. In general, keep high
impedance nodes short because they pick up noise much more easily
than low impedance nodes (like the output capacitor). 2017/4/27 64
AN1197-Selecting Inductors for Buck Converters
AN1157-Positive to Negative Buck-Boost Converter Using LM267X
SIMPLE SWITCHER Regulators AN1149-Layout Guidelines for Switching
Power Supplies