20120405 Presentation Krishna
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Transcript of 20120405 Presentation Krishna
Power Reduction and Prediction Techniques for
3-D Reconfigurable Architectures
Krishna Chaitanya Nunna
(クリシュナ チャイタニャ ヌンナ) PhD Student
Kyushu University
Outline
• 3D FPGAs
• Power Issues
• Thermal Issues
• Target Work
• Plan
2012/4/5 2 Kyushu University
Outline
• 3D FPGAs
• Power Issues
• Thermal Issues
• Target Work
• Plan
2012/4/5 3 Kyushu University
FPGA
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Configurable Logic
Blocks
I/O Blocks
Programmable Interconnects
MEMORY FF
MU
X
MU
X
OUT
SEL SEL
LOGIC BLOCK
FPGA Architecture
SWITCH and CONNECTION BLOCKS
• Field-programmable gate arrays (FPGAs) – programmable logic devices (PLDs)
– can be configured by the end-user to implement any digital circuit.
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Synthesis
Technology Mapping
Bit Stream Generation
Application Description
Partitioning
Placement
Routing
FPGA Conventional CAD Flow
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Embedded Block
Logic Block
Connection Block
Switch Box
I/O pads
TSV
Wires
Island Style 3D FPGA
2012/4/5 6 Kyushu University
Outline
• 3D FPGAs
• Power Issues
• Thermal Issues
• Target Work
• Plan
2012/4/5 7 Kyushu University
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• More transistors are needed to implement a given logic circuit in an FPGA in comparison with a custom ASIC.
leads to a higher power consumption per logic gate in FPGAs and
power-efficiency is undisputed as an area in which ASICs are superior to FPGAs.
• Power has been cited as a limiting factor in the ability of FPGAs to continue to replace ASICs.
Power Issues
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Power components breakdown
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Total Power Consumption
Dynamic Power Static Power
Logic Blocks
Connection Boxes
Switch boxes
Active or Utilized Area
Logic Blocks
Connection Boxes
Switch boxes
Entire area
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Dynamic Power Breakdown in Xilinx Virtex-II [Shang02]
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Static Power Breakdown in Xilinx Spartan-3 [Tuan03]
[Shang02] L. Shang, A. Kaviani, and K. Bathala. “Dynamic Power Consumption in the Virtex-II FPGA Family". In: ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 157{164, Monterey, CA, 2002. [Tuan03] T. Tuan and B. Lai. “Leakage Power Analysis of a 90nm FPGA". In IEEE Custom Integrated Circuits Conference, pp. 57-60, San Jose, CA, 2003
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From our experiments
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0
50
100
150
200
250
300
66.5 70 83.5 90.5 97.25
Po
wer
in m
W
Circuit Size Increases----------->
Dynamic(Total)
Dynamic(Routing)
Static(Total)
Dynamic(Logic)
FPGA Array = 20x20 Channel Width = 50
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Power consumption due to routing resources dominates.
Static power is almost constant with increasing circuit size.
For early stage power estimation, concentration on utilized routing resources makes a big difference.
Outline
• 3D FPGAs
• Power Issues
• Thermal Issues
• Target Work
• Plan
2012/4/5 12 Kyushu University
Thermal Issues • Thermal management of FPGA devices is more critical compared to ASIC
solutions,
– as it dissipates more power, while their operating temperatures usually exceed the critical one.
– Also, the leakage current increases exponentially with temperature, causing a positive feedback loop between leakage power and temperature [Farzan05].
• The thermal problem is severe in the 3D cases for mainly two reasons:
– The vertically stacked multiple layers of active devices causes a rapid increase of power density;
– The thermal conductivity of the dielectric layers between the device layers is very low compared to silicon and metal.
• Temperature increase as a function of the number of chip-layers (n) and the power density in each layer.
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Thermal issues in 3D FPGAs are relatively unexplored.
[Farzan05] Farzan Fallah and Massoud Pedram, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, IEICE leakage review journal 2005
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Outline
• 3D FPGAs
• Power Issues
• Thermal Issues
• Target Work
• Plan
2012/4/5 14 Kyushu University
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Our proposed flow
Pros: thermal-aware partitioning
Cons: - unavailability of required information (for the first step) based on rough
assumptions for the partitioning
Synthesis
Technology Mapping
Bit Stream Generation
Application Description
3D Architecture Description TA
Partitioning
TA 2D/3D Placement
TA Layer Assignment
Accurate post-layout simulation
Layout information for next iteration
TA 3D Routing
We are targeting for a 3D FPGA EDA methodology which can be of power/thermal-aware.
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How The Performance Metrics are Considered?
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Power consumption
Temperature Timing
Partitioning Early estimation Early estimation
Cut size-implicit
Layer Assignment
considered
considered Cut size and net length
Placement More accurate estimation
More accurate estimation
Wirelength estimation
Routing Most accurate estimation
Most accurate estimation
Precise wirelength
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Estimating Power & Thermal Parameters
Power and Thermal
conditions are met?
Yes
No
Partitioning
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Synthesis
Technology
Mapping
Bit Stream Generation
Application Description
3D Architecture Description
TA Partitioning
TA 2D/3D
Placement
TA Layer
assignment
Accurate post-layout simulation
Layout information for next iteration
TA 3D
Routing
Present Status
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3D Partitioning- A Detailed View
Outline
• 3D FPGAs
• Power Issues
• Thermal Issues
• Target Work
• Plan
2012/4/5 18 Kyushu University
Future Plan and Conclusion
• Power and thermal-aware partitioning
• Power and thermal-aware placement
• Power and thermal-aware routing
• Dynamic thermal management
• Possible architecture exploration
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3D integration mitigates many of the restrictions introduced by existing design methodologies.
Thermal management of 3D reconfigurable architectures is critical as FPGAs exhibit high power consumption higher temperatures in 3D stack
Significant contribution can be made in this domain which can hopefully exhibits promising results.
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