Dajjali fitnay kay numayan khad o khal by shaykh syed manazir ahsan gilani (r a)
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Design and Implementation of Turbo Decoder for 4G
standards IEEE 802.16e and LTE
Syed Z. Gilani
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Motivation
Conventional serial decoding architectures can
be performance bottleneck
6144 bit block, 8 iterations @ 250MHz, 1 bit
processed per cycle=> data rate < 6144/
(6144*8*4ns)
~ 31Mbps
Data rates for LTE can be 100Mbps-300Mbps Parallel architecture necessary to support high
throughput decoding
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Maximum-a posteriori (MAP) algorithm
Alpha
Beta
Gamma
LLR
(De)Interleaver P(i) = (f1*i + f2*i2 )mod Nswitch (i mod 4)
case 0: P(i) = (P0*i + 1 )mod N case 1: P(i) = (P0*i + 1 + N/2 + P1 )mod N
case 2: P(i) = (P0*i + 1 + P2 )mod N case 3: P(i) = (P0*i + 1 +N/2 + P3 )mod N
Turbo Decoder Overview
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Optimizations
Resource Sharing
Retiming
Look-ahead transformation
Variable and adaptive parallelism
Multiplierless interleaver
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Parallelization
Time (cycles)
States
PE 1
PE 2
PE 3
PE 4
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Variable Parallelization
Parallel Interleaver
Bank
0
Bank
1
Bank
0
Bank
1
Coded Bits Decoded Bits
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Variable Parallelization
Parallel Interleaver
Bank
0
Bank
3
Bank1
Bank
2
Bank
0
Bank
3
Bank1
Bank
2
Coded Bits Decoded Bits
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Interleaver Optimization
Interleaving functions P(i) = (f1*i + f2*i
2 )mod N switch (i mod 4)
case 0: P(i) = (P0*i + 1 )mod N
case 1: P(i) = (P0*i + 1 + N/2 + P1 )mod N
case 2: P(i) = (P0*i + 1 + P2 )mod Ncase 3: P(i) = (P0*i + 1 +N/2 + P3 )mod N
Unoptimized Memory requirements Dont want to use multipliers and dividers
Storing all memory address in RAM LTE alone supprts 40 different block lengths with different
interleaving parameters
Block lengths vary from 40 bits to 6144 bits
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Interleaver Optimization On-the-fly address generation
LTE Interleaving FunctionP(i) = (f1*i + f2*i
2 )mod N
P(i+1) = (f1*(i+1) + f2*(i+1)2)mod N
= P(i) +( f1 +f2 +2 f2)mod N
Wimax Interleaving Functionswitch (i mod 4)
case 0: P(i) = (P0*i + 1 )mod N
case 1: P(i) = (P0*i + 1 + N/2 + P1 )mod N
case 2: P(i) = (P0*i + 1 + P2 )mod N
case 3: P(i) = (P0*i + 1 +N/2 + P3 )mod N P(i+1) = (P0 (i) + P0 + constant factor )mod N
Replace sum by residue whenever sum exceeds N to avoid mod N(subtraction)
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Interleaver Optimization
PE i P(i) Bank
Add.
Bit
Add.
0 0 1 0 1
1 300 1501 5 1
2 600 601 2 1
3 900 2101 7 1
4 1200 1201 4 1
5 1500 301 1 1
6 1800 1801 6 1
7 2100 901 3 1
PE i P(i) Bank
Add.
Bit
Add.
0 1 1320 4 120
1 301 420 1 120
2 601 1920 6 120
3 901 1020 3 120
4 1201 120 0 120
5 1501 1620 5 120
6 1801 720 2 120
7 2101 2220 7 120
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Lookahead Transformation
0
1
6
7
0 0
1
2
3
4
5
6
7
0
tk tk+1 tk tk+2
16 Comparisons required for lookahead transformation in Duo-binary
Wimax turbo codes
Increases throughput by 2x
Maximum clock rate decreases from 500MHz to ~300MHz along withsignificant increase in area
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Results
No of Iterations Number of PEs Throughput Serial throughput
2 2 490Mbps 243Mbps
2 4 909Mbps 243Mbps
2 8 1666Mbps 243Mbps
4 2 245Mbps 122Mbps
4 4 455Mbps 122Mbps
4 8 833Mbps 122Mbps
8 2 122Mbps 60Mbps
8 4 228Mbps 60Mbps
8 8 417Mbps 60Mbps
@ 500Mhz
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Questions
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Outline
Motivation
Turbo Encoding
Turbo Decoding
Optimizations Look-ahead transformation
Variable and adaptive parallelism
Multiplierless interleaver Results
Summary
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Turbo Encoder
LTE Turbo Encoding Wimax Turbo Encoding
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Parallelization
Example 4 state trellis
1 decoded symbol per cycle
Time (cycles)
States