04_Cost Effective Spread Spectrum Clock Generation Design_고려대_김철우
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Transcript of 04_Cost Effective Spread Spectrum Clock Generation Design_고려대_김철우
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Cost Effective Spread Spectrum Clock Generator Design
Chulwoo Kim, Minyoung Song, Sewook Hwang
Advanced Integrated Systems Lab.
Korea University, Seoul, Korea
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Outline
Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions
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Outline
Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions
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Electromagnetic Interference (EMI)
Severe at the higher frequency spectral component
System-level and chip-level
High performance design
high integrated and high speed
Various EMI reduction techniques
Shielding
External filtering
Spread spectrum clock generation
Introduction
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Shielding Hard to apply to inter-chip communications
Cost-expensive
Methods for EMI Reduction (1)
EMI Shielding w/ Metal Caps
CX2520SB (Kyocera)
EMI Shielding w/ Lids
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Low voltage differential clocking Decreasing the signal level directly
Cost of level conversion and complex routing
Reduced spectrum amplitude
SNR decrease as well as EMI reduction
Methods for EMI Reduction (2)
A
A/N
A/N
t t
f f
A
A/N
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External filtering Increasing the rise and fall times of the clock.
The larger rise and fall times, the lower high-frequency spectral components
Expensive
Hard to apply for high-frequency applications
Methods for EMI Reduction (3)
t
T
t
T
Tr Tf
f f
-20 dB/decade -20 dB/decade
-40 dB/decade
1T 1T1Tr
Tr=Tf
FILTERin out
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Outline
Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions
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Motivation
To use lower high-frequency spectral signal directly
To be more effective as well as simple and cost-efficient solution
Spread spectrum clock generation (SSCG) To shape its clock spectrum itself and reducing its
peak
To spread its spectrum itself, its output frequency should be changed slightly
Spread Spectrum Clock Generation : EMI Reduction of the Clock Itself
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Carsons rule gives the BW of frequency modulated waveform
Total energy of original signal is kept unaffected.
The 98% of the total energy is contained inside a BW calculated :
SSCGs use the modulation frequency more than 30 kHz
To avoid audible band (20 ~ 20kHz)
Typical values of mod. freq.: 30k ~ 250kHz
Carsons Rule
2 c mBW f f
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SSCG output frequency and modulated phase
fm: The modulation frequency
Decide how often the output frequency is changed
: The frequency deviation
Decide how much the frequency is changed
Some wireline applications (SATA, DisplayPort, etc. )
fm and as 30k ~ 33 kHz and 5000ppm, respectively
Equations for SSCG Output
s / 2 cos 2 / 2CKout c sf t V f t t V
0
, 0t
mt f t dt
c cf f
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fm defines the distance b/w consecutive harmonics (ripples).
fm and RBW of spectrum analyzer affect themeasured peak values.
Spectra Analysis (1)
BW
fm
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RBW >fm :The measured values will be higher than theoretical values by means of BPF characteristics
RBW >fm RBW
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Spectra Analysis (3)
10 log c
m
fS
f
[Komatsu, ASSCC 2007]
Peak reduction:
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Outline
Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions
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The frequency modulation profile To decide the shape of the spectrum EMI reduction
Conventional profiles The sinusoidal modulation
Easy to implement with analog circuit
Hard to implement with digital circuit
The triangular modulation Simple but not optimum for EMI reduction.
The Hershey-Kiss modulation Better EMI performance
Complex due to its non-linearity
Frequency Modulation Profile (1)
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0 1 2 3 4 5 6 7 8 9
x 10-6
-0.2
-0.1
0
0.1
0.2
Modulating waveform
time (ms)
Devia
tion (
%)
0 1 2 3 4 5 6 7 8 9
x 10-6
10
20
30
40
50
60
Modulating waveform integral
time (ms)
Angle
(ra
d)
1.475 1.48 1.485 1.49 1.495 1.5 1.505 1.51 1.515 1.52 1.525
x 109
-140
-120
-100
-80
-60
-40
-20After modulation
Side-band harmonics (GHz)
Am
plit
ude (
dB
V)
0 1 2 3 4 5 6 7 8 9 10
x 10-6
-0.2
-0.1
0
0.1
0.2
Modulating waveform
time (ms)
Devia
tion (
%)
1 2 3 4 5 6 7 8 9 10
x 10-6
0
20
40
60
80
100
Modulating waveform integral
time (ms)
Angle
(ra
d)
1.475 1.48 1.485 1.49 1.495 1.5 1.505 1.51 1.515 1.52 1.525
x 109
-140
-120
-100
-80
-60
-40
-20After modulation
Side-band harmonics (GHz)
Am
plit
ude (
dB
V)
Frequency Modulation Profile (2)
Sinusoidal Triangular Hershey-Kiss
Devia
tio
n (
,
%)
An
gle
(ra
d)
Am
pli
tud
e (
dB
V)
1 2 3 4 5 6 7 8 9
x 10-6
-0.2
-0.1
0
0.1
0.2
Modulating waveform
time (ms)
Devia
tion (
%)
1 2 3 4 5 6 7 8 9 10
x 10-6
0
20
40
60
80
Modulating waveform integral
time (ms)
Angle
(ra
d)
1.475 1.48 1.485 1.49 1.495 1.5 1.505 1.51 1.515 1.52 1.525
x 109
-140
-120
-100
-80
-60
-40
-20After modulation
Side-band harmonics (GHz)
Am
plit
ude (
dB
V)
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Profiles also affect the displacement of spread spectrum
Down spreading is preferable to guarantee setup/hold time margins
Displacement of Spectrum
Down
SpreadingCenter
Spreading
Up
Spreading
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Outline
Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG
Conclusions
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A DLL-based clock generator Hard to implement a finer frequency control
Changing its delay rather than frequency itself
A PLL-based clock generator Finer frequency control is available.
Frequency-controllable PLL
Clock Generation Architecture
PFD CP VCO
DIVIDER
REFCK
OUTPUTCK
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Direct control of input of VCO Controlling the CP current
Feeding external control voltage
Control the division ratio of the programmable feedback divider Controlling the division ratio
Design Approaches for SSCG
PFD CP VCO
DIVIDER
Method I:
Modulating input voltage of VCO
directly
Method II:
Controlling the division ratio of feedback
divider
LF
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PLL loop characteristic does not affect the SS modulation.
Suffers from PVT variations of CP, LF & VCO gain and generates additional jitter.
SSCG Using a Programmable CP
PFD VCO
Main Divider
CP1
DividerProgrammable
Charge Pump
Control Signals
Output CK
[Chang, JSSC 2003]
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modulator : To filter out quantization noise
Quantization noise issues Similar to fractional-N PLL
Solution PLL loop bandwidth small enough to filter out the quantization
noise
To design a modulator to shape the quantization noise better.
SSCG Using a Programmable Divider
PD LPF VCO
DIVIDER
Input CKOutput CK
Profile
[Kokubo, ISSCC 2005]
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Outline
Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG Piecewise Linear Modulation
Newton-Raphson Profile Generator
Conclusions
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Trade-off EMI performance vs. circuit complexity
The piecewise linear modulation profile (PWL) Linear operation
Simpler than Hershey-Kiss modulation
Higher EMI reduction Increasing the slopes near the maximum and minimum peaks
compare to triangular modulation
A Cost-Effective Design of SSCG
time
T1 T2 T1
Am
plitu
de
2Am
Am
-Am
1
2
1 2
4
1
2
14 2
m
m
m
m
T T
T T
T T Tf
14
mm
TA
14
mm
TA
[Song, CICC 2008]
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To find optimal value Condition
Optimum
1
1 2
11
04
4
1
mm
m m
m
TA
A T
T
4
5
6
7
8
9
x 104
0
0.2
0.4
0.6
0.8
1
-30
-28
-26
-24
-22
-20
-18
1; Slope of The Linear Signal During T
1
; Ratio Between T1 and T
2
Am
plit
ude [
dB
V]
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Simple implementation with digital circuits Synthesizable
Sync with SSCG reference clock
The -controller Generating an add value () to change the slope of
the modulation profile
The more # of , the higher EMI reduction
PWL Modulator
Register
+
-Controller
CK
Modulation
Profile
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The higher resolution of division ratio, the lower quantization noise
Fractional dividing with 10-multi-phase clock
Phase mixer : increases the resolution of division ratio
Proposed Fractional Divider
DR
En
Phase Mixer
MU
X 2Ckvco
Controller
/60CKfb
Sel
En
Mx
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Phase selecting A resolution of division ratio is improved by 10 times.
Dividing with Phase SelectingT
CKvco
CKvco
CKvco
CKvco
CKvco
CKvco
CKout
7/10*T 7/10*T 7/10*T
Shift -3
phases
Shift -3
phases
Shift -3
phases
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Trade-off: VCO multi-phase vs. Phase noise
20 effective clock phases generated without increasing the number of VCO delay line
Phase Mixing
DR
En
Phase Mixer
MU
X 2Ckvco
Controller
/60CKfb
Sel
En
Mx
Sel Sel Sel
H L H
Sel
En
Mx
CKfb
0.75xT 0.75xT
59.75xT
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9.7dB of peak reduction at 270MHz with down spreading can be achieved from this figure.
Ex. SSCG Spectrum Results
PWL modulated spectrum
Non-modulated spectrum
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Ex. Die Photo
Careful for clock skew and noise
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Performance Comparisons
Modulation
Profile
Freq. Deviation /
Modulation Freq.
Process
Power
Modulation
Method
Peak to peak jitter*
RMS jitter*
Output Frequency
Peak Reduction
*A jitter w/o spread-spectrum mode
Triangular
-5150~-350ppm
30.3 ~ 33.3us
0.13um
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Phase
Interpolation
57.2ps
9.3ps
Sugawara
SOVC 02
1.5GHz
7dB
Triangular
-5000 ~ 0ppm
32us
0.15um
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Phase
Interpolation
-
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Aoyama
SOVC 03
1.5GHz
5.43dB
Triangular
-5000 ~ 0ppm
32us
0.15um
54mW
Delta-Sigma
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Kokubo
ISSCC 05
1.5GHz
10dB[12]
Triangular
-5000 ~ 0ppm
33us
0.18um
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Delta-Sigma
41.01ps
3.07ps
Lee
ISSCC 05
1.5GHz
9.8dB
Area - - 0.42mm2 0.31mm2
Piecewise Linear
-5000 ~ 0ppm
32us
0.18um
40mW
Delta-Sigma
27.88ps
3.77ps
Song
CICC 08
1.5GHz
14.2dB
0.49mm2
Triangular
-20000 ~
0ppm
7.4 ~ 196us
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15.6mW
Delta-Sigma
80ps
10.7ps
Ebuchi
JSSC 09
125 ~ 1250MHz
10.9dB @ 104M
0.47mm2
Triangular
-7500 ~
7500 ppm
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0.35um
27.5mW
VCO
67ps
10.7ps
Hsieh
TCAS 08
400MHz
16.3dB
0.65mm2
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Outline
Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
Cost-Effective Design of SSCG Piecewise Linear Modulation
Newton-Raphson Profile Generator
Conclusions
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Newton-Raphson Profile Generator
1
1
2n n
n
xy y x
y
2 [ ][ ] [ ]
2 [ ]
a X nY n X n AB s
A X n AB
- Newton-Raphson formula - Proposed formula
[Hwang, ISSCC 2011]
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Newton-Raphson Profile Generator
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i)0 ( / 4)
[ ] [ ]
ii) ( / 4) ( / 2)
[ ] - [ ]
where ( 0,1,2,...)
m
m m
MAX
N R
n T
X n STEP CNT n
T n T
X n CNT STEP CNT n
n k T k
- Up/Down Counter
- STEP : Slope of X
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Newton-Raphson Profile Generator
2 [ ][ ] [ ]
2 [ ]
A X nY n X n AB S
A X n AB
2A
- A[4:0] : Profile Resolution
- B[3:0] : Profile Slope
- S[5:0] : Profile Scale Factor
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Newton-Raphson Profile Generator
- Shifter (A=25)
- Adder
- Shifter (A=25)
- Divider
- Shifter (S=25)
- Adder
2 [ ][ ] [ ]
[ ]
A X nY n X n AB S
X n AB
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Newton-Raphson Profile Generator
m m m
m m
16
i)0< < (T / 4), (3 T / 4)<
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Newton-Raphson Profile Generator
m m m
m m
16
i)0< < (T / 4), (3 T / 4)<
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Measured Modulation Profile
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Proposed Architecture
Double binary-weighted DAC modulates the frequency information inside the frequency-to-voltage converter (FVC) in the frequency-locked loop (FLL).
Newton-Raphson modulation profile is generated and transferred to the FLL by the digital spread-spectrum controller (DSSC).
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Measured EMI Reduction
42 cases : 14 and 3 fm
EMI Reduction : 19.14dB ~ 23.73dB
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Measured Spectra
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Die Micrograph
Process : 1P6M 0.13m CMOS
Area : 447.6m X 169.7m = 0.076mm2
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Comparison with Other Works
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Outline
Introduction
Spread Spectrum Clock Generation
Frequency Modulation Profile
Design Approaches for SSCG
A Cost-Effective Design of SSCG
Conclusions
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SSCG
A powerful solution to reduce EMI reduction
Becoming essential to many applications
EMI reduction affected by the freq. modulation profile
Future Trends
Proposal of new profile and its optimization
The SSCG is also a clock source as well as EMI reducing device.
it is also required to enhance jitter performance.
A technique to reduce quantization noise should be also developed.
New EMI reduction mechanism.
Conclusions
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References