02.07.20 11:22CSCI 150 Introduction to Digital and Computer

System Design Midterm Review II

Jetic Gū2020 Summer Semester (S2)

Overview• Focus: Review

• Architecture: Combinational Logic Circuit

• Textbook v4: Ch1-4; v5: Ch1-3

• Core Ideas:

1. Digital Information Representation (Lecture 1)

2. Combinational Logic Circuits (Lecture 2)

3. Combinational Functional Blocks, Arithmetic Blocks (Lecture 3)

Lecture 3: Combinational Logic Design

Summary

P3 Comb. Design

5 Steps Systematic Design Procedures; Functional Blocks; Decoder, Enabler, Multiplexer; Arithmetic Blocks

Systematic Design Procedures1. Specification: Write a specification for the circuit

2. Formulation: Derive relationship between inputs and outputs of the systeme.g. using truth table or Boolean expressions

3. Optimisation: Apply optimisation, minimise the number of logic gates and literals required

4. Technology Mapping: Transform design to new diagram using available implementation technology

5. Verification: Verify the correctness of the final design in meeting the specifications

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P3.1 Comb. Design

Hierarchical Design

• "divide-and-conquer"

• Circuit is broken up into individual functional pieces (blocks)

• Each block has explicitly defined Interface (I/O) and Behaviour

• A single block can be reused multiple times to simplify design process

• If a single block is too complex, it can be further divided into smaller blocks, to allow for easier designs

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P3.1 Comb. Design

Value-Fixing, Transferring, and Inverting

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t

P3.2 Elementary Func.

① Value-Fixing: giving a constant value to a wire

• ; ;

② Transferring: giving a variable (wire) value from another variable (wire)

• ;

③ Inverting: inverting the value of a variable

•

F = 0 F = 1

F = X

F = X

Vector Denotation

Concep

t

P3.2 Elementary Func.

④ Multiple-bit Function

• Functions we’ve seen so far has only one-bit output: 0/1

• Certain functions may have -bit output

• , each is a one-bit function

• Curtain Motor Control Circuit:

n

F(n − 1 : 0) = (Fn−1, Fn−2, . . . , F0) Fi

F = (FMotor1, FMotor2

, FLight)

Taking part of the Vector

Concep

t

P1 Elementary Func.124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN

least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.

Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.

EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing

The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the

0 F3

1 F2

A F1

A F0

(a)

0

1

A

A

1

2 34

F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

F(d)

FIGURE 3-8Implementation of Multibit Rudimentary Functions

M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM

④ Multiple-bit Function

124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN

least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.

Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.

EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing

The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the

0 F3

1 F2

A F1

A F0

(a)

0

1

A

A

1

2 34

F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

F(d)

FIGURE 3-8Implementation of Multibit Rudimentary Functions

M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM

Output: (F2, F1)

Output: (F3, F1, F0)

124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN

least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.

Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.

EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing

The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the

0 F3

1 F2

A F1

A F0

(a)

0

1

A

A

1

2 34

F

0

(b)

4 2:1 F(2:1)2

F(c)

4 3,1:0 F(3), F(1:0)3

F(d)

FIGURE 3-8Implementation of Multibit Rudimentary Functions

M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM

Dimension

Selected Indices

Enabler

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P3.2 Elementary Func.

⑤ Enabler

• Transferring function, but with an additional signal acting as switchEN

EN X F

0 X 0

1 0 0

1 1 1

Enabler

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P3.2 Elementary Func.

⑤ Enabler

• Transferring function, but with an additional signal acting as switchEN

ENX

F ENX

F

Decoder• -bit input, bits output

•

• Design: use hierarchical designs!

n 2n

Di = mi

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P3.3 Adv. Func. Blocks

A1 A0 D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

3-5 / Decoding 129

each output. In the logic diagram in Figure 3-13(b), each minterm is implemented by a 2-input AND gate. These AND gates are connected to two 1–to–2-line decoders, one for each of the lines driving the AND gate inputs.

Large decoders can be constructed by simply implementing each minterm function using a single AND gate with more inputs. Unfortunately, as decoders become larger, this approach gives a high gate-input cost. In this section, we give a! procedure that uses design hierarchy and collections of AND gates to con-struct!any decoder with n inputs and 2n outputs. The resulting decoder has the same or a lower gate-input cost than the one constructed by simply enlarging each AND gate.

To construct a 3–to–8-line decoder (n = 3), we can use a 2–to–4-line decoder and a 1–to–2-line decoder feeding eight 2-input AND gates to form the minterms. Hierarchically, the 2–to–4-line decoder can be implemented using two 1–to–2-line decoders feeding four 2-input AND gates, as observed in Figure 3-13. The resulting structure is shown in Figure 3-14.

The general procedure is as follows:

1. Let k = n.

2. If k is even, divide k by 2 to obtain k/2. Use 2k AND gates driven by two decod-ers of output size 2k/2. If k is odd, obtain (k + 1)/2 and (k - 1)/2. Use 2k AND

AD0 ! A

D0

D1 ! A

D1

0 1 01 0 1

(a) (b)

A

FIGURE 3-12A 1–to–2-Line Decoder

A1

0011

A0

0101

D0

1000

D1

0100

D2

0010

D3

0001

(a)

(b)

A

D A1A0

A1A0

A1A0

A1A0D

D

D

1

A0

FIGURE 3-13A 2–to–4-Line Decoder

M03_MANO0637_05_SE_C03.indd 129 23/01/15 1:51 PM

3-to-8 Decoder

01234567

0

1

2

Encoder

• Inverse operation of a decoder

• inputs, only one is giving positive input1

• outputs

2n

n

Concep

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P3.3 Adv. Func. Blocks

1. In reality, could be less

A0

A1

A2

A0

A1

A2

3-to-8 Decoder

01234567

0

1

2

Octal-to-Binary

Encoder

01234567

0

1

2

EncoderP3.3 Adv. Func. Blocks

Octal-to-Binary

Encoder

01234567

0

1

2

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Concep

t

A0 = D1 + D3 + D5 + D7

A1 = D2 + D3 + D6 + D7

A2 = D4 + D5 + D6 + D7

Priority Encoder

• Additional Validity Output

• Indicating whether the input is valid (contains 1)

• Priority

• Ignores if

V

D<i Di = 1

P3.3 Adv. Func. Blocks

Concep

t

Priority Encoder

0

1

2

3

0

1

V

Priority EncoderP3.3 Adv. Func. Blocks

Priority Encoder

0

1

2

3

0

1

V

Concep

t

D3 D2 D1 D0 A1 A0 V

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 X 0 1 1

0 1 X X 1 0 1

1 X X X 1 1 1

V = D3 + D2 + D1 + D0

A1 = D3 + D3D2 = D2 + D3

A0 = D3D2D1 + D3

= D2D1 + D3

Multiplexer

• Multiple -variable input vectors

• Single -variable output vector

• Switches: which input vectors to output

n

n

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t

P3.3 Adv. Func. Blocks

n

n

…

n

n

01

I0

I1

S

Y

Common Techniques

• Implementing Multiplexer using Decoders

• Implementing Multiplexer using smaller Multiplexers

• Implementing Sum-of-Minterm using Decoder(use OR gate)

• Implementing Sum-of-Minterm using Multiplexer(use value fixing)

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P3.3 Adv. Func. Blocks

• 1-bit Half Adder and Full Adder

• n-bit Adder

• 1-bit subtractor and n-bit subtractor

• 2s complement and binary adder-subtractor

Concep

t

P3.4 Arithmetic Blocks Arithmetic Blocks

1-bit Adder

• Half adderinput , output ,

X YS C

Review

P0 Binary Adder

X+Y

Augend

Carries

Addend

Sum S

C

+

InputOutput Z

X+Y

Augend

Carries

Addend

Sum S

C

+

InputOutput

• Full adderinput , , ;output ,

X Y ZS C

Unsigned Binary Subtraction

Review

P3.4 Arithmetic Blocks

0011010110

−1001100011

InputOutput

0101101001100011

0Minuend X0:n−1

Borrows

Subtrahend Y0:n−1

Difference D0:n−1

B Z

Technology• 1 bit Unsigned Subtractor

X0Y0Z

1-Bit Binary Subtractor

B

D D0

X1Y1

1-Bit Binary Subtractor

B

D D1

…

Full Unsigned Subtraction

Concep

t

P3.4 Arithmetic Blocks

ARITHMETIC FUNCTIONS AND HDLS

As we will see, this circuit is more complex than necessary. To reduce theamount of hardware, we would like to share logic between the adder and the sub-tractor. This can also be done using the notion of the complement. So before con-sidering the combined adder–subtractor further, we will take a more careful lookat complements.

Complements

There are two types of complements for each base-r system: the radix comple-ment, which we saw earlier for base 2, and the diminished radix complement. Thefirst is referred to as the r’s complement and the second as the (r ! 1)’s comple-ment. When the value of the base r is substituted in the names, the two types arereferred to as the 2s and 1s complements for binary numbers and the 10s and 9scomplements for decimal numbers, respectively. Since our interest for thepresent is in binary numbers and operations, we will deal with only 1s and 2scomplements.

Given a number N in binary having n digits, the 1s complement of N isdefined as (2n ! 1) ! N. 2n is represented by a binary number that consists of a1 followed by n 0s. 2n ! 1 is a binary number represented by n 1s. For example,if n " 4, we have 24 " (10000)2 and 24 ! 1 " (1111)2 . Thus, the 1s complementof a binary number is obtained by subtracting each digit from 1. When subtract-ing binary digits from 1, we can have either 1 ! 0 " 1 or 1 ! 1 " 0, which

A B

Binary adder Binary subtractor

Selective2's complementer

Quadruple 2-to-1multiplexer

Result

Borrow

Complement

S0 1Subtract/Add

FIGURE 6Block Diagram of Binary Adder–Subtractor

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X Y

Output

Concep

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P3.4 Arithmetic Blocks

ARITHMETIC FUNCTIONS AND HDLS

As we will see, this circuit is more complex than necessary. To reduce theamount of hardware, we would like to share logic between the adder and the sub-tractor. This can also be done using the notion of the complement. So before con-sidering the combined adder–subtractor further, we will take a more careful lookat complements.

Complements

There are two types of complements for each base-r system: the radix comple-ment, which we saw earlier for base 2, and the diminished radix complement. Thefirst is referred to as the r’s complement and the second as the (r ! 1)’s comple-ment. When the value of the base r is substituted in the names, the two types arereferred to as the 2s and 1s complements for binary numbers and the 10s and 9scomplements for decimal numbers, respectively. Since our interest for thepresent is in binary numbers and operations, we will deal with only 1s and 2scomplements.

Given a number N in binary having n digits, the 1s complement of N isdefined as (2n ! 1) ! N. 2n is represented by a binary number that consists of a1 followed by n 0s. 2n ! 1 is a binary number represented by n 1s. For example,if n " 4, we have 24 " (10000)2 and 24 ! 1 " (1111)2 . Thus, the 1s complementof a binary number is obtained by subtracting each digit from 1. When subtract-ing binary digits from 1, we can have either 1 ! 0 " 1 or 1 ! 1 " 0, which

A B

Binary adder Binary subtractor

Selective2's complementer

Quadruple 2-to-1multiplexer

Result

Borrow

Complement

S0 1Subtract/Add

FIGURE 6Block Diagram of Binary Adder–Subtractor

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ARITHMETIC FUNCTIONS AND HDLS

As we will see, this circuit is more complex than necessary. To reduce theamount of hardware, we would like to share logic between the adder and the sub-tractor. This can also be done using the notion of the complement. So before con-sidering the combined adder–subtractor further, we will take a more careful lookat complements.

Complements

There are two types of complements for each base-r system: the radix comple-ment, which we saw earlier for base 2, and the diminished radix complement. Thefirst is referred to as the r’s complement and the second as the (r ! 1)’s comple-ment. When the value of the base r is substituted in the names, the two types arereferred to as the 2s and 1s complements for binary numbers and the 10s and 9scomplements for decimal numbers, respectively. Since our interest for thepresent is in binary numbers and operations, we will deal with only 1s and 2scomplements.

Given a number N in binary having n digits, the 1s complement of N isdefined as (2n ! 1) ! N. 2n is represented by a binary number that consists of a1 followed by n 0s. 2n ! 1 is a binary number represented by n 1s. For example,if n " 4, we have 24 " (10000)2 and 24 ! 1 " (1111)2 . Thus, the 1s complementof a binary number is obtained by subtracting each digit from 1. When subtract-ing binary digits from 1, we can have either 1 ! 0 " 1 or 1 ! 1 " 0, which

A B

Binary adder Binary subtractor

Selective2's complementer

Quadruple 2-to-1multiplexer

Result

Borrow

Complement

S0 1Subtract/Add

FIGURE 6Block Diagram of Binary Adder–Subtractor

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X Y

Output

Adder Subtractor I

Adder-Subtractor II

Concep

t

P3.4 Arithmetic Blocks

ARITHMETIC FUNCTIONS AND HDLS

adder interconnected to form an adder–subtractor. We have used 2s complement,since it is most prevalent in modern systems. The 2s complement can be obtainedby taking the 1s complement and adding 1 to the least significant bit. The 1s com-plement can be implemented easily with inverter circuits, and we can add 1 to thesum by making the input carry of the parallel adder equal to 1. Thus, by using 1scomplement and an unused adder input, the 2s complement is obtained inexpen-sively. In 2s complement subtraction, as the correction step after adding, we com-plement the result and append a minus sign if an end carry does not occur. Thecorrection operation is performed by using either the adder–subtractor a secondtime with M ! 0 or a selective complementer as in Figure 6.

The circuit for subtracting A " B consists of a parallel adder as shown inFigure 5, with inverters placed between each B terminal and the correspondingfull-adder input. The input carry C0 must be equal to 1. The operation that is per-formed becomes A plus the 1s complement of B plus 1. This is equal to A plus the2s complement of B. For unsigned numbers, it gives A " B if or the 2scomplement of B " A if .

The addition and subtraction operations can be combined into one circuitwith one common binary adder. This is done by including an exclusive-OR gatewith each full adder. A 4-bit adder–subtractor circuit is shown in Figure 7. Input Scontrols the operation. When S ! 0 the circuit is an adder, and when S ! 1 the cir-cuit becomes a subtractor. Each exclusive-OR gate receives input S and one of theinputs of B, Bi. When S ! 0, we have Bi ! 0. If the full adders receive the value ofB, and the input carry is 0, the circuit performs A plus B. When S ! 1, we have Bi !1 = and C0 ! 1. In this case, the circuit performs the operation A plus the 2scomplement of B.

FA FA FA FA

S

B3

C3

S2 S1 S0S3C4

C2 C1 C0

A3 B2 A2 B1 A1 B0 A0

FIGURE 7Adder–Subtractor Circuit

A B#A B$

Bi

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Add/Subtract

Z

X0Y0X1Y1X2Y2X3Y3