005 Fpga Spartan Verilog 2003
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Transcript of 005 Fpga Spartan Verilog 2003
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Lab3-1 明峰 交大資工系
Lab 4: FPGA Implementation
Specification
RTL design and
Simulation
Logic Synthesis
Gate Level Simulation
ASI Layout FPGA Implementation
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Lab3-2 明峰 交大資工系
!hy Top"#o$n%
& #esign of comple' systems& Reduce time"to"ma()et
* sho(ten the design ve(ification loop
* focus on functionality
& +asie( and cheape( to e'plo(e diffe(ent design option
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Lab3-3 明峰 交大資工系
RTL #esign
& ha(acte(istics * fully cloc) d(iven RTL code $ith some behavio(al const(ucts * contain complete functional desc(iption
* cycle accu(ate
& oding style
* st(uctu(al desc(iption ,component connections-net"list.
* data flo$ desc(iption ,continuous assignment.
* RTL desc(iption ,al$ays bloc).
& combinational RTL
& se/uential RTL
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Lab3-5 明峰 交大資工系
St(uctu(al 7apping
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Lab3-6 明峰 交大資工系
Resou(ce Sha(ing
& +'ampleif ,op8code 9.( a c 5
else
( a b 5
& Sha(ing * a single AL; fo( the t$o additions
* a 7;< fo( the second input of the AL;
& =o"Sha(ing
* t$o adde(s fo( the t$o additions
* an output 7;< to select the output
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Lab3-9 明峰 交大資工系
7ulti"Level Logic >ptimi0ation
&7eet pe(fo(mance o( a(ea const(aints th(ough(est(uctu(ing and simplifications
* t$o"level minimi0ation
* common facto( e't(action
* common e'p(ession (esubstitution
& T(ade"off bet$een a(ea and delay
& In comme(cial use fo( seve(al yea(s * f 2 abcdabceabcdabcdaccdfabcdeabcdf
* f 3 bdg bdfg bdgbdeg
* f 2 c,a'.ac'
* f 3 g'
* ' d,bf. d,be.
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Lab3-10 明峰 交大資工系
Technology 7apping
&T(anslation of a technology independent(ep(esentation of a ci(cuit into a ci(cuit in a given
technology $ith optimal cost
& >ptimi0ation c(ite(ia
* minimum a(ea
* minimum delay
* meeting specified timing const(aints
* meeting specified timing const(aints $ith minimum a(ea
& ;sages
* Technology mapping afte( technology independent logic
optimi0ation
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Lab3-11 明峰 交大資工系
Sample cove(s
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Lab3-12 明峰 交大資工系
State 7achine Synthesis
&T(anslate state table o( g(aph * state minimi0ation * state assignment to minimi0e the cost function
& hallenges
* state machine decomposition
* state assignment fo( pe(fo(mance
* state assignment fo( testability
* e't(act state g(aph f(om implementation
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Lab3-13 明峰 交大資工系
Spartan II Features
Plentiful logic and memo(y (esou(ces
* 2BC to 399C system gates ,up to BD3E3 logic cells.
* ;p to B Cb bloc) RA7 sto(age
Fle'ible I-> inte(faces
* F(om H to 34 I->s
* 2H signal standa(ds
Advanced 93B-933um H"Laye( 7etal P(ocess
Jigh pe(fo(mance
* System f(e/uency as high as 399 7J0
Advanced loc) ont(ol $ith 4 #edicated #LLs
;nlimited Re"p(og(ammability Fully PI ompliant
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Lab3-14 明峰 交大資工系
Spartan-II Top-level Arc!tecture
& onfigu(able logic bloc)s
* Implement logic he(eK
& I-> bloc)s
* ommunicate $ith othe(
chips
* hoose f(om 2H signal
standa(ds
& loc) RA7
* >n"chip memo(y fo( highe(
pe(fo(mance
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Lab3-15 明峰 交大資工系
Spartan-II Top-level Arc!tecture
& loc)s and delay loc)ed
loops
* Synch(oni0e to cloc) on and
off chip
& Rich inte(connect (esou(ces
* Th(ee"state inte(nal buses
& Po$e( do$n mode
* Lo$e( /uiescent po$e(
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Lab3-16 明峰 交大資工系
"L# Sl!ce $S!%pl!&!e'(
& 2 L holds 3 slices
& +ach slice contains t$o sets
of the follo$ing:
* Fou("input L;T
& Any 4"input logic function
& >( 2H"bit ' 2 RA7
& >( 2H"bit shift (egiste(
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Lab3-17 明峰 交大資工系
"L# Sl!ce $cont)'(
& +ach slice contains t$o sets
of the follo$ing:
* a((y M cont(ol
& Fast a(ithmetic logic
& 7ultiplie( logic
& 7ultiple'e( logic
* Sto(age element
& Latch o( flip"flop
& Set and (eset
& T(ue o( inve(ted inputs
& Sync o( async cont(ol
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Lab3-18 明峰 交大資工系
CLB
MUXF6
Slice
LUT
LUT MUXF5
Slice
LUT
LUTMUXF5
*e'!cate' +,pans!on ult!ple,ers& 7;( any B"input function
& 7;( any H"input function
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Lab3-19 明峰 交大資工系
I./ #loc $S!%pl!&!e'(
& Registe(ed inputD outputD 6"state cont(ol
& P(og(ammable sle$ (ateD pull"upD pull"do$nD )eepe(
and input delay
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Lab3-20 明峰 交大資工系
I./ Inter&ace Stan'ar's& I-> can be p(og(ammed fo( 2H diffe(ent signal
standa(ds
* N> cont(ols ma'imum output s$ing
* NR+F sets inputD outputD th(ee"state cont(ol
& #iffe(ent ban)s can suppo(t diffe(ent standa(ds at the
same time
* Logic level t(anslation
* oa(ds $ith mi'ed standa(ds
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Lab3-21 明峰 交大資工系
I/#s /ran!e' As In'epen'ent #ans
& As many as eight ban)s on a
device
* Pac)age dependent
& +ach ban) can be assigned
any of the 2H signal
standa(ds
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Lab3-22 明峰 交大資工系
2ns
2 n s
2 n s2 n
s
CLB Array
! er&or%ance out!n
& Jie(a(chical (outing
* SinglesD he'esD longs
& Spa(se connections on longe(
inte(connects fo( high speed
& Routing delay depends
p(ima(ily on distance * #i(ection independent
* #evice"si0e independent
& P(edictable fo( ea(ly design
analysis
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Lab3-23 明峰 交大資工系
oer-'on o'e
& ont(olled by single po$e( do$n pin
& All inputs bloc)edD appea( lo$ inte(nally
& All outputs disabled
& All (egiste( states p(ese(ved
& Po$e("do$n status pin& Synch(onous $a)e up
& 299 uA typical
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Lab3-24 明峰 交大資工系
Mode
Config.Data
Format
Direction ofSyncroni!ing
Cloc" UseSla#eSerial
Serial FPGA receivesCCLK
• Processor or CPLD or another FPGA ( in Mastermode) controls configuration of slave FPGA
• Also for configuring multiple slave FPGAs in a
dais chain (!"D
# $%D
FPGA# etc&)&MasterSerial
Serial FPGA generatesCCLK
• FPGA in Master mode configures itself from aserial P%'M&
• Also# st FPGA (master) in dais chain controlsconfiguration of slave FPGA(s) in a dais chain&
Sla#e
$arallel
te FPGA receives
CCLK
Processor or CPLD controls the fast configuration of
slave FPGA&%TA& Serial FPGA receives
*CKMa+e use of e,isting -oundar scan port
There are four ways to program a Spartan-II FPGA
"on&!urat!on o'es
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Lab3-25 明峰 交大資工系
De#ice XC2S'5 XC2S() XC2S5) XC2S')) XC2S'5) XC2S2))
Logic Cells .$! /0! (0!1 !022 $111 3!/!
Bloc" *AM Bits (4#$1. !.#304 $!#041 .2#/42 ./#(3! 30#$..
Bloc" *AM +ty. . 4 1 (2 (! (.
Ma,. User -/s 14 ($! (04 (/4 !42 !1.
$ac"age 56(22 56(22
CS(.. CS(..
*6(.. *6(.. *6(.. *6(..
P6!21 P6!21 P6!21 P6!21 P6!21
FG!34 FG!34 FG!34 FG!34
FG.34 FG.34 FG.34
Spartan-II Fa%!l /verv!e
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Lab3-26 明峰 交大資工系
Spartan-II Arc!tecture Su%%ar
#elive(s all the )ey (e/ui(ements fo( ASI (eplacement
* 399D999 gates
* 399 7J0
* Fle'ible I-> inte(faces
* >n"chip dist(ibuted and bloc) RA7
* loc) management
* Lo$ po$e(
* omplete development system suppo(t
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Lab3-27 明峰 交大資工系
#esign Tools& Standa(d A+ ent(y and ve(ification tools
& R+ Gen
#esign Implementation
Ne(ification
Static Timing AnalysisD
In"i(cuit Testing
*es!n
+ntrS!%ulator
1 *es!n anaer
!l!n,
Foun'at!onor All!ance
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Lab3-28 明峰 交大資工系
Foundation P(oOect 7anage( & Integ(ates all tools into one envi(onment
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Lab3-29 明峰 交大資工系
Schematic +nt(y
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Lab3-30 明峰 交大資工系
A+LD Ne(ilog and NJ#L Te't +nt(y
& F(om schematic menu
,o( via J#L +dito(.D
select Jie(a(chy " =e$Symbol !i0a(dQ to
c(eate symbol& Select J#L +dito( M
Language Assistant to
lea(n by e'ampleD then
define bloc)& Synthesi0e to +#IF
5
4
3
1
2
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Lab3-31 明峰 交大資工系
State 7achine G(aphical +dito(
G(aphical edito( synthesi0es into A+L o( NJ#L code
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Lab3-32 明峰 交大資工系
Simulation " +asy to ;se and Lea(n
&enerate st!%uluseas!l an' :u!cl * Ceyboa(d toggling * Simple cloc) stimulus * ustom fo(mulas
& +as 'ebu!n
* !avefo(m vie$e( * Signals easily added and
(emoved * Simulato( access f(om
schematic * olo("coded values on
schematic& Scr!pt +'!tor
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Lab3-33 明峰 交大資工系
!hat is Implementation%
& 7o(e than Oust Place M Route
& Implementation includes many phases
* Translate; 7e(ge multiple design files into a single netlist
* ap; G(oup logical symbols f(om the netlist ,gates. into
physical components ,Ls and I>s.
* lace < oute; Place components onto the chipD connectthemD and e't(act timing data into (epo(ts
* T!%!n $S!%(; Gene(ate a bac)"annotated netlist fo( timing
simulation tools
* "on&!ure; Gene(ate a bitst(eam fo( device configu(ation
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Lab3-34 明峰 交大資工系
Te(minology
& P(oOect * Sou(ce file5 has a defined $o()ing di(ecto(y and family
& Ne(sion * A
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Lab3-35 明峰 交大資工系
Sta(ting the Flo$ +ngine
Foun'at!on ro=ect anaer
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Lab3-36 明峰 交大資工系
The Flo$ +ngineI%ple%entat!on
pases
I%ple%entat!on
status
essae area
Flo control buttons
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Lab3-37 明峰 交大資工系
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Lab3-38 明峰 交大資工系
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Lab3-39 明峰 交大資工系
Lab 4: "Segment #ecode(
& input U6:9V sig 5 -- 9"F
& output UH:9V cont(ol 5 -- active high
L+#2 L+# 3
a BH 4
b B2 3
c HB 49
d H4 4
e H 3
f B4 43
g B9 3E
a
g
d
b
c
f
e
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Lab3-40 明峰 交大資工系
4"bit 7agnitude ompa(ato(
& input U6:9V aD b 5
& input agbD albD aeb 5
& 22 input pins
&
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4"bit 7agnitude ompa(ato(
& output agboD alboD aebo 5
& ;se