中科院研究生院课程： VLSI 测试与可测试性设计

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VLSI Test Principles and Architectures Logic BIST1

中科院研究生院课程： VLSI 测试与可测试性设计

第 7讲逻辑自测试 (1)

李晓维中科院计算技术研究所

Email: [email protected]

http://test.ict.ac.cn

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Chapter 5Chapter 5

Logic Built-In Self-TestLogic Built-In Self-Test

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What is this chapter about?What is this chapter about? Basic concepts of logic BIST

BIST Design Rules

Test pattern generation techniques

Output response analysis techniques

Logic BIST Architecture

Fault Coverage Enhancement

Various BIST timing control diagrams

A Design Practice

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IntroductionIntroduction

What are the problems in today’s semiconductor testing? Traditional test techniques become quite

expensive No longer provide sufficiently high fault coverage

Why do we need built-in self-test (BIST)? For mission-critical applications Detect un-modeled faults Provide remote diagnosis

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BIST Techniques CategoriesBIST Techniques Categories

Online BIST Concurrent online BIST Non Concurrent online BIST

Offline BIST Functional offline BIST Structural offline BIST

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A General Form of Logic BISTA General Form of Logic BIST

Non-concurrent

BIST

Offline Online

ConcurrentFunctional Structural

[Abramovici 1994]

Logic BIST Techniques

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AA Typical Logic BIST SystemTypical Logic BIST System

Structural off-line BIST

Logic BIST

Controller

Test Pattern Generator (TPG)

Output Response Analyzer (ORA)

Circuit Under Test (CUT)

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BIST Design RulesBIST Design Rules

Logic BIST requires much more stringent

design restrictions when compared to

conventional scan. Therefore, when designing

a logic BIST system, it is essential that the

circuit under test meet all scan design rules

and BIST specific design rules, called BIST

design rules.

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Typical X-bounding MethodsTypical X-bounding Methods

Methods for blocking an unknown (X) source

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X-bounding Methods X-bounding Methods

Depending on the nature of each unknown (X) source,

several X-bounding methods can be appropriate for use.

Common problems:

(1) Increase the area of the design.

(2) Impact timing.

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Typical Unknown SourcesTypical Unknown Sources

Analog Blocks Adding bypass logic. Adding control-only scan point

Memories and Non-Scan Storage Elements Bypass logic Initialization

Combinational Feedback Loops Scan points

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Typical Unknown Sources (cont’d)Typical Unknown Sources (cont’d)

Asynchronous Set/Reset Signals using the existing scan enable (SE) signal to

protect each shift operation and adding a set/reset clock point (SRCK) on each set/reset signal to test the set/reset circuitry.

Set/ResetCircuitry

RD Q

FunctionalLogic

CK

0

1

Scan-In

SE

SRCK

[Abdel-Hafez 2004]

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Asynchronous Set/Reset Signals

CK

SRCK

SE

Shift Window Capture Window

… C1

Shift Window

C2

…

Capture Window

…

Shift Window

Timing control diagram for testing data and set/reset faults

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Tri-State Buses Re-synthesize each bus with multiplexers. One-hot decoder

A one-hot decoder for testing a tri-state bus with 2 drivers

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False Paths 0-control point 1-control point

Critical Paths Adding an extra input pin to a selected

combinational gate on the critical path.

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Multiple-Cycle Paths 0-control point 1-control point Holding certain scan cell output states

Floating Ports PI or PO must have a proper connection to Power

(Vcc) or Ground (Vss). Floating inputs to any internal modules must be

avoided.

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Bi-directional I/O Ports Fix the direction of each bi-directional I/O port to

either input or output mode.

BIST_mode

EN

D IO

Z

SE

Forcing a bi-directional port to output mode

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Re-TimingRe-TimingRaces and hazards caused by clock skews may occur between the TPG and the (scan chain) inputs of the CUT as well as between the (scan chain) outputs of the CUT and the ORA. To avoid these potential problems and ease physical implementation, we recommend adding re-timing logic between the TPG and the CUT and between the CUT and the ORA.

D Q

CK D Q

CK O R A

CK3

D Q

CK D Q

CK T P G

CK1 CK2

CUT

Re-timing logic among the TPG, CUT, and ORA

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Test Pattern GenerationTest Pattern Generation

Test pattern generators (TPGs) constructed from linear feedback shift registers (LFSRs)

TPG Exhaustive testing Pseudo-random testing Pseudo-exhaustive testing

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Standard LFSRStandard LFSR Consists of n D flip-flops and a selected

number of exclusive-OR (XOR) gates

An n-stage (external-XOR) standard LFSR

[Golomb 1982]

Si0 Si1Sin-2 Sin-1

hn-1 hn-2 h2 h1

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Standard Linear Feedback Shift Register (LFSR)Standard Linear Feedback Shift Register (LFSR)

X 0 ( t + 1)X 1 ( t + 1)

.

.

.X n -3 ( t + 1)X n -2 ( t + 1)X n -1 ( t + 1)

10...00

h 1

01...00

h 2

00...001

……

………

00...10

h n -2

00...01

h n -1

X 0 ( t )X 1 ( t )

.

.

.X n -3 ( t )X n -2 ( t )X n -1 ( t )

=

X ( t + 1) = T s X ( t ) ( T s is companion matrix )

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Standard n-Stage LFSR ImplementationStandard n-Stage LFSR Implementation

Autocorrelation – any shifted sequence same as original in 2n-1 – 1 bits, differs in 2n-1 bits

If hi = 0, that XOR gate is deleted

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Modular LFSRModular LFSR

Each XOR gate placed between two adjacent D flip-flops

An n-stage (internal-XOR) modular LFSR

[Golomb 1982]Si0 Si1 Sin-2

h1 h2 hn-2 hn-1

Sin-1

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Generic Modular LFSRGeneric Modular LFSR

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Example Modular LFSRExample Modular LFSR

f (x) = 1 + x2 + x7 + x8

Read LFSR tap coefficients from left to right

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LFSR PropertiesLFSR Properties

The internal structure of the n-stage LFSR can be described by a characteristic polynomial of degree n, f(x).

hi is either 1 or 0,depending on the feedback path

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LFSR PropertiesLFSR Properties

Let Si represent the contents of the n-stage LFSR after shifts of the initial contents,S0,of the LFSR, and Si(x) be the polynomial representation of Si

thi

If T is the smallest positive integer such that f(x) divides ,then the integer T is called the period of the LFSR.

Tx1

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4-stage standard and modular LFSRs4-stage standard and modular LFSRs

421 xxxf

• 4-stage Standard LFSR

• 4-stage Modular LFSR

41 xxxf

30 xs

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LFSR TheoryLFSR Theory

Cannot initialize to all 0’s – hangs

If X is initial state, progresses through states X, Ts X, Ts2 X,

Ts3 X, …

Matrix period:

Smallest k such that Tsk = I

k LFSR cycle length

Described by characteristic polynomial:

f (x) = |Ts – I X |

= 1 + h1 x + h2 x2 + … + hn-1 xn-1 + xn

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Modular Internal XOR LFSRModular Internal XOR LFSR Described by companion matrix Tm = Ts T

Internal XOR LFSR – XOR gates in between D flip-flops Equivalent to standard External XOR LFSR

With a different state assignment Faster – usually does not matter Same amount of hardware

X (t + 1) = Tm x X (t) f (x) = | Tm – I X |

= 1 + h1 x + h2 x2 + … + hn-1 xn-1 + xn

Right shift – equivalent to multiplying by x, and then dividing by characteristic polynomial and storing the remainder

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Modular LFSR MatrixModular LFSR Matrix

X0 (t + 1)X1 (t + 1)X2 (t + 1)

..

.Xn-3 (t + 1)Xn-2 (t + 1)Xn-1 (t + 1)

001...000

000...010

010...000

………

………

000...001

1h1h2...

hn-3hn-2hn-1

X0 (t)X1 (t)X2 (t)..

.Xn-3 (t)Xn-2 (t)Xn-1 (t)

=

000...000

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Primitive polynomials list Primitive polynomials list Primitive polynomials of degree n up to 100

013424)( xxxxxxp Note: “24 4 3 1 0” means

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Exhaustive TestingExhaustive Testing

Exhaustive Testing Applying exhaustive patterns to an n-input

combinational circuit under test (CUT)

Exhaustive pattern generator Binary counter Complete LFSR

n2

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Binary counterBinary counter

Example binary counter as EPG

X1 X3

X4X2

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Complete LFSRComplete LFSR

Example complete LFSRs as EPG

0 0 0 1 0 0 0 1

0 0 0 1 1 0 0 0

(a) 4-stage standard CFSR (b) 4-stage modular CFSR

(c) A minimized version of (a)

(d) A minimized version of (b)

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Exhaustive Testing performanceExhaustive Testing performance

Exhaustive Testing guarantees all detectable, combinational faults will be detected.

Test time maybe be prohibitively long if input number is large than 20.

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Pseudo-Random TestingPseudo-Random Testing

Pseudo-random pattern generator Reduce test length but sacrifice the fault

coverage Difficult to determine the required test

length and fault coverage

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Pseudo-Random TestingPseudo-Random Testing

Maximum-length LFSR RP-resistant problem

Weighted LFSR Cellular Automata

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Weighted LFSRWeighted LFSR

Example weighted LFSR as PRPG

X1

1 0

X2

X3

X4

0 1

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Weighted Pattern GeneratorWeighted Pattern Generator

w1

0000

w2

0011

Inv.0101

p (output)½½¼

3/4

w1

1111

w2

0011

p (output)1/87/8

1/1615/16

Inv.0101

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Cellular AutomataCellular Automata

Provide more random test patterns Provide high fault coverage in a random-

pattern resistant (RP-resistant) circuit Implementation advantage

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Memory

Function f

xi(t) to its right cell

xi(t+1) from the right cell

to its left cell xi(t)

111 110 101 100 011 010 001 000

0 1 0 1 1 0 1 0

1 0 1 1 0 0 0 1Rule 90Rule 177

27 26 25 24 23 22 21 20

An example of two rules, 90 and 177, of a CA

A CA cell structure


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A general structure of an n-stage CA

Each rule determines the next state of a cell based on the state of the cell and its neighbors

‘0’

‘0’

Cell0

Cell1

Celln-2

Celln-1

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Example cellular automatonExample cellular automaton

A 4-stage CA Test sequence

0 0 0 10 0 1 00 1 1 11 1 1 10 0 1 10 1 0 11 0 0 01 1 0 00 1 1 01 1 0 10 1 0 01 0 1 01 0 1 11 0 0 11 1 1 0

X0 X1

‘0’

‘0’

X3X2

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CA construction rulesCA construction rulesConstruction rules for cellular automata of length n up to 53

[Hortensius 1989]

*For n=7, Rule=152=001,101,010=1,101,010, where “0” denotes a rules 90 and “1” denotes a rule 150 cell, or vice versa

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Pseudo-Exhaustive Testing Pseudo-Exhaustive Testing

Reduce test time while retaining many advantages of exhaustive testing

Guarantee 100% single-stuck fault coverage

Verification test technique [McCluskey 1984] Segmentation test technique [McCluskey 1981]

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Verification TestingVerification Testing

Divide the CUT into m cones, backtracing from each output to determine the inputs that drive the output. Each cone will receive

exhaustive test patterns and are tested concurrently. [McCluskey 1984]

x1

y1

x2

y2

x3

y3

x4

y4

Pseudo-exhaustive pattern generatorsPEPGs

An (n, w)=(4, 2) CUT

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Syndrome Driver CounterSyndrome Driver Counter

Use SDC to generate test patterns. Check whether some inputs can share the same test signal. If n-p Inputs can share test inputs with other p inputs, then the circuit can be tested exhaustively with these

p inputs. [Savir 1980]

A 3-stage syndrome driver counter

X1 X2 X3

X4

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Constant-Weight CounterConstant-Weight Counter

Use CWCs to generate test patterns. Constant-Weight counters are constructed using constant-weight code or M-out-of-N code. The constant-weight test set is a minimum-length test set for many circuits.

[McCluskey 1982]

A 3-stage constant-weight counterX1 X2 X3

X4

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Combined LFSR/SRCombined LFSR/SRUse a combination of an LFSR and a shift register (SR) for patterngeneration. The method is most effective when w is much less than n.In general, this technique requires much more tests than other schemes when w is greater than n/2.

[Barzilai 1983 ] [Tang 1984]

A 4-stage combinedLFSR/SRX1 X2 X3 X4

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Combined LFSR/PSCombined LFSR/PSA combined LFSR/PS approach using a combination of an LFSR and a linear phase shifter which includes a network of XOR gates to generate test pattern. Similar to combined LFSR/SR, this technique requires more tests than other schemes when w is greater than n/2.

[Vasanthavada 1985]

A 3-stage combined LFSR/PSX1 X2 X3

X4

X1 X2 X3

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Condensed LFSRCondensed LFSR

)]1/([]1/[ knkknkw

Condensed LFSRs are constructed based on linear codes.Define g(x) and p(x) as the generator polynomial and primitive polynomial over GF(2), respectively. An (n, k) condensed LFSR

can be realized using

Where

[Wang 1986a]

)()...1()()()( 2 xpxxxxpxgxf kn

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Example Condensed LFSR Example Condensed LFSR

A (4,3) condensed LFSR Test sequence

1100011000111010010110011111

Set

X1 X2 X3 X4

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Cyclic LFSRCyclic LFSR

Use cyclic LFSRs to reduce the test length when w < n/2.

A cyclic code always exists when

1,12' bn b

find a generator polynomial g(x) of largest degree k’ (or smallest degree k), for generating an (n’,k’) = (n’,n’-k) cyclic code, that divides 1+x^^n’ and has a design distance d > w+1;

construct an (n’,k) cyclic LFSR using f(x) = h(x)p(x) = (1+x^^n’)p(x)/g(x), where h(x) = (1+x^^n’)/g(x); and

shorten this (n’,k) cyclic LFSR to an (n,k) cyclic LFSR by deleting the rightmost, middle, or leftmost n’-n stages from the (n’,k) cyclic LFSR.

To exhaustively test any (n,w) CUT

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Example Cyclic LFSR Example Cyclic LFSR A (8,5) cyclic LFSR, picking the first 6 stages and the last two stages of the (15,5) cyclic LFSR.

An (n,k-s) shorted cyclic LFSR can be employed when

1 0 1 0 0 1 0 0

22 , bn b

1 0 1 0 1 0 1 0

[Wang 1987b]

[Wang 1988b]

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Compatible LFSR Compatible LFSR

(a) An (n,w) = (5,4) CUT (b) A 2-stage compatible LFSR

The combined LFSR of an l-stage LFSR and an l-to-n mapping logic,

called l-stage compatible LFSR, can further reduce the test length,

when only single stuck faults are considered.

Y1

Y2

X1

X2

X3

X4

X5

0 0

X1 X2 X3 X5X4

Example compatible LFSR as PEPG

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Segmentation TestingSegmentation Testing

Used when Test length using previous techniques is too long

or Output depends on all inputs.

Divide the circuit into segments Hardware partitioning Sensitized partitioning

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Delay Fault TestingDelay Fault Testing

Need patterns to test delay fault exhaustively

Test set could cause test invalidation when more than one inputs change.

122 nn

TESTTYPE

X1 X2 Xn-1Xn

hn-1 hn-2 h2 h1

0

1 [Bushnell 2000]

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Output Response AnalysisOutput Response Analysis

Ones count testing Transition count testing Signature analysis

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Ones Count TestingOnes Count Testing

},,{ 1210 Lrrrr

Assume the CUT has one output and the output contains a stream of L bits. Let the fault-free output response be

Aliasing probability [Savir 1985]

Ones count testing will need a counter to count the number of 1s in the bit stream.

)12/()1),(()( LOC mLCmP

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One Count TestingOne Count Testing

SignatureCUT

T

Counter

CLK

One counter as ORA

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Transition Count TestingTransition Count TestingTransition count testing is similar to that for ones count testing, except the signature is defined as the number of 1-to-0 and 0-to-1 transitions.

Aliasing probability

[Hayes 1976]

)12/()1),1(2()( LTC mLCmP

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Transition Count TestingTransition Count Testing

Transition counter as ORA

CUTT SignatureCounter

CLK

D Q

riri-1

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Transition CountingTransition Counting

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Signature AnalysisSignature AnalysisSignature analysis is the most popular compaction technique used today, based on cyclic redundancy checking.

Two signature analysis schemes Serial signature analysis Parallel signature analysis

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Serial Signature AnalysisSerial Signature Analysis

11210 ...)(

LL xmxmxmmxM

An n-stage single-input signature register

Define L-bit output sequence M

Let the polynomial of the modular be f(x)

IFSignature is the

polynomial remainder, r(x))()()()( xrxfxqxM

r0 rn-2 rn-1

h1 h2 hn-2 hn-1

M r1

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ExampleExample

A 4-stage SISR

M

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Parallel Signature AnalysisParallel Signature AnalysisMultiple-input signature register (MISR)

An n-input MISR can be remodeled as a single-input SISR witheffective input sequence M(x) and effective error polynomial E(x)

)()(...)()()( 11

22

10 xMxxMxxxMxMxM nn

nn

)()(...)()()( 11

22

10 xExxExxxExExE nn

nn

M1 M2M0 Mn-2 Mn-1

h1 h2 hn-2 hn-1

r0 r1 rn-1rn-2

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Multiple-Input Shift Register (MISR)Multiple-Input Shift Register (MISR)

X0 (t + 1)X1 (t + 1)X2 (t + 1)

001

010

110

=X0 (t)X1 (t)X2 (t)

d0 (t)d1 (t)d2 (t)

+X0 (t + 1)X1 (t + 1)X2 (t + 1)

001

010

110

=X0 (t)X1 (t)X2 (t)

d0 (t)d1 (t)d2 (t)

+X0 (t)X1 (t)X2 (t)

d0 (t)d1 (t)d2 (t)

+

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4-stage MISR4-stage MISR

A 4-stage MISR

M0

M1

M2

M3

1 0 0 1 00 1 0 1 0

1 1 0 0 0

1 0 0 1 1

1 0 0 1 1 0 1 1M

An equivalent M sequence

Aliasing probability

)12/()12()( )( mLnmLPSA nP

M1M2M0 M3

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Experiment HardwareExperiment Hardware

3 bit exhaustive binary counter for pattern generator

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Transition Counting vs. LFSRTransition Counting vs. LFSR LFSR aliases for f sa1, transition counter for a sa1

Pattern

abc000001010011100101110111

Transition CountLFSR

Good01000111

3001

a sa101110111

Signatures

3101

f sa111111111

0001

b sa100001111

1010

Responses

000001010011100101110111

01000111

3001

a01110111

3101

sa111111111

0001

b sa100001111

1010

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8038680386 中的中的 BISTBIST结构结构

350乘积线

PLA1LFSR

LFSR

13 16

175乘积线

PLA3LFSR

LFSR

19 12

160乘积线

PLA2LFSR

LFSR

16 18

95K位

CROMLFSR

LFSR

12 37

控制

EAX寄存器

LFSR LFSR

LFSR LFSR

ALU

16

16

16

1632 32

32

特征值 M总线复位BUSY

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LFSRLFSR 的大小和特征多项式的大小和特征多项式模块数目特征多项式控制 PLA输入输出乘积线

1912175

X19+X5+X2+X+1X12+X7+X4+X+1

入口 PLA输入输出乘积线

1316350

X13+X4+X3+X+1X16+X12+X3+X+1

测试 PLA输入输出乘积线

1618160

X16+X12+X3+X+1X18+X7+1

CROM输入输出字数

12372560

二进制计数器X378+X12 +X10 +X2 +1

入口 PLA输入 16 X16+X12+X3+X+1

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BISTBIST结构的开销结构的开销项目测试面

积被测面

积测试晶

体管被测晶体

管点被测晶体

管配置占用面积 (%)

控制 PLA

入出

360

140

2100 500

320

6790 2890 23.8

入口 PLA

入出

243

164

3500 320

450

11600 6170 11.6

测试 PLA

入出

101

121

1950 240

350

6870 3760 11.4

合并 1090 1200 100

CROM 531 9100 1000 95700 24800 5.8

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中科院研究生院课程： VLSI测试与可测试性设计

下次课预告

时间： 2007 年 11 月 12 日（周一 7:00pm ）

地点： S106 室内容：逻辑自测试 (2)

教材： VLSI TEST PRINCIPLES AND ARCHITECTURES

Chapter 5 Logic Built-In Self-Test

中科院研究生院课程： VLSI 测试与可测试性设计

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