˘ ˇ ˘ ˆ˙ ˇ ˆ ˇvega.unitbv.ro/~pana/TST/IA_proiect.CIA/Foi de catalog... · 2018-02-24 ·...

SLOS157B − JUNE1996 − REVISED APRIL 2005

3−1WWW.TI.COM

Output Swing Includes Both Supply Rails

Low Noise . . . 19 nV/√Hz Typ at f = 1 kHz

Low Input Bias Current . . . 1 pA Typ

Fully Specified for Single-Supply 3-V and5-V Operation

Very Low Power . . . 110 µA Typ

Common-Mode Input Voltage RangeIncludes Negative Rail

Wide Supply Voltage Range2.7 V to 10 V

Macromodel Included

description

The TLV2221 is a single low-voltage operational amplifier available in the SOT-23 package. It offers acompromise between the ac performance and output drive of the TLV2231 and the micropower TLV2211.

It consumes only 150 µA (max) of supply current and is ideal for battery-powered applications. The deviceexhibits rail-to-rail output performance for increased dynamic range in single- or split-supply applications. TheTLV2221 is fully characterized at 3 V and 5 V and is optimized for low-voltage applications.

The TLV2221, exhibiting high input impedance and low noise, is excellent for small-signal conditioning forhigh-impedance sources, such as piezoelectric transducers. Because of the micropower dissipation levelscombined with 3-V operation, these devices work well in hand-held monitoring and remote-sensingapplications. In addition, the rail-to-rail output feature with single or split supplies makes this family a greatchoice when interfacing with analog-to-digital converters (ADCs).

With a total area of 5.6mm2, the SOT-23 package only requires one third the board space of the standard 8-pinSOIC package. This ultra-small package allows designers to place single amplifiers very close to the signalsource, minimizing noise pick-up from long PCB traces. TI has also taken special care to provide a pinout thatis optimized for board layout (see Figure 1). Both inputs are separated by GND to prevent coupling or leakagepaths. The OUT and IN− terminals are on the same end of the board to provide negative feedback. Finally, gainsetting resistors and decoupling capacitor are easily placed around the package.

VI VDD+

OUTIN−

VDD/GND

IN+C

RI

RF

GND

V+

VO

1

2

3

4

5

Figure 1. Typical Surface Mount Layout for a Fixed-Gain Noninverting Amplifier

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DBV PACKAGE(TOP VIEW)

5

43

1

2

IN−

VDD−/GND

IN+ VDD+

OUT

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Copyright 1997 −2005, Texas Instruments Incorporated

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

SLOS157B − JUNE1996 − REVISED APRIL 2005

3−2 WWW.TI.COM

AVAILABLE OPTIONS

TA VIOmax AT 25 °CPACKAGED DEVICES

SYMBOLCHIP

FORM‡TA VIOmax AT 25 °CSOT-23 (DBV)†

SYMBOL FORM‡

(Y)0°C to 70°C 3 mV TLV2221CDBV VADC

TLV2221Y−40°C to 85°C 3 mV TLV2221IDBV VADI

TLV2221Y

† The DBV package available in tape and reel only.‡ Chip forms are tested at TA = 25°C only.

TLV2221Y chip information

This chip, when properly assembled, displays characteristics similar to the TLV2221C. Thermal compressionor ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip may be mounted withconductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 10 MILS TYPICAL

BONDING PADS: 4 × 4 MILS MINIMUM

TJmax = 150°C

TOLERANCES ARE ±10%.

ALL DIMENSIONS ARE IN MILS.

PIN (2) IS INTERNALLY CONNECTEDTO BACKSIDE OF CHIP.

+

−OUT

IN+

IN−

VDD+(5)

(1)

(3)(4)

(2)

VDD−/GND

40

(3)

(2)

(1) (5)

(4)

32

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †

Supply voltage, VDD (see Note 1) 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input voltage, VID (see Note 2) ±VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (any input, see Note 1) −0.3 V to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input current, II (each input) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current into VDD+ ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current out of VDD− ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Duration of short-circuit current (at or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA: TLV2221C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV2221I −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DBV package 260°C. . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to VDD −.2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought

below VDD− − 0.3 V.3. The output can be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum

dissipation rating is not exceeded.

DISSIPATION RATING TABLE

PACKAGETA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C

PACKAGETA ≤ 25 C

POWER RATINGDERATING FACTORABOVE TA = 25°C

TA = 70 CPOWER RATING

TA = 85 CPOWER RATING

DBV 150 mW 1.2 mW/°C 96 mW 78 mW

recommended operating conditions

TLV2221C TLV2221IUNIT

MIN MAX MIN MAXUNIT

Supply voltage, VDD 2.7 10 2.7 10 V

Input voltage range, VI VDD− VDD+ −1.3 VDD− VDD+ −1.3 V

Common-mode input voltage, VIC VDD− VDD+ −1.3 VDD− VDD+ −1.3 V

Operating free-air temperature, TA 0 70 −40 85 °C

NOTE 1: All voltage values, except differential voltages, are with respect to VDD −.


5WWW.TI.COM

electrical characteristics at specified free-air temperature, V DD = 3 V (unless otherwise noted)

PARAMETER TEST CONDITIONS TA†TLV2221C TLV2221I

UNITPARAMETER TEST CONDITIONS TA†MIN TYP MAX MIN TYP MAX

UNIT

VIO Input offset voltage 0.62 3 0.62 3 mV

VIO

Temperaturecoefficient of input

Full range1 1 V/°CαVIO coefficient of input

offset voltage

Full range1 1 µV/°C

Input offset voltagelong-term drift(see Note 4)

VDD± = ±1.5 V,VO = 0,

VIC = 0,RS = 50 Ω

25°C 0.003 0.003 µV/mo

IIO Input offset current

O S

25°C 0.5 0.5pAIIO Input offset current

Full range 150 150pA

IIB Input bias current25°C 1 1

pAIIB Input bias currentFull range 150 150

pA

0 −0.3 0 −0.325°C

0to

−0.3to

0to

−0.3to

VICRCommon-mode input

RS = 50 Ω |VIO| ≤5 mV

25 C to2

to2.2

to2

to2.2

VVICRCommon-mode inputvoltage range RS = 50 Ω, |VIO| ≤5 mV

0 0Vvoltage range

Full range0to

0toFull range to

1.7to

1.7

High-level outputIOH = −100 µA 25°C 2.97 2.97

VOHHigh-level outputvoltage IOH = −400 A

25°C 2.88 2.88 VVOH voltage IOH = −400 µAFull range 2.5 2.5

V

Low-level output VIC = 1.5 V, IOL = 50 µA 25°C 15 15

VOLLow-level output voltage VIC = 1.5 V, IOL = 500 A

25°C 150 150 mVVOL voltage VIC = 1.5 V, IOL = 500 µAFull range 500 500

mV

Large-signalV = 1.5 V, RL = 2 kΩ‡

25°C 2 3 2 3

AVD

Large-signaldifferential voltage

VIC = 1.5 V,VO = 1 V to 2 V

RL = 2 kΩ‡Full range 1 1 V/mVAVD differential voltage

amplificationVO = 1 V to 2 V

RL = 1 MΩ‡ 25°C 250 250

V/mV

ridDifferential inputresistance

25°C 1012 1012 Ω

ricCommon-mode inputresistance

25°C 1012 1012 Ω

cicCommon-mode inputcapacitance

f = 10 kHz 25°C 6 6 pF

zoClosed-loop output impedance

f = 10 kHz, AV = 10 25°C 90 90 Ω

CMRRCommon-mode VIC = 0 to 1.7 V, 25°C 70 82 70 82

dBCMRRCommon-moderejection ratio

VIC = 0 to 1.7 V,VO = 1.5 V, RS = 50 Ω Full range 65 65

dB

kSVR

Supply voltage rejection ratio

VDD = 2.7 V to 8 V, 25°C 80 95 80 95dBkSVR rejection ratio

(∆VDD /∆VIO)

VDD = 2.7 V to 8 V,VIC = VDD/2, No load Full range 80 80

dB

IDD Supply current VO = 1.5 V, No load25°C 100 150 100 150

µAIDD Supply current VO = 1.5 V, No loadFull range 200 200

µA

† Full range for the TLV2221C is 0°C to 70°C. Full range for the TLV2221I is − 40°C to 85°C.‡ Referenced to 1.5 VNOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated

to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.


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operating characteristics at specified free-air temperature, V DD = 3 V



UNIT

Slew rate at unity VO = 1.1 V to 1.9 V, RL = 2 kΩ‡,25°C 0.1 0.18 0.1 0.18

SRSlew rate at unitygain

VO = 1.1 V to 1.9 V,CL = 100 pF‡

RL = 2 kΩ‡,Full

range0.05 0.05

V/µs

VnEquivalent input f = 10 Hz 25°C 120 120

nV/√HzVnEquivalent inputnoise voltage f = 1 kHz 25°C 20 20

nV/√Hz

VN(PP)

Peak-to-peakequivalent input

f = 0.1 Hz to 1 Hz 25°C 680 680nVVN(PP) equivalent input

noise voltage f = 0.1 Hz to 10 Hz 25°C 860 860nV

InEquivalent inputnoise current

25°C 0.6 0.6 fA /√Hz

VO = 1 V to 2 V,f = 20 kHz,

AV = 125°C

2.52% 2.52%

THD+NTotal harmonic

Of = 20 kHz,RL = 2 kΩ‡ AV = 10

25°C7.01% 7.01%

THD+NTotal harmonic distortion plus noise VO = 1 V to 2 V,

f = 20 kHz,AV = 1

25°C0.076% 0.076%O

f = 20 kHz,RL = 2 kΩ§ AV = 10

25°C0.147% 0.147%

Gain-bandwidthproduct

f = 1 kHz, CL = 100 pF‡

RL = 2 kΩ‡,25°C 480 480 kHz

BOM

Maximumoutput-swingbandwidth

VO(PP) = 1 V, RL = 2 kΩ‡,

AV = 1,CL = 100 pF‡ 25°C 30 30 kHz

ts Settling time

AV = −1,Step = 1 V to 2 V,

‡

To 0.1% 25°C 4.5 4.5 µs

ts Settling timeStep = 1 V to 2 V,RL = 2 kΩ‡,CL = 100 pF‡ To 0.01% 25°C 6.8 6.8 µs

φmPhase margin atunity gain RL = 2 kΩ‡, CL = 100 pF‡

25°C 51° 51°

Gain margin

RL = 2 kΩ‡, CL = 100 pF‡

25°C 12 12 dB† Full range is −40°C to 85°C.‡ Referenced to 1.5 V§ Referenced to 0 V


7WWW.TI.COM

electrical characteristics at specified free-air temperature, V DD = 5 V (unless otherwise noted)



UNIT

VIO Input offset voltage 0.61 3 0.61 3 mV

VIO

Temperaturecoefficient of input

Full range1 1 V/°CαVIO coefficient of input

offset voltage

Full range1 1 µV/°C

Input offset voltagelong-term drift(see Note 4)

VDD± = ±2.5 V,VO = 0,

VIC = 0,RS = 50 Ω

25°C 0.003 0.003 µV/mo

IIO Input offset current

O S

25°C 0.5 0.5pAIIO Input offset current

Full range 150 150pA

IIB Input bias current25°C 1 1

pAIIB Input bias currentFull range 150 150

pA

VICRCommon-mode input

RS = 50 Ω |VIO| ≤5 mV

25°C0to4

−0.3to

4.2

0to4

−0.3to

4.2VVICR

Common-mode inputvoltage range RS = 50 Ω, |VIO| ≤5 mV

Full range0to

3.5

0to

3.5

V

VOHHigh-level output IOH = −500 µA

25°C4.75 4.88 4.75 4.88

VVOHHigh-level outputvoltage IOH = −1 mA

25°C4.5 4.76 4.5 4.76

V

Low-level outputVIC = 2.5 V, IOL = 50 µA 25°C 12 12

VOLLow-level outputvoltage VIC = 2.5 V, IOL = 500 A

25°C 120 120 mVVOL voltage VIC = 2.5 V, IOL = 500 µAFull range 500 500

mV

Large-signalV = 2.5 V, RL = 2 kΩ‡

25°C 3 5 3 5

AVD

Large-signaldifferential voltage

VIC = 2.5 V,VO = 1 V to 4 V

RL = 2 kΩ‡Full range 1 1 V/mVAVD differential voltage

amplificationVO = 1 V to 4 V

RL = 1 MΩ‡ 25°C 800 800

V/mV

ridDifferential inputresistance

25°C 1012 1012 Ω

ricCommon-mode input resistance

25°C 1012 1012 Ω

cicCommon-mode input capacitance

f = 10 kHz 25°C 6 6 pF

zoClosed-loopoutput impedance

f = 10 kHz, AV = 10 25°C 70 70 Ω

CMRRCommon-mode VIC = 0 to 2.7 V, VO = 1.5 V, 25°C 70 85 70 85

dBCMRRCommon-moderejection ratio

VIC = 0 to 2.7 V,RS = 50 Ω

VO = 1.5 V,Full range 65 65

dB

kSVR

Supply voltage rejection ratio

VDD = 4.4 V to 8 V, 25°C 80 95 80 95dBkSVR rejection ratio

(∆VDD /∆VIO)

VDD = 4.4 V to 8 V,VIC = VDD/2, No load Full range 80 80

dB

IDD Supply current VO = 2.5 V, No load25°C 110 150 110 150

µAIDD Supply current VO = 2.5 V, No loadFull range 200 200

µA

† Full range for the TLV2221C is 0°C to 70°C. Full range for the TLV2221I is − 40°C to 85°C.‡ Referenced to 2.5 VNOTE 5: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated

to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.


8 WWW.TI.COM

operating characteristics at specified free-air temperature, V DD = 5 V



UNIT

Slew rate at unity VO = 1.5 V to 3.5 V, RL = 2 kΩ‡,25°C 0.1 0.18 0.1 0.18

SRSlew rate at unitygain

VO = 1.5 V to 3.5 V,CL = 100 pF‡

RL = 2 kΩ‡,Full

range0.05 0.05

V/µs

VnEquivalent input f = 10 Hz 25°C 90 90

nV/√HzVnEquivalent inputnoise voltage f = 1 kHz 25°C 19 19

nV/√Hz

VN(PP)

Peak-to-peakequivalent input

f = 0.1 Hz to 1 Hz 25°C 800 800nVVN(PP) equivalent input

noise voltage f = 0.1 Hz to 10 Hz 25°C 960 960nV

InEquivalent inputnoise current

25°C 0.6 0.6 fA /√Hz

VO = 1.5 V to 3.5 V,f = 20 kHz,

AV = 125°C

2.45% 2.45%

THD+NTotal harmonic

Of = 20 kHz,RL = 2 kΩ‡ AV = 10

25°C5.54% 5.54%

THD+NTotal harmonic distortion plus noise VO = 1.5 V to 3.5 V,

f = 20 kHz,AV = 1

25°C0.142% 0.142%O

f = 20 kHz,RL = 2 kΩ§ AV = 10

25°C0.257% 0.257%

Gain-bandwidthproduct

f = 1 kHz, CL = 100 pF‡

RL = 2 kΩ‡, 25°C 510 510 kHz

BOMMaximum output-swing bandwidth

VO(PP) = 1 V, RL = 2 kΩ‡,

AV = 1,CL = 100 pF‡ 25°C 40 40 kHz

ts Settling time

AV = −1,Step = 1.5 V to 3.5 V,

‡

To 0.1% 25°C 6.8 6.8

sts Settling timeStep = 1.5 V to 3.5 V,RL = 2 kΩ‡,CL = 100 pF‡ To 0.01% 25°C 9.2 9.2

µs

φmPhase margin atunity gain RL = 2 kΩ‡, CL = 100 pF‡

25°C 52° 52°

Gain margin

RL = 2 kΩ‡, CL = 100 pF‡

25°C 12 12 dB† Full range is −40°C to 85°C.‡ Referenced to 2.5 V§ Referenced to 0 V


9WWW.TI.COM

electrical characteristics at V DD = 3 V, TA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONSTLV2221Y

UNITPARAMETER TEST CONDITIONSMIN TYP MAX

UNIT

VIO Input offset voltageVDD± = ±1.5 V, VIC = 0, VO = 0,

620 µV

IIO Input offset currentVDD± = ±1.5 V,RS = 50 Ω

VIC = 0, VO = 0,0.5 pA

IIB Input bias currentRS = 50 Ω

1 pA

−0.3VICR Common-mode input voltage range | VIO| ≤5 mV, RS = 50 Ω

−0.3to VVICR Common-mode input voltage range | VIO| ≤5 mV, RS = 50 Ω to

2.2V

VOH High-level output voltage IOH = −100 µA 2.97 V

VOL Low-level output voltageVIC = 1.5 V, IOL = 50 µA 15

mVVOL Low-level output voltageVIC = 1.5 V, IOL = 500 µA 150

mV

AVDLarge-signal differential

VO = 1 V to 2 VRL = 2 kΩ† 3

V/mVAVDLarge-signal differentialvoltage amplification VO = 1 V to 2 V

RL = 1 MΩ† 250V/mV

rid Differential input resistance 1012 Ω

ric Common-mode input resistance 1012 Ω

cic Common-mode input capacitance f = 10 kHz 6 pF

zo Closed-loop output impedance f = 10 kHz, AV = 10 90 Ω

CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, VO = 0, RS = 50 Ω 82 dB

kSVR Supply voltage rejection ratio (∆VDD/∆VIO) VDD = 2.7 V to 8 V, VIC = 0, No load 95 dB

IDD Supply current VO = 0, No load 100 µA

† Referenced to 1.5 V

electrical characteristics at V DD = 5 V, TA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONSTLV2221Y

UNITPARAMETER TEST CONDITIONSMIN TYP MAX

UNIT

VIO Input offset voltageVDD± = ±1.5 V, VIC = 0, VO = 0,

610 µV

IIO Input offset currentVDD± = ±1.5 V,RS = 50 Ω

VIC = 0, VO = 0,0.5 pA

IIB Input bias currentRS = 50 Ω

1 pA

−0.3VICR Common-mode input voltage range | VIO| ≤5 mV, RS = 50 Ω

−0.3to VVICR Common-mode input voltage range | VIO| ≤5 mV, RS = 50 Ω to

4.2V

VOH High-level output voltage IOH = −500 µA 4.88 V

VOL Low-level output voltageVIC = 2.5 V, IOL = 50 µA 12

mVVOL Low-level output voltageVIC = 2.5 V, IOL = 500 µA 120

mV

AVDLarge-signal differential

VO = 1 V to 4 VRL = 2 kΩ† 5

V/mVAVDLarge-signal differentialvoltage amplification VO = 1 V to 4 V

RL = 1 MΩ† 800V/mV

rid Differential input resistance 1012 Ω

ric Common-mode input resistance 1012 Ω

cic Common-mode input capacitance f = 10 kHz 6 pF

zo Closed-loop output impedance f = 10 kHz, AV = 10 70 Ω

CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, VO = 0, RS = 50 Ω 85 dB

kSVR Supply voltage rejection ratio (∆VDD/∆VIO) VDD = 2.7 V to 8 V, VIC = 0, No load 95 dB

IDD Supply current VO = 0, No load 110 µA

† Referenced to 2.5 V


10 WWW.TI.COM

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

VIO Input offset voltageDistributionvs Common-mode input voltage

2, 34, 5

αVIO Input offset voltage temperature coefficient Distribution 6, 7

IIB/IIO Input bias and input offset currents vs Free-air temperature 8

VI Input voltagevs Supply voltagevs Free-air temperature

910

VOH High-level output voltage vs High-level output current 11, 14

VOL Low-level output voltage vs Low-level output current 12, 13, 15

VO(PP) Maximum peak-to-peak output voltage vs Frequency 16

IOS Short-circuit output currentvs Supply voltagevs Free-air temperature

1718

VO Output voltage vs Differential input voltage 19, 20

AVD Differential voltage amplification vs Load resistance 21

AVD Large signal differential voltage amplificationvs Frequencyvs Free-air temperature

22, 2324, 25

zo Output impedance vs Frequency 26, 27

CMRR Common-mode rejection ratiovs Frequencyvs Free-air temperature

2829

kSVR Supply-voltage rejection ratiovs Frequencyvs Free-air temperature

30, 3132

IDD Supply current vs Supply voltage 33

SR Slew ratevs Load capacitancevs Free-air temperature

3435

VO Inverting large-signal pulse response vs Time 36, 37

VO Voltage-follower large-signal pulse response vs Time 38, 39

VO Inverting small-signal pulse response vs Time 40, 41

VO Voltage-follower small-signal pulse response vs Time 42, 43

Vn Equivalent input noise voltage vs Frequency 44, 45

Input noise voltage (referred to input) Over a 10-second period 46

THD + N Total harmonic distortion plus noise vs Frequency 47

Gain-bandwidth productvs Free-air temperaturevs Supply voltage

4849

φm Phase marginvs Frequencyvs Load capacitance

22, 2352, 53

Gain margin vs Load capacitance 50, 51

B1 Unity-gain bandwidth vs Load capacitance 54, 55


11WWW.TI.COM


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mpl

ifier

s −

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DISTRIBUTION OF TLV2211INPUT OFFSET VOLTAGE

VIO − Input Offset Voltage − mV

15

10

5

0

20

25

−1.5 −1 −0.5 0 0.5 1 1.5

385 Amplifiers From 1 Wafer LotVDD = ±1.5 VTA = 25°C

Figure 3

Pre

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age

of A

mpl

ifier

s −

%

DISTRIBUTION OF TLV2211INPUT OFFSET VOLTAGE

VIO − Input Offset Voltage − mV

15

10

5

0

20

25

−1.5 −1 −0.5 0 0.5 1 1.5

VDD = ±2.5 VTA = 25°C

385 Amplifiers From 1 Wafer Lot

Figure 4

− In

put O

ffset

Vol

tage

− m

V

INPUT OFFSET VOLTAGE†

vsCOMMON-MODE INPUT VOLTAGE

ÁÁÁÁÁÁ

VIO

VIC − Common-Mode Input Voltage − V

1

0.8

0.6

0.4

0.2

0

−0.2

−0.4

−0.6

−0.8

−1−1 0 1 2

VDD = 3 VRS = 50 ΩTA = 25°C

3

Figure 5

− In

put O

ffset

Vol

tage

− m

V

INPUT OFFSET VOLTAGE†

vsCOMMON-MODE INPUT VOLTAGE

ÁÁÁÁV

IO

VIC − Common-Mode Input Voltage − V

1

0.8

0.6

0.4

0.2

0

−0.2

−0.4

−0.6

−0.8

−1−1 0 1 2

VDD = 5 VRS = 50 ΩTA = 25°C

3 4 5

† For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.


12 WWW.TI.COM


Figure 6

DISTRIBUTION OF TLV2221 INPUT OFFSETVOLTAGE TEMPERATURE COEFFICIENT †

Per

cent

age

of A

mpl

ifier

s −

%

αVIO − Input Offset VoltageTemperature Coefficient − µV/°C

15

10

5

0

20

25

−4 −3 −2 0 1 2 3

VDD = ±1.5 VP PackageTA = 25°C to 125°C

−1 4


Figure 7

DISTRIBUTION OF TLV2221 INPUT OFFSETVOLTAGE TEMPERATURE COEFFICIENT †

Per

cent

age

of A

mpl

ifier

s −

%

αVIO − Input Offset VoltageTemperature Coefficient − µV/°C

15

10

5

0

20

25

−4 −3 −2 0 1 2 3

VDD = ±2.5 VP PackageTA = 25°C to 125°C

−1 4


Figure 8

IIB a

nd II

O −

Inpu

t Bia

s an

d In

put O

ffset

Cur

rent

s −

pA

INPUT BIAS AND INPUT OFFSET CURRENTSvs

FREE-AIR TEMPERATURE

I IB

I IO

TA − Free-Air Temperature − °C

50

40

20

10

0

90

30

25 45 65 85

70

60

80

100

105 125

VDD± = ±2.5 VVIC = 0 VO = 0RS = 50 Ω

IIB

IIO

Figure 9

0

4

1 1.5 2 2.5

− In

put V

olta

ge −

V

2

1

3

INPUT VOLTAGEvs

SUPPLY VOLTAGE5

3 3.5 4

−1

−2

−3

−4

−5

RS = 50 ΩTA = 25°C

|VIO| ≤5 mV

ÁÁÁÁ

VI

|VDD±| − Supply Voltage − V

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.


13WWW.TI.COM


Figure 10

− In

put V

olta

ge −

V

INPUT VOLTAGE†‡

vsFREE-AIR TEMPERATURE

ÁÁVI


2

1

0

3

4

5

−1−55 −35 −15 5 25 45 65 85

|VIO| ≤5 mV

VDD = 5 V

105 125

Figure 11

− H

igh-

Leve

l Out

put V

olta

ge −

V

HIGH-LEVEL OUTPUT VOLTAGE †‡

vsHIGH-LEVEL OUTPUT CURRENT

ÁÁÁÁÁÁ

V OH

|IOH| − High-Level Output Current − mA

1.5

1

0.5

00 0.5 1 1.5 2 2.5 3

2

2.5

3

3.5 4 4.5 5

VDD = 3 V

TA = −40°C

TA = 25°C

TA = 85°C

TA = 125°C

Figure 12

0.6

0.4

0.2

00 1 2 3

− Lo

w-L

evel

Out

put V

olta

ge −

V

0.8

1

LOW-LEVEL OUTPUT VOLTAGE ‡

vsLOW-LEVEL OUTPUT CURRENT

1.2

4 5

ÁÁÁÁ

V OL

IOL − Low-Level Output Current − mA

VDD = 3 VTA = 25°C

VIC = 0

VIC = 0.75 V

VIC = 1.5 V

Figure 13

− Lo

w-L

evel

Out

put V

olta

ge −

V

LOW-LEVEL OUTPUT VOLTAGE †‡


ÁÁÁÁÁÁ

V OL


0.4

0.2

1.2

00 1 2 3

0.8

0.6

1

1.4

4 5

TA = 85°C

TA = − 40°C

TA = 25°C

TA = 125°C

VDD = 3 VVIC = 1.5 V

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.


14 WWW.TI.COM


Figure 14

− H

igh-

Leve

l Out

put V

olta

ge −

V

HIGH-LEVEL OUTPUT VOLTAGE †‡

vsHIGH-LEVEL OUTPUT CURRENT

ÁÁÁÁ

V OH

|IOH| − High-Level Output Current − mA

2

1

00 1 2 3 4

3

4

5

5 6 7 8


TA = −40°C

TA = 25°C

TA = 85°C

TA = 125°C

Figure 15

− Lo

w-L

evel

Out

put V

olta

ge −

V

LOW-LEVEL OUTPUT VOLTAGE †‡


ÁÁÁÁV

OL


0.6

0.4

0.2

00 1 2 3

1

1.2

1.4

4 5 6

0.8


TA = −40°C

TA = 85°C

TA = 25°C

TA = 125°C

Figure 16

− M

axim

um P

eak-

to-P

eak

Out

put V

olta

ge −

V

f − Frequency − Hz

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE ‡

vsFREQUENCY

ÁÁÁÁÁÁ

VO

(PP

)

4

2

1

5

3

0102 103 104 105

RL = 2 kΩTA = 25°C

VDD = 5 V

VDD = 3 V

Figure 17

− S

hort

-Circ

uit O

utpu

t Cur

rent

− m

A

SHORT-CIRCUIT OUTPUT CURRENTvs

SUPPLY VOLTAGE

I OS

VDD − Supply Voltage − V2

−8

−4

0

4

8

12

16

20

3 4 5 6 7 8

VO = VDD/2TA = 25°CVIC = VDD/2

VID = −100 mV

VID = 100 mV



15WWW.TI.COM


Figure 18

− S

hort

-Circ

uit O

utpu

t Cur

rent

− m

A

SHORT-CIRCUIT OUTPUT CURRENT†‡


I OS


20

16

12

8

4

0

−4

−8−75 −50 −25 0 25 50 75 100 125

VDD = 5 VVIC = 2.5 VVO = 2.5 V

VID = −100 mV

VID = 100 mV

Figure 19

543210−1−2−3−4−50

0.5

1

1.5

2

2.5

3VDD = 3 VRI = 2 kΩVIC = 1.5 VTA = 25°C

OUTPUT VOLTAGE‡

vsDIFFERENTIAL INPUT VOLTAGE

VID − Differential Input Voltage − V

− O

utpu

t Vol

tage

− V

VO

Figure 20

543210−1−2−3−4−50

1

2

3

4

5

VDD = 5 VVIC = 2.5 VRL = 2 kΩTA = 25°C

OUTPUT VOLTAGE‡

vsDIFFERENTIAL INPUT VOLTAGE

VID − Differential Input Voltage − V

− O

utpu

t Vol

tage

− V

VO

Figure 21

DIFFERENTIAL VOLTAGE AMPLIFICATION ‡

vsLOAD RESISTANCE

RL − Load Resistance − k Ω

− D

iffer

entia

l Vol

tage

Am

plifi

catio

n −

V/m

V

ÁÁÁÁÁÁ

AV

D

1 101 102 103

102

101

1

103

VDD = 5 V

VDD = 3 V

VO(PP) = 2 VTA = 25°C



16 WWW.TI.COM


om −

Pha

se M

argi

n φ m


LARGE-SIGNAL DIFFERENTIAL VOLTAGE †

AMPLIFICATION AND PHASE MARGINvs

FREQUENCYA

VD

− L

arge

-Sig

nal D

iffer

entia

l

ÁÁÁÁ

AV

D Vol

tage

Am

plifi

catio

n −

dB

104

Gain

Phase Margin

20

80

60

40

0

−20

−40

180°

135°

90°

45°

0°

−45°

−90°105 106 107

VDD = 5 VRL = 2 kΩCL= 100 pFTA = 25°C

Figure 22

om −

Pha

se M

argi

n φ m


LARGE-SIGNAL DIFFERENTIAL VOLTAGEAMPLIFICATION AND PHASE MARGIN †

vsFREQUENCY

AV

D −

Lar

ge-S

igna

l Diff

eren

tial

ÁÁÁÁ

AV

D Vol

tage

Am

plifi

catio

n −

dB

Gain

Phase Margin

VDD = 3 VRL = 2 kΩCL= 100 pFTA = 25°C

104

20

80

60

40

0

−20

−40

180°

135°

90°

45°

0°

−45°

−90°105 106 107

Figure 23



17WWW.TI.COM


Figure 24

LARGE-SIGNAL DIFFERENTIALVOLTAGE AMPLIFICATION †‡



− La

rge-

Sig

nal D

iffer

entia

l Vol

tage

A

VD

Am

plifi

catio

n −

V/m

V

−50 −25 0 25 50 75 100

RL = 2 kΩ

RL = 1 MΩ

103

102

1

VDD = 3 VVIC = 1.5 VVO = 0.5 V to 2.5 V

−75 125

101

Figure 25

LARGE-SIGNAL DIFFERENTIALVOLTAGE AMPLIFICATION †‡



− La

rge-

Sig

nal D

iffer

entia

l Vol

tage

A

VD

Am

plifi

catio

n −

V/m

V

VDD = 5 VVIC = 2.5 VVO = 1 V to 4 V

RL = 2 kΩ

RL = 1 MΩ

−50 −25 0 25 50 75 100 125

104

103

102

1−75

101

Figure 26

− O

utpu

t Im

peda

nce

−

f− Frequency − Hz

OUTPUT IMPEDANCE‡

vsFREQUENCY

Ωz

o

1101 103 104 105102

VDD = 3 VTA = 25°C

AV = 100

AV = 10

AV = 1

10

100

1000

Figure 27

− O

utpu

t Im

peda

nce

−

f− Frequency − Hz

OUTPUT IMPEDANCE‡

vsFREQUENCY

Ωz

o

VDD = 5 VTA = 25°C

AV = 100

AV = 10

AV = 1

10

1

0.1

1000

100

101 103 104 105102



18 WWW.TI.COM


Figure 28

CM

RR

− C

omm

on-M

ode

Rej

ectio

n R

atio

− d

B


COMMON-MODE REJECTION RATIO†

vsFREQUENCY

80

40

20

0

100

60

101 102 103 104 105 106


TA = 25°C


Figure 29

CM

MR

− C

omm

on-M

ode

Rej

ectio

n R

atio

− d

B

COMMON-MODE REJECTION RATIO†‡



88

86

84

82

80

78−75 −50 −25 0 25 50 75 100 125

VDD = 5 V

VDD = 3 V

Figure 30

− S

uppl

y-Vo

ltage

Rej

ectio

n R

atio

− d

B


SUPPLY-VOLTAGE REJECTION RATIO †

vsFREQUENCY

ÁÁÁÁÁÁ

kS

VR

60

40

20

100

80

0

−20101 102 103 104 105 106

kSVR+

kSVR−

VDD = 3 VTA = 25°C

Figure 31

− S

uppl

y-Vo

ltage

Rej

ectio

n R

atio

− d

B



vsFREQUENCY

ÁÁÁÁÁÁ

kS

VR

VDD = 5 VTA = 25°C

kSVR−

kSVR+

100

80

60

40

20

0

−20101 102 103 104 105 106

‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.



19WWW.TI.COM


Figure 32

− S

uppl

y-Vo

ltage

Rej

ectio

n R

atio

− d

B



ÁÁÁÁÁÁ

kS

VR

TA − Free-Air Temperature − °C−50 −25 0 25 50 75 100 125−75

VDD = 2.7 V to 8 VVIC = VO = VDD /2

100

98

96

94

92

90

Figure 33

− S

uppl

y C

urre

nt −

A

µ

ÁÁÁÁÁÁ

I DD

VDD − Supply Voltage − V

SUPPLY CURRENT †

vsSUPPLY VOLTAGE

TA = 25°CTA = 85°C

TA = −40°C

VO = 0 No Load

200

175

150

125

100

75

50

25

00 2 4 6 8 10

Figure 34

SR

− S

lew

Rat

e −

SLEW RATE‡

vsLOAD CAPACITANCE

CL − Load Capacitance − pF

sµ

V/

0.5

101

0.4

0.3

0.2

0.1

0102 103 104 105

VDD = 5 VAV = −1TA = 25°C

SR−

SR+

Figure 35

SR

− S

lew

Rat

e −

SLEW RATE†‡


sµ

V/


0.2

0.1

0

0.3

0.4

0.5

−50 −25 0 25 50 75 100

VDD = 5 VRL = 2 kΩCL = 100 pFA V = 1

−75 125

SR−

SR+



20 WWW.TI.COM


Figure 36

− O

utpu

t Vol

tage

− V

INVERTING LARGE-SIGNAL PULSERESPONSE†

VO

t − Time − µs

A V = −1TA = 25°C

VDD = 3 VRL = 2 kΩCL = 100 pF

1.5

1

0.5

0

2

2.5

3

0 5 10 15 20 25 30 35 40 45 50

Figure 37

INVERTING LARGE-SIGNAL PULSERESPONSE†

t − Time − µs

− O

utpu

t Vol

tage

− V

VO

2

1

00 5 10 15 20 25 30

3

4

5

35 40 45 50

VDD = 5 VRL = 2 kΩCL = 100 pFAV = −1TA = 25°C

Figure 38

VOLTAGE-FOLLOWER LARGE-SIGNALPULSE RESPONSE†

− O

utpu

t Vol

tage

− V

VO

t − Time − µs

1

00 5 10 15 20 25 30

2

3

35 40 45 50

A V = 1TA = 25°C

VDD = 5 VRL = 2 kΩCL = 100 pF

4

5

Figure 39

VOLTAGE-FOLLOWER LARGE-SIGNALPULSE RESPONSE†

− O

utpu

t Vol

tage

− V

VO

t − Time − µs

2

1

00 5 10 15 20 25 30

3

4

5

35 40 45 50

VDD = 5 VCL = 100 pFAV = 1TA = 25°C RL = 100 kΩ

Tied to 2.5 V

RL = 2 kΩTied to 2.5 V

RL = 2 kΩTied to 0 V



21WWW.TI.COM


Figure 40

INVERTING SMALL-SIGNALPULSE RESPONSE†

− O

utpu

t Vol

tage

− V

VO

t − Time − µs

0.82

0

0.8

0.78

0.76

0.74

0.72

0.70.5 1 1.5 2 2.5 3 3.5 4 4.5 5


Figure 41

VO

− O

utpu

t Vol

tage

− V

INVERTING SMALL-SIGNALPULSE RESPONSE†

VO

t − Time − µs


2.58

0

2.56

2.54

2.52

2.5

2.48

2.46

2.440.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Figure 42

VOLTAGE-FOLLOWER SMALL-SIGNALPULSE RESPONSE†

VO

− O

utpu

t Vol

tage

− V

VO

t − Time − µs

0.82

0

0.8

0.78

0.76

0.74

0.72

0.71 2 3 4 5 6 7 8 9 10

VDD = 3 VRL = 2 kΩCL = 100 pFAV = 1TA = 25°C

Figure 43

VOLTAGE-FOLLOWER SMALL-SIGNALPULSE RESPONSE†

VO

− O

utpu

t Vol

tage

− V

VO

t − Time − µs

2.58

0

2.56

2.54

2.52

2.5

2.48

2.46

2.440.5 1 1.5 2 2.5 3 3.5 4 4.5 5

VDD = 5 VRL = 2 kΩCL = 100 pFAV = 1TA = 25°C



22 WWW.TI.COM


Figure 44

− E

quiv

alen

t Inp

ut N

oise

Vol

tage

−


EQUIVALENT INPUT NOISE VOLTAGE †

vsFREQUENCY

Vn

nV/

Hz

101 102 103 104

120

VDD = 3 VRS = 20 ΩTA = 25°C100

80

60

40

20

0

Figure 45

− E

quiv

alen

t Inp

ut N

oise

Vol

tage

−


EQUIVALENT INPUT NOISE VOLTAGE †

vsFREQUENCY

Vn

nV/

Hz VDD = 5 V

RS = 20 ΩTA = 25°C

101 102 103 104

120

100

80

60

40

20

0

Figure 46

Inpu

t Noi

se V

olta

ge −

nV

t − Time − s

INPUT NOISE VOLTAGE OVERA 10-SECOND PERIOD†

0 2 4 6

750

1000

8 10

500

−250

−500

−750

−1000

250

VDD = 5 Vf = 0.1 Hz to 10 HzTA = 25°C

0

Figure 47

TH

D +

N −

Tot

al H

arm

onic

Dis

tort

ion

Plu

s N

oise

− %


TOTAL HARMONIC DISTORTION PLUS NOISE †

vsFREQUENCY

101 102 103 104 105

0.1

10

0.01

1

AV = 1

AV = 10

AV = 1

AV = 10

VDD = 5 VTA = 25°C

RL = 2 kΩ Tied to 2.5 VRL = 2 kΩ Tied to 0 V



23WWW.TI.COM


Figure 48

Gai

n-B

andw

idth

Pro

duct

− k

Hz

GAIN-BANDWIDTH PRODUCT †‡



500

400

300

200

600

700

800

−50 −25 0 25 50 10075

VDD = 5 Vf = 10 kHzRL = 2 kHzCL = 100 pF

125−75

Figure 49

Gai

n-B

andw

idth

Pro

duct

− k

Hz

GAIN-BANDWIDTH PRODUCTvs

SUPPLY VOLTAGE

VDD − Supply Voltage − V

500

450

425

400

550

575

600

525

475

0 2 3 5 7 81 4 6

RL = 2kCL = 100 pFTA = 25°C

Figure 50

Gai

n M

argi

n −

dB

GAIN MARGINvs

LOAD CAPACITANCE


Rnull = 500 Ω

Rnull = 200 Ω

Rnull = 0

20

10

5

0

15

101 102 103 105104

Rnull = 1 kΩ

TA = 25°CRL = ∞

Figure 51

CL − Load Capacitance − pF101 102 103 105104

Rnull = 1 kΩ

Rnull = 500 Ω

Rnull = 100 Ω

Rnull = 0

TA = 25°CRL = 2 kΩ

20

15

10

5

0

Gai

n M

argi

n −

dB

GAIN MARGINvs

LOAD CAPACITANCE



24 WWW.TI.COM


Figure 52

om −

Pha

se M

argi

n

PHASE MARGINvs

LOAD CAPACITANCE


mφ

101 102 103 105

75°

60°

45°

30°

15°

0°

Rnull = 200 Ω

Rnull = 500 Ω

Rnull = 0

Rnull = 1 kΩ

104

TA = 25°CRL = ∞

Figure 53

CL − Load Capacitance − pF101 102 103 105

75°

60°

45°

30°

15°

0°104

Rnull = 1 kΩ

Rnull = 500 Ω

Rnull = 100 Ω

Rnull = 0

TA = 25°CRL = 2 kΩ

om −

Pha

se M

argi

n

PHASE MARGINvs

LOAD CAPACITANCE

mφ

Figure 54

− U

nity

-Gai

n B

andw

idth

− k

Hz

UNITY-GAIN BANDWIDTHvs

LOAD CAPACITANCE


ÁÁÁÁ

B1

600

101 102 103 104 105

500

400

300

200

100

0

TA = 25°CRL = ∞

Figure 55CL − Load Capacitance − pF

101 102 103 105104

TA = 25°CRL = 2 kΩ

600

500

400

300

200

100

0

− U

nity

-Gai

n B

andw

idth

− k

Hz

UNITY-GAIN BANDWIDTHvs

LOAD CAPACITANCE

ÁÁÁÁÁÁ

B1


25WWW.TI.COM

APPLICATION INFORMATION

driving large capacitive loads

The TLV2221 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 50through Figure 55 illustrate its ability to drive loads greater than 100 pF while maintaining good gain and phasemargins (Rnull = 0).

A small series resistor (Rnull) at the output of the device (Figure 56) improves the gain and phase margins whendriving large capacitive loads. Figure 50 through Figure 53 show the effects of adding series resistances of100 Ω , 200 Ω , 500 Ω , and 1 kΩ . The addition of this series resistor has two effects: the first effect is that it addsa zero to the transfer function and the second effect is that it reduces the frequency of the pole associated withthe output load in the transfer function.

The zero introduced to the transfer function is equal to the series resistance times the load capacitance. Tocalculate the approximate improvement in phase margin, equation 1 can be used.

∆φm1 tan–1 2 × π × UGBW × Rnull × CL

∆φm1 improvement in phase margin

UGBW unity-gain bandwidth frequencyRnull output series resistance

CL load capacitance

(1)

where :

The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (Figure 54 and Figure55). To use equation 1, UGBW must be approximated from Figure 54 and Figure 55.

VDD−/GND

VDD+

Rnull

CL

VI

+

−

RL

Figure 56. Series-Resistance Circuit

The TLV2221 is designed to provide better sinking and sourcing output currents than earlier CMOS rail-to-railoutput devices. This device is specified to sink 500 µA and source 1 mA at VDD = 5 V at a maximum quiescentIDD of 200 µA. This provides a greater than 80% power efficiency.

When driving heavy dc loads, such as 2 kΩ, the positive edge under slewing conditions can experience somedistortion. This condition can be seen in Figure 38. This condition is affected by three factors:

Where the load is referenced. When the load is referenced to either rail, this condition does not occur. Thedistortion occurs only when the output signal swings through the point where the load is referenced.Figure 39 illustrates two 2-kΩ load conditions. The first load condition shows the distortion seen for a 2-kΩload tied to 2.5 V. The third load condition in Figure 39 shows no distortion for a 2-kΩ load tied to 0 V.

Load resistance. As the load resistance increases, the distortion seen on the output decreases. Figure 39illustrates the difference seen on the output for a 2-kΩ load and a 100-kΩ load with both tied to 2.5 V.

Input signal edge rate. Faster input edge rates for a step input result in more distortion than with slower inputedge rates.


26 WWW.TI.COM

APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using Microsim Parts, the model generation software usedwith Microsim PSpice. The Boyle macromodel (see Note 6) and subcircuit in Figure 57 are generated usingthe TLV2221 typical electrical and operating characteristics at TA = 25°C. Using this information, outputsimulations of the following key parameters can be generated to a tolerance of 20% (in most cases):

Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification

Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit

NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journalof Solid-State Circuits, SC-9, 353 (1974).

OUT

+

−

+

−

+

−

+

−

+−

+

−

+

− +

−

+−

.SUBCKT TLV2221 1 2 3 4 5C1 11 12 12.53E−12C2 6 7 50.00E−12DC 5 53 DXDE 54 5 DXDLP 90 91 DXDLN 92 90 DXDP 4 3 DXEGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5FB 7 99 POLY (5) VB VC VE VLP+ VLN 0 893.6E3 −90E3 90E3 90E3 −90E3GA 6 0 11 12 94.25E−6GCM 0 6 10 99 9.300E−9ISS 3 10 DC 9.000E−6HLIM 90 0 VLIM 1KJ1 11 2 10 JXJ2 12 1 10 JXR2 6 9 100.0E3

RD1 60 11 10.61E3RD2 60 12 10.61E3R01 8 5 35R02 7 99 35RP 3 4 49.50E3RSS 10 99 22.22E6VAD 60 4 −.5VB 9 0 DC 0VC 3 53 DC .666VE 54 4 DC .666VLIM 7 8 DC 0VLP 91 0 DC 3.4VLN 0 92 DC 11.4.MODEL DX D (IS=800.0E−18).MODEL JX PJF (IS=500.0E−15 BETA=1.527E−3+ VTO=−.001).ENDS

VDD+

RP

IN −2

IN+1

VDD−

VAD

RD1

11

J1 J2

10

RSS ISS

3

12

RD2

60

VE

54DE

DP

VC

DC

4

C1

53

R2

6

9

EGND

VB

FB

C2

GCM GA VLIM

8

5

RO1

RO2

HLIM

90

DLP

91

DLN

92

VLNVLP

99

7

Figure 57. Boyle Macromodel and Subcircuit

PSpice and Parts are trademark of MicroSim Corporation.

"!#!)% %#&)$! #!)% !" !$+" #!)% '"! (. " $). !" " $). " !$ -""$ (. % &)). "'"%$/ ))! $+ %' $! !'"$/ +" $"%$ % ! $+%# !& $!" '"!& $ $! -+ + $+ #!) ")$%*

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Top-Side Markings(4)

Samples

TLV2221CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM 0 to 70 VADC

TLV2221CDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)


TLV2221CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS& no Sb/Br)


TLV2221CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS& no Sb/Br)


TLV2221IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 VADI

TLV2221IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 VADI

TLV2221IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM VADI

TLV2221IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM VADI

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

http://www.ti.com/product/TLV2221?CMP=conv-poasamples#samplebuy








http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 2

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1(mm)

W(mm)

Pin1Quadrant

TLV2221CDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3

TLV2221CDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3

TLV2221IDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3

TLV2221IDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Mar-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV2221CDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0

TLV2221CDBVT SOT-23 DBV 5 250 182.0 182.0 20.0

TLV2221IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0

TLV2221IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Mar-2008

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to itssemiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyersshould obtain the latest relevant information before placing orders and should verify that such information is current and complete.TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integratedcircuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products andservices.Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and isaccompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduceddocumentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statementsdifferent from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for theassociated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designersremain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers havefull and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI productsused in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, withrespect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerousconsequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm andtake appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer willthoroughly test such applications and the functionality of such TI products as used in such applications.TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended toassist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in anyway, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resourcesolely for this purpose and subject to the terms of this Notice.TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TIproducts, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specificallydescribed in the published documentation for a particular TI Resource.Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications thatinclude the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISETO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTYRIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationregarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty orendorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES ORREPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TOACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OFMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUALPROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OFPRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES INCONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEENADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, suchproducts are intended to help enable customers to design and create their own applications that meet applicable functional safety standardsand requirements. Using products in an application does not by itself establish any safety features in the application. Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, allmedical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applicationsand that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatoryrequirements in connection with such selection.Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2018, Texas Instruments Incorporated

http://www.ti.com/sc/docs/stdterms.htm

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