1

Performance You Can SeePerformance You Can See

邏輯分析儀概念與基本原理邏輯分析儀概念與基本原理

2

討論主題

4邏輯分析儀( LA )概念與基本原理

4支援套件 (support package)4新一代的 LA TLA 7012 amp TLA 70164Q amp A

3

邏輯分析儀概念與基本原理

4

Basic concept of Logic analyzer

4什麼是LA為何需要LA4LA的主要功能及指標4LA的架構

-探棒 (Probe)-同步 (Synchronous) amp 非同步 (Asynchronous)-觸發狀態機 (Trigger state machine)-擷取記憶體 (Acquisition memory)

5

Driving InnovationCreates Digital Debugging Challenges

Todayrsquos speeds are causing more signal integrity challenges than ever

4 Faster synchronous bus architectures0Faster clock amp data rates0Quicker rise amp fall times0Shorter setup amp hold times

4 Electrical amp physical challenges0Smaller logic swings0Differential signals0More signals to measure0Signal impedance amp termination issues

Digital Designers need to be able to correlate the Digital Designers need to be able to correlate the analog characteristics of their digital signalsanalog characteristics of their digital signals

6

偵錯階段

電錶

Emulator軟體偵錯工具偵錯工具

即時示波器

邏輯分析儀

初始電氣特性檢查

硬體功能檢查

軟體整合及偵錯

系統最佳化

參數及極限分析

硬體偵錯

硬體及軟體偵錯

硬體 amp 軟體偵錯階段及工具

7

什麼是LA (Logic Analyzer)

時域儀器(電壓 vs 時間)頻域儀器(功率 vs 頻率)調制域儀器(頻率 vs 時間)邏輯域儀器(邏輯 vs 時間)

示波器

頻譜或FFT分析儀調制域(向量)分析儀邏輯分析儀

8

為何需要LA

4因為LA能夠解決以下問題 0跟蹤微處理機的即時代碼數據

0同時觀察多路邏輯訊息

0擷取間歇性系統故障0系統崩潰的原因跟蹤0嵌入式系統(Embedded system)的發展0

9

LA的主要功能

4擷取 (同步和非同步模式)0即時非侵入式測試工具 允許待測電路全速執行

4儲存 (一般 轉態 條件儲存模式)0所存的數據用作對糾纏不清的邏輯或代碼進行後續處理分析

4觸發(Trigger)和限定(Qualification)0挑戰您的智慧 節約您的時間 善待您老板的資金和投入

4顯示(狀態 波形 直方圖 高階代碼)0您需要有意義的信息顯示而不是一大堆的二進制碼

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

2

討論主題

4邏輯分析儀( LA )概念與基本原理

4支援套件 (support package)4新一代的 LA TLA 7012 amp TLA 70164Q amp A

3

邏輯分析儀概念與基本原理

4

Basic concept of Logic analyzer

4什麼是LA為何需要LA4LA的主要功能及指標4LA的架構

-探棒 (Probe)-同步 (Synchronous) amp 非同步 (Asynchronous)-觸發狀態機 (Trigger state machine)-擷取記憶體 (Acquisition memory)

5

Driving InnovationCreates Digital Debugging Challenges

Todayrsquos speeds are causing more signal integrity challenges than ever

4 Faster synchronous bus architectures0Faster clock amp data rates0Quicker rise amp fall times0Shorter setup amp hold times

4 Electrical amp physical challenges0Smaller logic swings0Differential signals0More signals to measure0Signal impedance amp termination issues

Digital Designers need to be able to correlate the Digital Designers need to be able to correlate the analog characteristics of their digital signalsanalog characteristics of their digital signals

6

偵錯階段

電錶

Emulator軟體偵錯工具偵錯工具

即時示波器

邏輯分析儀

初始電氣特性檢查

硬體功能檢查

軟體整合及偵錯

系統最佳化

參數及極限分析

硬體偵錯

硬體及軟體偵錯

硬體 amp 軟體偵錯階段及工具

7

什麼是LA (Logic Analyzer)

時域儀器(電壓 vs 時間)頻域儀器(功率 vs 頻率)調制域儀器(頻率 vs 時間)邏輯域儀器(邏輯 vs 時間)

示波器

頻譜或FFT分析儀調制域(向量)分析儀邏輯分析儀

8

為何需要LA

4因為LA能夠解決以下問題 0跟蹤微處理機的即時代碼數據

0同時觀察多路邏輯訊息

0擷取間歇性系統故障0系統崩潰的原因跟蹤0嵌入式系統(Embedded system)的發展0

9

LA的主要功能

4擷取 (同步和非同步模式)0即時非侵入式測試工具 允許待測電路全速執行

4儲存 (一般 轉態 條件儲存模式)0所存的數據用作對糾纏不清的邏輯或代碼進行後續處理分析

4觸發(Trigger)和限定(Qualification)0挑戰您的智慧 節約您的時間 善待您老板的資金和投入

4顯示(狀態 波形 直方圖 高階代碼)0您需要有意義的信息顯示而不是一大堆的二進制碼

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

3

邏輯分析儀概念與基本原理

4

Basic concept of Logic analyzer

4什麼是LA為何需要LA4LA的主要功能及指標4LA的架構

-探棒 (Probe)-同步 (Synchronous) amp 非同步 (Asynchronous)-觸發狀態機 (Trigger state machine)-擷取記憶體 (Acquisition memory)

5

Driving InnovationCreates Digital Debugging Challenges

Todayrsquos speeds are causing more signal integrity challenges than ever

4 Faster synchronous bus architectures0Faster clock amp data rates0Quicker rise amp fall times0Shorter setup amp hold times

4 Electrical amp physical challenges0Smaller logic swings0Differential signals0More signals to measure0Signal impedance amp termination issues

Digital Designers need to be able to correlate the Digital Designers need to be able to correlate the analog characteristics of their digital signalsanalog characteristics of their digital signals

6

偵錯階段

電錶

Emulator軟體偵錯工具偵錯工具

即時示波器

邏輯分析儀

初始電氣特性檢查

硬體功能檢查

軟體整合及偵錯

系統最佳化

參數及極限分析

硬體偵錯

硬體及軟體偵錯

硬體 amp 軟體偵錯階段及工具

7

什麼是LA (Logic Analyzer)

時域儀器(電壓 vs 時間)頻域儀器(功率 vs 頻率)調制域儀器(頻率 vs 時間)邏輯域儀器(邏輯 vs 時間)

示波器

頻譜或FFT分析儀調制域(向量)分析儀邏輯分析儀

8

為何需要LA

4因為LA能夠解決以下問題 0跟蹤微處理機的即時代碼數據

0同時觀察多路邏輯訊息

0擷取間歇性系統故障0系統崩潰的原因跟蹤0嵌入式系統(Embedded system)的發展0

9

LA的主要功能

4擷取 (同步和非同步模式)0即時非侵入式測試工具 允許待測電路全速執行

4儲存 (一般 轉態 條件儲存模式)0所存的數據用作對糾纏不清的邏輯或代碼進行後續處理分析

4觸發(Trigger)和限定(Qualification)0挑戰您的智慧 節約您的時間 善待您老板的資金和投入

4顯示(狀態 波形 直方圖 高階代碼)0您需要有意義的信息顯示而不是一大堆的二進制碼

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

4

Basic concept of Logic analyzer

4什麼是LA為何需要LA4LA的主要功能及指標4LA的架構

-探棒 (Probe)-同步 (Synchronous) amp 非同步 (Asynchronous)-觸發狀態機 (Trigger state machine)-擷取記憶體 (Acquisition memory)

5

Driving InnovationCreates Digital Debugging Challenges

Todayrsquos speeds are causing more signal integrity challenges than ever

4 Faster synchronous bus architectures0Faster clock amp data rates0Quicker rise amp fall times0Shorter setup amp hold times

4 Electrical amp physical challenges0Smaller logic swings0Differential signals0More signals to measure0Signal impedance amp termination issues

Digital Designers need to be able to correlate the Digital Designers need to be able to correlate the analog characteristics of their digital signalsanalog characteristics of their digital signals

6

偵錯階段

電錶

Emulator軟體偵錯工具偵錯工具

即時示波器

邏輯分析儀

初始電氣特性檢查

硬體功能檢查

軟體整合及偵錯

系統最佳化

參數及極限分析

硬體偵錯

硬體及軟體偵錯

硬體 amp 軟體偵錯階段及工具

7

什麼是LA (Logic Analyzer)

時域儀器(電壓 vs 時間)頻域儀器(功率 vs 頻率)調制域儀器(頻率 vs 時間)邏輯域儀器(邏輯 vs 時間)

示波器

頻譜或FFT分析儀調制域(向量)分析儀邏輯分析儀

8

為何需要LA

4因為LA能夠解決以下問題 0跟蹤微處理機的即時代碼數據

0同時觀察多路邏輯訊息

0擷取間歇性系統故障0系統崩潰的原因跟蹤0嵌入式系統(Embedded system)的發展0

9

LA的主要功能

4擷取 (同步和非同步模式)0即時非侵入式測試工具 允許待測電路全速執行

4儲存 (一般 轉態 條件儲存模式)0所存的數據用作對糾纏不清的邏輯或代碼進行後續處理分析

4觸發(Trigger)和限定(Qualification)0挑戰您的智慧 節約您的時間 善待您老板的資金和投入

4顯示(狀態 波形 直方圖 高階代碼)0您需要有意義的信息顯示而不是一大堆的二進制碼

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

5

Driving InnovationCreates Digital Debugging Challenges

Todayrsquos speeds are causing more signal integrity challenges than ever

4 Faster synchronous bus architectures0Faster clock amp data rates0Quicker rise amp fall times0Shorter setup amp hold times

4 Electrical amp physical challenges0Smaller logic swings0Differential signals0More signals to measure0Signal impedance amp termination issues

Digital Designers need to be able to correlate the Digital Designers need to be able to correlate the analog characteristics of their digital signalsanalog characteristics of their digital signals

6

偵錯階段

電錶

Emulator軟體偵錯工具偵錯工具

即時示波器

邏輯分析儀

初始電氣特性檢查

硬體功能檢查

軟體整合及偵錯

系統最佳化

參數及極限分析

硬體偵錯

硬體及軟體偵錯

硬體 amp 軟體偵錯階段及工具

7

什麼是LA (Logic Analyzer)

時域儀器(電壓 vs 時間)頻域儀器(功率 vs 頻率)調制域儀器(頻率 vs 時間)邏輯域儀器(邏輯 vs 時間)

示波器

頻譜或FFT分析儀調制域(向量)分析儀邏輯分析儀

8

為何需要LA

4因為LA能夠解決以下問題 0跟蹤微處理機的即時代碼數據

0同時觀察多路邏輯訊息

0擷取間歇性系統故障0系統崩潰的原因跟蹤0嵌入式系統(Embedded system)的發展0

9

LA的主要功能

4擷取 (同步和非同步模式)0即時非侵入式測試工具 允許待測電路全速執行

4儲存 (一般 轉態 條件儲存模式)0所存的數據用作對糾纏不清的邏輯或代碼進行後續處理分析

4觸發(Trigger)和限定(Qualification)0挑戰您的智慧 節約您的時間 善待您老板的資金和投入

4顯示(狀態 波形 直方圖 高階代碼)0您需要有意義的信息顯示而不是一大堆的二進制碼

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

6

偵錯階段

電錶

Emulator軟體偵錯工具偵錯工具

即時示波器

邏輯分析儀

初始電氣特性檢查

硬體功能檢查

軟體整合及偵錯

系統最佳化

參數及極限分析

硬體偵錯

硬體及軟體偵錯

硬體 amp 軟體偵錯階段及工具

7

什麼是LA (Logic Analyzer)

時域儀器(電壓 vs 時間)頻域儀器(功率 vs 頻率)調制域儀器(頻率 vs 時間)邏輯域儀器(邏輯 vs 時間)

示波器

頻譜或FFT分析儀調制域(向量)分析儀邏輯分析儀

8

為何需要LA

4因為LA能夠解決以下問題 0跟蹤微處理機的即時代碼數據

0同時觀察多路邏輯訊息

0擷取間歇性系統故障0系統崩潰的原因跟蹤0嵌入式系統(Embedded system)的發展0

9

LA的主要功能

4擷取 (同步和非同步模式)0即時非侵入式測試工具 允許待測電路全速執行

4儲存 (一般 轉態 條件儲存模式)0所存的數據用作對糾纏不清的邏輯或代碼進行後續處理分析

4觸發(Trigger)和限定(Qualification)0挑戰您的智慧 節約您的時間 善待您老板的資金和投入

4顯示(狀態 波形 直方圖 高階代碼)0您需要有意義的信息顯示而不是一大堆的二進制碼

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

7

什麼是LA (Logic Analyzer)

時域儀器(電壓 vs 時間)頻域儀器(功率 vs 頻率)調制域儀器(頻率 vs 時間)邏輯域儀器(邏輯 vs 時間)

示波器

頻譜或FFT分析儀調制域(向量)分析儀邏輯分析儀

8

為何需要LA

4因為LA能夠解決以下問題 0跟蹤微處理機的即時代碼數據

0同時觀察多路邏輯訊息

0擷取間歇性系統故障0系統崩潰的原因跟蹤0嵌入式系統(Embedded system)的發展0

9

LA的主要功能

4擷取 (同步和非同步模式)0即時非侵入式測試工具 允許待測電路全速執行

4儲存 (一般 轉態 條件儲存模式)0所存的數據用作對糾纏不清的邏輯或代碼進行後續處理分析

4觸發(Trigger)和限定(Qualification)0挑戰您的智慧 節約您的時間 善待您老板的資金和投入

4顯示(狀態 波形 直方圖 高階代碼)0您需要有意義的信息顯示而不是一大堆的二進制碼

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

8

為何需要LA

4因為LA能夠解決以下問題 0跟蹤微處理機的即時代碼數據

0同時觀察多路邏輯訊息

0擷取間歇性系統故障0系統崩潰的原因跟蹤0嵌入式系統(Embedded system)的發展0

9

LA的主要功能

4擷取 (同步和非同步模式)0即時非侵入式測試工具 允許待測電路全速執行

4儲存 (一般 轉態 條件儲存模式)0所存的數據用作對糾纏不清的邏輯或代碼進行後續處理分析

4觸發(Trigger)和限定(Qualification)0挑戰您的智慧 節約您的時間 善待您老板的資金和投入

4顯示(狀態 波形 直方圖 高階代碼)0您需要有意義的信息顯示而不是一大堆的二進制碼

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

9

LA的主要功能

4擷取 (同步和非同步模式)0即時非侵入式測試工具 允許待測電路全速執行

4儲存 (一般 轉態 條件儲存模式)0所存的數據用作對糾纏不清的邏輯或代碼進行後續處理分析

4觸發(Trigger)和限定(Qualification)0挑戰您的智慧 節約您的時間 善待您老板的資金和投入

4顯示(狀態 波形 直方圖 高階代碼)0您需要有意義的信息顯示而不是一大堆的二進制碼

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

10

4通道數

4儲存深度和限定

4擷取速度

4觸發能力

4可同時觀察同步與非同步數據

LA的主要指標

由信號頻寬(BW)或Processor Bus 時序決定

靈活 易於理解和設定

34CH for 8位元CPU 例如 8031680568CH for 16位元CPU 例如 808668IIC11102CH for 32位元CPU 例如 8038668360136CH for 例如 P6Power PCor System

硬體設計 64K軟體設計 長記憶體(Deep Mem) 4M~16M軟 硬體整合 由使用者選擇長度

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

11

邏輯分析儀方塊圖

ReferenceMemory

DATA

MemoryAddressRegister

AcquisitionMemory

SampleClock

Generator

TriggerControl

DATA DisplayControl

Log-inRegister

同步(SYNC)

非同步(ASYNC)

BUFFERS

Store Clock

DATA

ClockQualifier

ExternalClock

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

12

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

13

數位臨界值比較

4LA Probe好比多個具有1位元垂直分辨率的示波器

臨界電壓

LA顯示

LA顯示

比較器

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

14

4多通道

4限制的動態範圍

41位元的垂直解析度 (類似比較器)4輸入(或探棒) 具有臨界點設定

0固定值 (TTLCMOS logic) 0可變值 (+- 5-10V)

4探棒可改變或降低頻寬

0額外電路探棒頭接地皆會影響其系統性能

LA數位探棒之特性

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

15

LA的架構

探捧 -以數位的觀點來看

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

16

非同步(Asynchronous) vs 同步(Synchronous)

4非同步(Asynchronous) 時序(Timing)0邏輯分析儀產生取樣時脈

0愈快愈好

4同步(Synchronous) 狀態(State)0由待測系統產生取樣時脈0邏輯分析儀可接受的外部時脈頻率需足夠

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

17

時序(Timing)分析

4由邏輯分析儀產生非同步時脈作取樣週期

4快速 -提供足夠的解析度(resolution)4主要規格 = 最小可偵測的脈波寬度

LA產生的取樣週期

0 0 0 0 01 11

50 GHz = 20ps clock

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

18

時序(Timing)分析

4最佳取樣週期為待測信號週期的5至10倍

原始信號

快速取樣週期

LA 顯示

慢速取樣週期

LA 顯示

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

19

非同步時序精確性

4所有邏輯分析儀都有最大正負1個取樣週期的誤差

A 正誤差範圍B 負誤差量C 正誤差量

LA取樣週期

0 00 1 1 0 1 0

0 1 10 0

DATA

LA顯示

AB

C

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

20

解析度(Resolution) vs 精確度(Accuracy)

bull Delay 1 Delay 2

1 2 S a m p l e s

1 S a m p l e

D a t a 1

D a t a 2

足 夠 的 解 析 度

1 S a m p l e

4 S a m p l e sD e l a y 1

D e l a y 2

不 足 的 解 析 度

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

21

頻道間的延遲(Skew)

4信號路徑中不同的延遲時間

邏輯分析儀

Ch 1

Ch 1

Ch 2

Ch 2

頻道間的延遲

信號端

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

22

臨界值精確度的影響

4信號的臨界點0臨界點的精確度影響時序測試的精確度

邊緣誤差

高臨界值

低臨界值

高臨界值所判斷的資料

低臨界值所判斷的資料

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

23

4主要規格0TCLK min (最快的取樣週期)0TSKEW min (頻道間的延遲時間)0TDATA-WIDTH min (最短的擷取資料事件時間)4TDATA-WIDTH min = TCLK min + TSKEW min

0TGLITCH min (最小可擷取資料的脈波寬度)

4次要規格0TR min (轉態上升時間 -頻寬的功能) 0VTHRESH-ACC (臨界點電壓精確度誤差) 0VSWING min (輸入電壓可被擷取的最小變化)

非同步(時序模式)規格

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

24

常規(Conventional) vs 轉態(Transitional)

4轉態時序0僅儲存在邏輯產生變化時

0維持高取樣率及節省記憶體

Data

0 0 1 1 01

0010 1 0

Conventional = 8 locations

Transitional = 4 locations

LA 內部的取樣時序

取樣時序從資料轉態點取得

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

25

Benefits of Faster Edge Rates

4快速的信號Edge可以減少信號因轉態時間所造成的誤差

4快速的信號Edge可以減少信號因臨界電壓所造成的誤差

CYCLE TIME

TRANSITION TIME

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

26

Faster Edge Rates Challenges

4快速的信號Edge容易因傳輸線的負載效應造成Turn Lump

4快速的信號Edge代表有一很大的瞬時電流0Increased ground bounce especially on wide buses0Increased crosstalk

Turn Lumped

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

27

Fast Digital Signal EdgesCreate Signal Integrity Problems

Digital Signal

4Signal integrity problems results from the complex interactions of0Output drivers0Signal path layout0Signal path loads0Signal path termination0Ground and power distribution

AnalogSignal

Error

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

28

Capture Elusive Hardware Problems4 Glitches4 Logic level violations4 Setuphold violations4 Logic errors 4 Crosstalk4 Reflections4 Bus contention 4 Termination errors4 Clock skew4 Missing clocks4 Missing data4 Refresh problems4 Power supply problems4 Ground bounce problems

4 Propagation delay errors4 Incorrect state4 Timing margins amp violations4 Pulse width violations4 Propagation delay errors4 Critical races 4 Timing hazards4 Metastability4 Errors in bridge circuits4 Thermal circuit errors 4 Handshake errors4 Address decoding errors 4 Fan out errors4 Tri-state errors

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

29

GlitchesCapture Elusive Hardware Problems

4Glitches cause errors in state machine logic0Counter circuits trigger circuits etc

4Unexpected signals4Very short in duration4Hard to detect amp trigger on4May occur infrequently

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

30

Logic Analyzer Timing OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous

0Precise time interval measurement for signal to signal edges or pulseevent widths

0Faster the sample rate the finer the resolution

0Also called general purpose timing

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

31

Logic Analyzer Timing OperationClocking is Internal (From the Logic Analyzer)

ProbingAnalysisamp Display

TriggerControl

InternalClocking

Target

Logic Analyzer

Acquisition Memory

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

32

Glitch ErrorsGlitch Trigger amp Display

A3 is a 4 bit busA2 is a 8 bit bus

Glitches are occurring on A3 bus

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

33

Glitch ErrorsExpand A3 bus into its 4 signal lines

A3(3) and A3(0) have glitches

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

34

Glitch ErrorsView A3(3) Glitches with 8 GHz (125 ps) MagniVu Timing

A3(3) glitches measured with 125 ps resolution

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

35

50 GHz (20 ps) 128 Kb depth421 GHz adjustable sample rateTrigger position variable from 0-65 pre-fillIndependent MagniVutrade and Main triggersAlways available in ALL clocking modes

Breakthrough 50 GHz MagniVutrade50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz Analog

Anytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

50 GHzSample

50GHz MagniVu Timing128 Kb

28 MHz Stateor

64 GHz Deep Timing

2M ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

36

Glitch ErrorsAnalog measurements time correlated with digital signals

A3(3) glitches measured with external oscilloscopeusing the logic analyzer probes

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

37

Glitch Caused by PCB Reflection

臨界電壓

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

38

PCB Reflection error2 ns Deep Timing amp 20 ps MagniVu Timing

臨界電壓

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

39

Crosstalk Errors

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

40

Bus Delay Error

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

41

時序(Timing)分析特點

硬體軟體整合硬體偵錯0取代示波器可同時監測許多頻道間的相對關係0提供比示波器更多更強的觸發能力(資料事件LevelActionshellip)0分析匯流排信號 (Address Data Control)0偵測競態條件(race conditions) 短時脈衝波 時序問題0可發現時序上的問題

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

42

同步 (狀態)

4 取樣時脈由待測裝置系統產生4 LA 擷取資料當待測系統也視該資料為有效時

4 設定(Setup)時間和保持(Hold)時間是關鍵性的規格4 LA取樣時間必須跟待測系統一樣快 -愈快並不一定好

最小可偵測的脈波寬度

外部時脈

資料

設定時間保持時間

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

43

匯流排速度 vs 處理器速度

4時脈速度不等於匯流排速度

68020

ClockT1 T2 T3

One Bus Cycle

Clock

OneBus Cycle

R3000

OneBus Cycle

33 MHz Clock =11 MHz Bus

33 MHz Clock =66 MHz Bus

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

44

Setup Hold Time Requirement

DATA

OUTPUT

CLOCK

DATA

CLOCK

OUTPUTD

CK

Q

基本儲存單元

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

45

早於Setup-Time的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

46

違反設定時間

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

47

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

違反保持時間

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

48

晚於Hold-Time之後的資料

DATA

CLOCK

OUTPUTD

CK

Q

DATA

OUTPUT

CLOCK

Setup Hold

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

49

SetupHold Violation Error Caused Glitch50 GHz (20 ps) MagniVu Timing

Data-in(0) changed15 ns before the clock edgeFlip-flop setup specification is 25 ns Glitch

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

50

Glitches Some CausesViolation of Device Input SetupHold Timing

4 Input setup timing requirements0Input signal has to be stable before

the clock edge

4 Input hold timing requirements0Input signal has to be stable after

the clock edge

Clock Input

thold

tsetup

D Input

Data

Clock

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

51

D Flip-Flop Electrical Characteristics

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

52

Need for 125 ps Timing

Typical Digital Devices

200 MHz133 MHz

80 MHz66 MHz50 MHz50 MHz33 MHz16 MHz16 MHz

na

Altera Max 7000 PLDLattice GAL22V10-7 PALTI TMS320C549-40 DSPMotorola MCM69D536 SRAMMotorola MPC 860 Comm ControllerIDT 72420L20 Synchronous FIFOMotorola Coldfire MCF 5206 MicrocontrollerMotorola MC68332 MicrocontrollerAMD 29DL800B Flash MemoryTI FN74LVC573A Octal Latch

25 ns45 ns

5 ns3 ns4 ns5 ns3 ns5 ns

35 ns2 ns

Clock Rate

05 ns0 ns0 ns1 ns2 ns1 ns3 ns0 ns0 ns

15 ns

Setup Hold

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

53

State OperationLogic Analyzer Acquires Data on a Clock Edge

4State is clocking external from the circuit under test0Store data when valid - Synchronous

0Setup amp hold violations

0Use for processor buses amp state machines

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

54

Logic Analyzer State AcquisitionClocking is External (From the Target)

ProbingAnalysisamp Display

TriggerControl

External Clocking

Target

Logic Analyzer

Acquisition Memory

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

55

SetupHold ViolationState Acquisition and 50 GHz (20 ps) MagniVu Timing

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

56

SetupHold ViolationData-In Changed 375 ps before Clock edge

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

57

AutoDeskewDeskew

4AutomateDeskew of logic analyzer sample position0Per channel

analysis0Supports

externalexternal 2X external 4Xand custom clock modes

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

58

AutoDeskewVerify

4Verify logic analyzer sample position placement0Utilizes setuphold

violation detection to verify the TLArsquos ability to capture valid data

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

59

Timing amp State OperationLogic Analyzer Acquires Data on a Clock Edge

4Timing is clocking internal to the logic analyzer0Store at fixed intervals - Asynchronous0Precise time interval measurement for signal to signal edges

or pulseevent widths0Capture glitches

4State is clocking external from the circuit under test0Store data when valid - Synchronous0Use for processor buses amp state machines0Setuphold violations

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

60

4主要規格0TPERIOD min (時脈週期)0TCLOCK min (時脈寬度 highlow)0TSU min (設定時間)0TH min (保持時間)

4次要規格0TSU min + TH min4(設定與保持時間窗口)

同步(狀態模式)規格

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

61

時間標記(Time stamp)

4提供多重顯示時資料的時間關係

4提供兩個事件間的時間關係

4太克永遠提供時間標記的資料

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

62

資料的時間標記

4使用在狀態分析(State Analysis)4多個模組同時擷取資料需要作時間關連

Data A - 1 timestampData A - 2 timestampData A - 3 timestampData A - 4 timestampData A - 5 timestamp

Data B - 1 timestampData B - 2 timestampData B - 3 timestampData B - 4 timestampData B - 5 timestamp

Data A - 1 timestampData A - 2 timestampData B - 1 timestampData A - 4 timestampData A - 5 timestampData B - 2 timestampData A - 2 timestampData A - 3 timestampData B - 3 timestampData A - 5 timestamp

CORRELATION

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

63

狀態(State)擷取特點

硬體軟體整合軟體偵錯0主要使用在微處理器的分析

0其次使用在一般同步系統的分析 (目前大部份系統都是同步)0將複雜的微處理器和匯流排反應重建為易於了解的格式

(反組譯 disassembly)

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

64

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

65

觸發(Triggering)

4告訴LA何時該停止擷取資料

4動態地告訴LA何時該儲存資料

4觸發其他的模組

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

66

觸發來源

4資源(事件) 0資料識別(字元和範圍)0時鐘(Timer)計數器(Counters)

4狀態層(Levels)0尋找一串列事件

4反應(Actions)0事件發生後的動作

速度是主要的規格0多快能在一系列的資料中找到所要的事件

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

67

4一個觸發動作包含偵測到事件發生並作出反應

ndash Eventsndash Word Recognitionndash Sequence Recognitionndash External Event

ndash Actionsndash StopStart Storagendash External Pulsendash Pause Data Storagendash Trigger

ndash Range Recognitionndash Counterndash Timer

ndash Go State xndash Control Timerndash Control Counter

觸發資源

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

68

Trigger State Machine

4偵測序列事件

4在每個狀態中作出反應0Control CountersTimers0Go To State X0Trigger other modules0Trigger System

State1

State0

State2

State3

Trigger State Machine

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

69

Trigger State Machine

4每個狀態可檢查一個或多個條件0ANDOR Events0IfThenElse

Conditions

IF(test 3)

Actions

State0

Else Else Else

Conditions Conditions Conditions

Actions ActionsActions

IF(test 0)

IF(test 1)

IF(test 2)

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

70

Level vs State Triggering

4Level vs State Triggering0序列處理 vs 並列處理

4太克使用State Triggering架構0概念 = 提供許多觸發步驟其中每個步驟皆可做許多的反應或是測量

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

71

Trigger Libraries

4快速完成所需的觸發條件設定0選擇預先定義的觸發結構設定0輸入所需的條件參數

0TLA 允許使用者自定Libraries

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

72

Triggering

4多樣化的觸發資源讓使用者更容易限定觸發條件0快速找到問題的根源

4軟體偵錯需要複雜的觸發設定0迴圈觸發 多重路徑 序列事件0If A Then B Else C

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

73

LA的架構

探捧 -以數位的看法

非同步(asynchronous)和同步(synchronous)觸發狀態機(Trigger state machine)擷取記憶體(Acquisition memory)

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

74

擷取記憶體

4擷取記憶體(Acquisition memory)0主要的資料儲存

0所有通道的記錄長度皆相同

0深度記憶體(Deeper memory) = 儲存更長的時間(資料)4轉態儲存時序(Transitional Timing)延長記憶體的儲存能力

4限定儲存(Qualified Storage)延長記憶體的儲存能力

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

75

記憶體深度與擷取時間

VISIBLESYMPTOM

CAUSE OFPROBLEM

POST-TRIGGERDATA

You CANT acquirethis data withoutdeeper memory

Trigger PointPRE-TRIGGER

DATA

BC

A

EXAMPLE TRIGGER POSITION DATA CAPTURED

A End of Memory All Pre-TriggerB Center of Memory Half Pre-Trigger

Half Post-TriggerC Beginning of Memory All Post-Trigger

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

76

限定儲存

IO Program - Reads Data amp Writes Data

InitializeDataRead

ProcessData

Wait forDeviceReady

IdelLoop

DataWrite

Store Store

僅儲存所需的資料

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

77

Simultaneous StateTiming -All Through The Same Probe

General-PurposeLogic Analyzer

Modules

High-SpeedTiming Modules TLA 7000 Series

Logic AnalyzerModule

Other Logic Analyzers TLA 7000 Seriesbull Multiple probing connectionsbull Multiple probe loads per signalbull Complex user interface setupbull Extra cost

bull Single probing connectionbull Single probe load per signalbull Easy-to-accessbull Standard

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

78

Logic AnalyzerSupport Package

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

79

Support Package

4 What do you need 0CPU or Bus0Package (DIP PLCC LCC PGA PQFPhellip)0Run Control ( Like ICE functionhellip)4Non-intrusive tool

0High-Level Language support (IEEE 695 OMFx86hellip)0Monitor Multiple CPU orand Bus

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

80

Support Package

4 Include Software Adapter Disassembly0Need installation to LA0Connect to Target Board0Re-load the support package 0Setup Trigger condition0Viewing the acquisition data in data window

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

81

80c1678x251Sx8x296SAAGP 1X2Xi960RPRDPentium IIPentium IIIMCF52020406P5455MPC505509MPC860821MPC850823801MPC8260PPC750740PPC403AMD K6-2SH-3Cyrix 6x8668HC12TMS320C6201AGP4XRAMBUS

TMS Post-Intro 1750a

29000050320c20253240506502802rc02680968302 68HC1116808580c166Arm coreGPIBPacqMem 3468102136PPC603evSerialTSC701Z180M-Core80C3xx80C5xx68180

AE Support

Compact PCIEISAISAMIPS R3081MIPS R4000MIPS R5000MIPS RM5200MIPS R7000MIPS RC647xPCI (several variations)PCMCIACard BusSIMMDIMMS-DIMMUSBVMEMPC8240Strong ARM SA1105630x

Third Party Support808688

801861888028680386DX80386SX80386EXi486P54P55P68031518096C19680C196NXi960CACFi960Jxi960Hxi960RP680001068020680306804068060MCF520203CPU326834068360R30515281290303540Z80PPC60xTMS320C3xAPICSCSI

TMS Intro

Current ProcessorBus Support

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

82

Software Debug solution

4Multi-Processor Embedded Software requires0Disassembler Support (see Appendix A)

4Disassembler for processor support082x0 74xx 7x0 8x0 Mcore 68K ColdFire DSPhellip

4Disassembler for Bus support0PCI-ExpressGen2SATA Inifiniband rapid IO PCI CPCI GBE USB 1394 GPIB Micro channel Utopiahellip

4Disassembler for Memory structures 0DDRIII1600RAMBUS DDR266 DDR400 DDRII667FBD PC133 DIMM SIMMhellip

0Require Deep and Time correlated acquisition4Micro to Micro Correlation

4Micro to Bus Correlation

4Up to 256M Trace depth per channel

4156ps Timestamp resolution on all channels

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

83

Embedded Software DebuggingReal-time Hardware Trace

Real-time Instruction Trace

Non-intrusive

Source Code Debug

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

84

High Level Source Debug

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

85

Run Control tools Integrated with Logic Analyzers

Real-time TraceLogic Analyzer

Probes

Ethernet or Parallel interface

Run ControlJTAGBDM

Target System

LA TRACE bridges the gap

Integrated HWSW Development

4 Utilize logic analyzers to capture information and integrate with run control tools

4 Unify display of data in a single window

4 Key features0 Sync Wind River ICE with the LA

(cross trigger data transfer)0 Trace in Wind Rivers debug window

that integrates with the LA0 Event generation ability to generate

events from Wind Rivers source window

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

86

Embedded Systems Development Tools

4 Run Control0Ability to set hardwareSoftware

breakpoints 0Correlated real-time trace of executing

software - with Logic Analyzer

0Event Trace capability in native software environment - with Logic Analyzer

0Code instrumentation - with Logic Analyzer

0Code profiling with Cache enabled - with Logic Analyzer

0RTOS Task awareness - with Logic Analyzer

4 Logic Analyzer0Analog amp digital signal acquisition amp

analysis0Multiple bus capture

4Diassassembler for MicroBuses4 Fully Correlated Real time analysis

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

87

Output Window of a Typical Trace System

LA Real time trace Data

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

88

Function Profile

4 All information is extracted From Logic acquired Analyzer Data0Full Time Stamp available from LA0Full Function profile ndash Min Max amp Average Entry to Exit Time

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

89

Basic Trace and Breakpoints ldquoHardware Code Breakpointrdquo

4 Ability to Set ldquoHardware Code Breakpointrdquo0Once the Logic

Analyzer BP is set Run the Target until the Breakpoint initiates the ldquoTarget Stopped MSGrdquo (Trigger)

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

90

Logic Analyzer Setup

4 The Logic Analyzer is configured by LATrace to trigger on 00040670

4 lsquoSignal Outrsquo will be generated by the TLA when 00040670 is on Address bus

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

91

Debugging in a Multiple-Bus Environment

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

92

Memory StructureRAMBUS

DDRSDRAM

MasterMPC750

GBE

1394

USB

603e coreUtopia

PowerQuiccII Slave 2

PCILocal

603e coreUtopia

PowerQuiccII Slave 1

PCILocal

DSx

LO

CLK

QBus

IBus

I

RF

Q

DSP FPGA ASIC (Wireless Application)

TelcoIF

Cntl

CPU

DA

MOD

DSPCoding

ModFiltering

MIPSR7000

Multi-ProcessorBus Environment- Typical Embedded System -

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

93

8260 750

MIPS

PCI

FireWire

Five Real-time Instruction TraceWindows

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

94

8260 750 R7000 PCI

Integrated Real-time Instruction Trace

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

95

Review

Platform Architecture Probing IViewtrade

- Performance Analysis- Function profile

Real-Time CorrelatedInstruction Trace

- Conditional Trace- Code instrumentation- Task-Aware Trace

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

96

External Logic Analyzer Approach Revisited4 Route internal signals to debug pins0Make use of the programmable nature of FPGAs

Approach is useful but has limitationshellip0Changing probe points often takes recompile4 Recompile of design changes timing and uses up engineering

time011 relationship between internal probe points and debug pins

limits visibility

There is a betterhellip FPGAViewtrade

Test Mux

JTAG

JTAG Cable

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

97

Introducing A Better Way

Real-Time Logic Debug Solution for Altera FPGAs

A Tektronix Altera and First Silicon Solutions (FS2) collaboration

ltltTLA picturegtgtltltpicturegtgt ltltscreen shotgtgt

19

Supports all TektronixTLA Logic Analyzers

Supports completerange of Altera FPGAs

FPGAView fromFirst Systems Solutions

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

98

Real-Time Logic Debug Solution for Altera FPGAsBenefits

4Enables real-time debugging of Altera FPGAs0For RampD engineers designing with Altera FPGAs0Allows design teams to view the internal operation of their

Altera FPGA design0Allows correlation of these signals with other board signals

4Increases productivity and cuts debugging time0Change internal probe points in instant ndash no need to

recompile your design0Monitor multiple internal signals per debug pin

4Easier to use and less intrusive than other debug methodologies

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

99

Real-Time Logic Debug Solution for Altera FPGAs overview4 Software package developed by

First Silicon Solutions (wwwfs2com)0 Supports Altera FPGA devices0 Runs on Windows 2000 and

Windows XP machines

Altera USB-Blastertrade or ByteBlastertradeJTAGCable

Tektronix TLA Series Logic Analyzerrunning v43 or later

LogicAnalyzer

FS2 FPGAViewtradeControl Software

Altera Quartusreg II v51Multiplexer

SolutionFunction

Altera Quartusreg II v51 Logic Analyzer Interface

JTAG

USB-Blastertrade orByteBlastertrade

TektronixLogic Analyzer Probe

FPGAViewtradeSoftware

FPGA

PC Board

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

100

Using FPGAView4 Easy Steps

4 Step 1 - Create the Logic Analyzer Interface Block

4 Step 2 - Configure FPGAView for your debug environment

4 Step 3 - Map FPGA Pins to Logic Analyzer

4 Step 4 - Make Your Measurement

Create the Logic Analyzer Interface

Block

Configure FPGAView for your debug environment

Map FPGA Pins to Logic Analyzer

Make Your Measurement

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

101

Using FPGAViewStep 1 ndash Create the Logic Analyzer Interface Block

4Use Altera Quartus II Logic Analyzer Interface Editor to define and insert Logic Analyzer Interface0Available in all editions of Quartus II including free Web

Edition

Specify number ofdebug pins

Specify Number of Banks

Specify Mode

Specify Clock(if using State Mode)

Power-Up Mode

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

102

Using FPGAViewStep 2 ndash Configure FPGAView for your debug environment

Specify JTAG Interface

Specify TLA Interface

Open lai file

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

103

Using FPGAViewStep 3 ndash Map FPGA Pins to Logic Analyzer

4Use FPGAView to ldquoconnectrdquo FPGA pins to logic analyzer0Enables automatic

channel name updating0Drag amp Drop operation0Supports multiple LAIs

FPGAs TLA modules

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

104

Using FPGAViewStep 4 ndash Make Your Measurement

4 Use Bank pull-down list to select Bank to measure0 After selection FPGAView

sets up LAI via JTAG0 Programs the TLA with the

proper signal names4 Makes it easy to

interpret measurement results

4 Easily switch internal probe points by selecting a different Bank0 No need to recompile your

design4 Correlate FPGA signals with

other signals in your system

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

105

Introducing the Next Generation of the TLA 7000 amp TLA5000Series of Logic

Analyzers

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

106

TLA FAMILY

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

107

104rdquo264 cm

Expand the view of your analysis

TLA7012 - Largest display on a logic analyzer15rdquo Active TFT

15rdquo381 cm

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

108

Easier Access to Results

4Windows XP Remote Desktop - Send only the screen

4New Remote Hosted Mode - Send the data for full analysis

Lab 2

Lab 3

InternetInternet

Lab 1

LANLAN

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

109

TLA7000 Mainframes

4TLA7012 Portable Mainframe2 Module Mainframe

4TLA7016 Benchtop Mainframe6 Module Mainframe

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

110

TLA7012 Portable Mainframe2 Module Mainframe

Product OverviewWorldrsquos largest display on LA ndash 15 inch 381 cm (1024x768 resolution)Optional touch screenCompatible with all TLA Modules6x faster system data throughputPC Hosted UI with V5051 TLA App SWSame width amp depth as TLA715 ndash 2 inch 51 cm taller for larger display

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

111

Product DetailsIntelreg 2 GHz Pentiumreg M-760

Intelreg 915GM chipset (533 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN7 USB 20 ports (3 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPMHard DriveDual external display outputs (1600x1200)Optional 35rdquo USB floppy availableNo PC Card PS2 serial nor parallel ports

USB-to-serialparallel adapters available via 3rd

parties

Windows XP Pro + SP2 with MultilingualUser Interface Pack (34 languages)USB Security Block for secure environments

TLA7012 Portable Mainframe2 Module Mainframe

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

112

2176167 PortablesPortable

54441 PortablePortable

Config

108881 BenchtopPortable

2722---Portable Only

Max ChsMax ModulesExpansionMaster

123

TLA7012 Portable Configurations

1

TLA7012

GbESwitch

TekLinkCable

2

TLA7012 TLA7012

LANLAN

TekLinkCable

3

TLA7012 TLA7016

GbESwitch

LANLAN

4

TL708EX Hub

Customer-supplied PC

4

TekLink Cable

TLA7012

TLA7012

GbESwitch

LANLAN

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

113

TLA7016 Benchtop Mainframe6 Module Mainframe

Product OverviewSupports up to 6 TLA modulesCompatible with all TLA ModulesRequires external PC running TLA AppGigabit Ethernet Slot0 Interface Module that supports DHCP client capability6x faster system data throughputPC Hosted UI with V5051 TLA App SWSW configurable as master or expansionUpgrade kit for TLA720 TLA721 amp TLA7XM with ALL TLA7016 features

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

114

TLA7016 Benchtop Mainframe Accessories

TLA7PC1 Benchtop ControllerIntelreg 3 GHz Pentiumreg 4

Intelreg 865G chipset (800 MHz FSB)1 GB DDR2 RAM (expandable to 2 GB)Gigabit Ethernet (GbE) LAN6 USB 20 ports (2 front + 4 rear)

47 GB DVDplusmnRRW driveRemovable 35rdquo 80 GB SATA 7200 RPM Hard DiskOptional external 35rdquo USB floppy available3x PS2 (1 front amp 2 rear) 1x serial and 1x parallel3x full-size PCI slots (32-bit 33 MHz)Windows XP Pro + SP2 with Multilingual User Interface Pack (34 languages)

TLA7PC1Benchtop Controller

020-2666-xxGbE 16-port Switch

TL708EX8-port Instrument Hub and Expander

GbE Switch16 autosensing ports

TL708EXUsed to connect 3-to-8 TLA701x mainframesSupports data communication run control amp real-time triggeringSimple plug-and-play operation

020-2665-xx21rdquo Flat-Panel Display

21rdquo Flat Panel Display1600x1200 native resolution with DVI-D amp 15-pin D-Sub inputs

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

115

Config

6528487 BenchtopsBenchtop

1632121 BenchtopBenchtop

8166---Benchtop Only

Max ChsMax ModulesExpansionMaster

TLA7016 Benchtop Configurations

1

Customer-supplied PC

TLA7PC1 Tek PC1-OR-

TLA7016

GbESwitch

LANLAN

2

2

TekLink Cable

TLA7PC1 Tek PC

Customer-supplied PC

-OR-

TLA7016 TLA7016

GbESwitch

LANLAN

3

TL708EX Hub

TLA7PC1 Tek PC

Customer-supplied PC

3

TekLink Cable

-OR-

TLA7016

TLA7016

GbESwitch

LANLAN

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

116

Easily reconfigure your logic analysis systems

4 30 Big Cables0 120 screws

4 20 TLA7XM Modules

TLA721 and TLA7XM-Based System

50 fewer cables easier connections andno specialized expansion mainframes or

modules

4 8 GbE LAN Cables4 8 TekLink Cables0 32 screws

4 No TLA7XM Modules

New TLA7016-Based System

Customer-supplied PC

TL708EX Hub

TLA7PC1 Tek PC

TekLink Cable

- OR -

TLA7016GbE

Switch

LANLAN

TLA7016

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

117

V50 TLA Application Software FeaturesSimpler navigation with new look-and-feel

bull Explorer windowbull Toolbar buttonsbull Tabbed windows

Automated LA data measurementsHosted mode for online or offline operation from external PC

bull Replaces TLAVu Simultaneously connect to multiple TLAs from one PC

bull Only one TLA App-Offline per PCCompatible with all pre-V50 TLA setups and dataCompatible with

bull Windows XP Professionalbull Windows 2000 Professional

V5051 SW Runs OnTLA7012 amp TLA7016

TLA520xTLA715 amp TLA721

TLA714720TLA60x61x62x

Any PC with WinXP Pro or Win2K Pro

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

118

Locate and Analyze your Problems More Efficiently

Industry First Automated Digital Measurements and Drag-and-Drop Triggers

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

119

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

120Automated LA Data Measurements

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

121

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

122Drag-n-drop Triggering

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

123

Introducing the TLA7ABxx Logic Analyzer

Enhanced Enhanced iViewiView --SimultaneousSimultaneous

AnalogAnalog amp amp DigitalDigitalThrough the Same Through the Same

ProbeProbe

ConnectorlessConnectorlessCompressionCompressionHighHigh--DensityDensity

ProbingProbing

WorldsWorldsFirstFirst and and FastestFastest

SiGeSiGeLogic AnalyzerLogic Analyzer

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

124

8 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 2 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

800 MHz

State Clock Rate

Up to 125 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 6528 Ch Max

The TLA7Axx Logic Analyzer

Generational Advance

2 GHz 256 Mb

Deep Timing

Worldrsquos Deepest

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

125

TLA7Axx Module Overview

4 34 68 102 amp 136 channel modules4 8 GHz MagniVutrade timing 16 Kb4 500 MHz deep timing 64 Mb (all ch)4 1 GHz deep timing 128 Mb (12 ch)4 2 GHz deep timing 256 Mb (14 ch)4 450 MHz state 64 Mb (all ch)4 800 MHz state 128 Mb (12 ch)4 125 Gbs data 256 Mb (14 ch)4 Next Gen family of high-performance

07 pF probes4 2 GHz analog mux provides any of 136ch

to 4 ch analog probe output BNC

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

126

TLA7Axx Module Characteristics

4 34 68 102 amp 136 channel modules4 Up to 680 channels with 5 merged

modules0All merged channels operate off single timebase0Only 102 amp 136 channel modules can be merged

4 Up to 8160 channels with 60 modules0TLA721 with 10 TLA7XM expansion mainframes0Typical correlation accuracy of 2 ns with any

other module

4 4 Analog Probe Output BNCs on every module

4 Securely attach probes-to-module and modules-to-mainframe with captive screws

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

127

50 GHz

MagniVu Timing

Worldrsquos Fastest

Any of 136 ch Multiplexed to 4 Analog Outputs 3 GHz

Analog Probe Outputs

Worldrsquos First Logic Analyzer with Analog Mux

1400 MHz

State Clock Rate

Up to 28 Gbs Data Rate

34 to 136 Ch

Channels

680 Ch Merged - 8160 Ch Max

The TLA7Bxx Logic Analyzer

Generational Advance

64 GHz 512 Mb

Deep Timing

Worldrsquos Deepest

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

128

New TLA module TLA7ACx

All P6800P6900 Series probesProbes

Standard - 2 MbOptional - 8 Mb 32 Mb 128 MbRecord Length

Standard ndash Fixed Analog Outputs with 2 GHz Analog BandwidthOptional ndash Full Analog Mux Control with 2 GHz Analog BandwidthAnalog Mux (iCapture)

Standard ndash 235 MHz Optional ndash 450MHzState ClockData

500 ps (2 GHz) (14 channels)1 ns (1 GHz) (12 channels)

2 ns (500 MHz) (all channels)Deep Timing

125 ps (8 GHz) 16 KbMagniVutrade Timing

13610268Channels per Module

TLA7AC4TLA7AC3TLA7AC2Product

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

129

New TLAampBxx module

50GSs (20ps)-128k

Memory Depth

TLA7BB3 TLA7BB4TLA7BB2DIGITAL CHARACTERISTICS

Digital Channels

High Speed Timing (MagniVu)

Deep Memory Timing

State Speed

68 102 136

800160032006400 MSs

14GHz28Gbps

Standard 2Mb Maximum 64Mb

Probes P68xx and P69xx

Analog Mux 3 GHz

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

130

Enhanced iView

4 iView - Integrated View0 Introduced May 2001

0 Integrated view of analog and digital on a single TLA display

0Still required separate LA amp scope probes

4 Enhanced iView0Adds single analog and digital probing to

iView

Enhanced iViewEnhanced iViewSingle analog and digital probing with

integrated view of analog and digital on a single TLA display

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

131

80 ps glitch triggering amp storage with 20 ps resolution 40 ps setup amp hold time violation triggering with 20 ps resolution State sample point adjustable per channel with 20 ps resolution20 ps timestamp resolution provides precise time correlation of all data - automaticallySeparate MagniVu Trigger independent from main module trigger

50 GHzSample

r

50 GHz MagniVu Timing128 Kb

28 GHz Stateor

64 GHz Deep Timing

2M Kb ndash 256 Mb

Real-TimeClocking

StateMachine

TriggerState

Machine

+-

BreakthroughAcquisition Technology

50 GHz Timing Simultaneous with up to 28 MHz State with up to 3 GHz AnalogAnytime hellip on any channel hellip on any model hellip without reconnecting or reacquiring

iViewiView tradetrade

BREAKTHROUGHBREAKTHROUGHTECHNOLOGYTECHNOLOGY

3 GHzAnalog

Mux34 ch34 ch34 ch34 ch

Internal DSO orTDS Scope (iView)4 ch

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

132

TLA7ABxx Analog Probe Outputs

4 Single-point digital amp analog probing

4 3 GHz analog bandwidth on all channels

4 Any of up to 136 logic analyzer input channels multiplexed (10x attenuation) to 4 analog output BNCs(50Ω)

4 Analog probe outputs are always live0Use external TDS oscilloscope to

monitor signals when TLA7Axx idle

0Convenient access for other instruments

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

133

Simultaneous 3 GHz Analog Measurements Through the Same Logic Analyzer Probe

External TDS oscilloscope or TLA oscilloscope modules

DPO7000 TLA7DxEx DSADPO70k7k

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

134

Supported Tektronix Oscilloscopes

4 DSA70000 series DPO0 20GHz bandwidth 50 Gss sample rate

4 TDS7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 CSA7000 Series DPO0 4 GHz bandwidth 20 Gss sample rate

4 TDS6000 Series DSO0 6 GHz bandwidth 20 Gss sample rate

4 TDS30003000B Series DPO0 500 MHz bandwidth 25 Gss sample rate

4 Selected TDS600700 Series Models0 TDS724D754C754D784C784D794D0 TDS654C684C694C All DSADPO70K and 7k oscilloscopes require

firmware V12 or later to work with iView Before using any oscilloscope with iView it is recommended that you install the latest firmware upgrade available from Tektronix (wwwtekcom)

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

135

The icapture trade Toolset

4Quickly and easily find and characterize both analog and digital anomalies with the icapturetradetool set

0 iConnecttrade enables simultaneous digital and analog acquisition through a single probe

0 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

0 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

136

iView

4 iViewtrade displays automatically time-correlated analog and digital data in a single logic analyzer display

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

137

Analog Mux ndash Now iConnecttrade

4 iConnecttrade enables simultaneous digital and analog acquisition through a single logic analyzer probe

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

138

iVerifytrade

4 iVerifytrade enables multi-channel analysis and validation using oscilloscope-generated eye diagrams

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

139

iVerifytrade

4 Quickly generate high-resolution eye diagrams on multiple channels

4 Analyze the data by performing measurements0Horizontal and vertical

histograms0Eye-limit0 4-point and 6-point

polygon masks0Upper and lower masks0Slope0Statistical

measurements

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

140

iVerifyHorizontal and Vertical Histograms

4Perform Horizontal and Vertical Histograms Simultaneously

4Provides Hit Data in Window Below

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

141

iVerifyEye Limit Measurement

4Automatic Eye Limit Measurement0Eye Height0Eye Width

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

142

iVerifyFour and Six Point Polygon Measurement

4Four Point and Six Point Polygon Measurements with Number of Hits in Mask

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

143

iVerifySlope Measurement

4Automatic Slope Measurement in sV

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

144

iVerifyHighlight Channel

4Highlight Single Channels to Locate Problem Signals Quickly

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

145

LA Module Standard Probe

4 17 channels per probe (16 data + 1 clockdata)4 Industry-standard podlets4 Acquires Simultaneous 2 GHz Timing and 200 MHz State4 le 2 pF probe loading

P6419 P6410

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

146

New High-Density Probe

4Connects 34 channels in an extremely small area

4Full performance 200 MHz state and 2 GHz timing

4Less than 25 pF capacitive loading

4 Integral latching mechanism assures reliable connection

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

147

P68xxP69xx Logic Analyzer Probe Overview

4P6810 34-Ch General-Purpose Probe4P6860 34-Ch High-Density Probe4P6960 34-Ch High-Density Probe4P6880 34-Ch High-Density Differential Probe4P6980 34-Ch High-Density Differential Probe

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

148

P68xx SiGe Probe Technology

P6860P6860HighHigh--DensityDensity

P6880P6880DifferentialDifferential

HighHigh--DensityDensity

P6810P6810GeneralGeneral--PurposePurpose

07 pF07 pFTOTALInput

Capacitance

ProbingProbingBREAKTHROUGHBREAKTHROUGH

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

149

34-Ch High Density Active Probe

4Simultaneous digital amp analog measurements

4High-density compression probing4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing whichever

is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) digital threshold accuracy

4Minimal loading of 07 pf 20KΩ to ground

4Spare elastomer holders4 2 ea Thin (Black)4 2 ea Thick (Gray)

4PCB layout details in P68106080 Probe Manual

Two17 chprobeheads

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

150

34-CH High-Density Differential Active Probe

4 Simultaneous digital and analog measurements

4 High-density compression probing4 4 probe-heads support 89 Channels

each (9 w clockqual)4 2x mode and 4x modes utilize 2 and 1

probe-head respectively4 Full differential and single-ended data

inputs and clockquals4 -20 V to +55 V operating range4 Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 Minimal loading of 07 pf 20KΩ to

ground4 Spare elastomer holders

4 2 ea Thin (Black)4 2 ea Thick (Gray)

4 PCB layout details in P68106080 Probe Manual

Four89 chprobeheads

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

151

TLA7Axx Differential Definitions

For differential signals the magnitude of the voltage difference Vmax ndash Vmin(and Vmin-Vmax) must be greater than or equal to 150 mv

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

152

High Density Compression ProbingNo PCB Connectors Required

No PCB Connectors CostsSecure amp Reliable Connections

For P68xx probe design-in informationRefer to P68xx Probe Instruction Manual wwwtekcomla

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

153

34-Ch General-Purpose Active Probe

4Simultaneous digital amp analog measurements

4P6417 ldquolikerdquo with 34-individual ldquoactiverdquo channel podlets

4Full differential amp single-ended data amp clockquals

4 0100 and 2mm podlet amp lead-set connection capability

4 -20 V to +55 V operating range4Minimum input signal swing0 300 mV or 25 of signal swing

whichever is greater (single-ended)0 150 mV swing each side (differential)

4 +-(25 mV +1) threshold accuracy 4 07 pf 20KΩ to ground loading4Probing accessories standard

4 2 x 1ch leadsets4 4 x 8ch single-ended leadsets4 4 x 8ch differential leadsets4 40 SMT KlipChips

34Podlets

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

154

TLA5000 Series Logic AnalyzersTLA5000 Series Logic Analyzers

The debug power you need the simplicity you want and a price you can afford

The debug power you need the simplicity you want and a price you can afford

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

155

Unequaled High Performance Features

GHzDeep Memory Timing

psMagniVutradeTiming

MHzState

MbDeep Memory

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

156

Banner Specifications

2Mb ndash Std8Mb ndash Opt32Mb-Opt

Memory

235MHzState

125 ps(8GHz)

MagniVu High-Res Timing

2GHz1GHz500MHz(QuarterHalfFull Ch)

General-Purpose Deep Timing

1361026834ChannelsTLA5204TLA5203TLA5202TLA5201

General-Purpose Deep 2GHz1GHz500MHz Memory Timing (QuarterHalfFull Ch)

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

157

TLA 70005000 SeriesThe Logic Analyzer for the Entire Digital Design Team

Breakthrough Solutionsfor HW and SW Debug

David Yang楊雄偉

davidyangtektronixcom(02)-27571517

158

Thank You For Attending

158

Thank You For Attending