PLD--Programmable Logic Devices

74/5440004500,

PLDCPU+RAM+PLDPLD2

2.1.1 PLD

70PROM PLA_Programmable Logic Array 70AMD PAL_Programmable Array Logic80LatticeGAL_Generic Array Logic (2.1

80Xilinx FPGA_Field Programmable Gates Array AlteraEPLD_Erasable Programmable Logic Device

90Lattice ISP_In System Programming ispLSI2.1.1 PLD

PLD 1000 420MHz 90 nm VDSMVery Deep Sub Micrometer

PLD ISP_In System Programming

PLDIC40%PLD 35%40%

9.17.99/*

Density Leadership

1998 1999 2000 2001 2002

VirtexXCV1000

Density (system gates)

10M GatesIn 2002

Virtex-EXCV3200E

Virtex Architecture Extends to 10 Million System Gates

4M

3M

1M

10M

Virtex-II

Key Points:XCV2000, AVAILABLE NOW, is the worlds largest shipping FPGA any which way you measure it. In addition, the V3200E is the largest announced FPGA in the industry.Our technology roadmap and the Virtex architecture will allow us to deliver 4M system gate devices by year 2000 and 10M system gates by year 2002.

FYIXCV3200E Logic cells73,00820K1500E Logic cells54,720

Altera

Sheet1

RAM

FFI/Ons

APEX IIEP2A904000k8928011401,523,712

APEX20KEP20K1500E1500k518408084442,368

FLEX10KEPF10K10250k4992406424,576

FLEX8000EPF805050k40323603

FLEX6000EPF6024A24K19602185

MAX9000EPM956012k56021212

MAX7000EPM72565k25616010

MAX5000EPM51923.75k192641

ClassicEP18100.9k484820

AlteraFPGA (SOC): Stratix

Xilinx

Sheet1

CLB/FFRAM

nsmAI/O

XC2000XC2018L1.0K~1.5K10017210474

XC3000XC30905.0K~6.0K32092864144

XC3100XC3195/A6.5K~7.5K48413200.98176

XC4000XC4063EX62K~130K2304537621238473728

XC5200XC521514K~18K484193648244

XC6200XC626464K~100K16384163848512262K

XC8100XC81098.1K~9.4K26881344124208

XC7200XC7272A2.0K7212615872

XC7300XC731443.8K144234724156

XC9500XC952886.4K2882881024180

XilinxFPGA (SOC): Virtex-II Pro

Lattice

Sheet1

FF

nsI/O

ispLSI1000/Eisp10488k1922885108

ispLSI2000/E/Visp21928k1921926110

ispLSI3000isp344820k32067212224

ispLSI5000Visp5512V24k51238410384

ispLSI6000isp619225k19241615159

ispLSI8000isp884045k84011528.5312

PLD

Total 1998 PLD Market=$2.1 B Total 1999 PLD Market=$2.6 B

Source: Dataquest, March 2000

a.

ns 2 ns PLD

0.6um

30%

0.5um

50%

0.35um

70%

b. ISP ISPIn_System Programmability/Programming

PLD ISP PLD

/

ISP

ISP ISPISPISP

~ms ISP

PLD

PLDPROMEPROM EEPROMPLAFPLAPALGALCPLD EPLDEEPLDHDPLDFPGApLSI ispLSIispGALispGDS2.1.2 PLD

1 PLD PLDHDPLD500 PLDPLDPLAPROMPALGALPLDHDPLD

2

FPGAField Programmable Gates Array CPLDComplex Programmable Logic Device

FPGASRAMSRAM

FPGA

CPLD PALGAL EEPROM

PALGALCPLD

CPLD

CPLDFPGA12 CPLD500 ~ 50000 FPGA1K ~ 10M 3 CPLD1KFPGA100K 4

3 PROMPAL E2CMOS SRAM

4 EPROM EEPROM SRAM

2.2 Altera PLDFPGACLPD

a. PLD b. / c. /

PLD/(

CPLDFPGACPLD

EPM7128

FPGA

EPF10K10

576

2.2.1 Altera

AlteraPLD

Altera PLDMAX

MAX9000MAX7000MAX5000ClassicFLEX

APEX IIAPEX20KFLEX10KFLEX8000FLEX6000

MAX Multiple Array Matrix EPROM(Classic MAX5000)EEPROM MAX7000MAX9000 CPLDMAX

MAX9000MAX7000MAX5000Classic

FLEX Flexible Logic Element Matrix Look Up Table __LUT SRAM FPGA FLEX10K EAB_Embedded Array Block APEX20K FLEX

APEX IIAPEX20KFLEX10KFLEX8000FLEX6000

Altera

Sheet1

APEX20KSRAM

FLEX10KSRAM

FLEX8000SRAM

FLEX6000SRAM

MAX9000EEPROM

MAX7000EEPROM

MAX5000EPROM

ClassicEPROM

Altera I/0

Sheet1

I/O

APEX20K99~780100000~1000000

FLEX10K135~57010000~250000

FLEX800078~2082500~50000

FLEX600081~21816000~24000

MAX9000159~2166000~12000

MAX700036~212600~5000

MAX500028~100600~375

Classic22~68300~900

Altera

Altera

2.2.2 Altera FLEX 10K

1 EAB_Embedded Array Block2048/EAB LAB_Logic Array Block2 250000/40960RAM 20EAB

3

I/O SRAM JTAG(Joint Test Action Group) BST(Boundary Scan Test) ICR(In Circuit Reconfiguration), (Clock Lock) (Clock Boost)

4

Fast Track

5 I/O I/O I/O Open-Drain Option)

6 84 ~ 672

FLEX10KEPF10K10LC84

EPF10K10LC84

FLEX10KEPF10K250ABC600

EPF10K250ABC600

FLEK10K(EAB)

(LAB)

Fast Track

I/O

EAB(Embedded Array Block)

EAB 1EAB

2048 RAM 8

11

EAB FIFOROMRAM

EAB

2 EAB RAM EABRAM

2048x1 1024x2 512x4 256x8

EAB

EABRAM

RAM 4(16 x 1)RAM RAMRAM

EAB

1EABRAM

EAB 51245128

MAX+PLUS

2EABRAM

EAB2048x1 EAB4096x1 EAB

3RAMRAM4ROM ROMAlterar .mif ROM3EAB FIFO FIFOFirst In First Out- 4EABLUTLook up Table EAB LUT

5EAB EABLUT 6 EAB

LAB _Logic Array Block

LAB8LELABLAB

4ClockPresetClearOE

LE LE(Logic Element) FLEX10K

1 LUT 2

3 LE0.2ns

n+1LEn

LUT

4 LUT

nLE4n

Fast Track

FLEX 10K Fast Track

,

FPGA

Xilinx XC4000

I/O IOEInput Output Element

FLEX10KI/OIOEIOEI/O

2.3 Xilinx Virtex

2.3.1 1. FPGA 50K ~ 1M 200MHz2. Select I/O 16 3. DLL24

4. LUTRAM RAMRAM40965. 7. SRAM

2.3.2

3

/IOB CLB_Configurable Logic Block;

Virtex FPGA

1. CLB_Configurable Logic Block CLBCLBslicesliceLC

CLB

2. Slice LC_Logic Cell

Slice

3. RAMBlock SelectRAM RAMRAM 4096 4096 RAM

4. / IOB_ Input/Output Block

IOB Bank Virtex IOB 8 Bank Bank Vcco I/O

/

5. 4 1 2

/General Routing Matrix

3I/O

Virtex VersaRing CLB IOB

4

24

4

6. DLL_Delay Lock Loop

DLL

DLL

2.4 (ISP)GAL LatticeISP LatticeispLSI/pLSIGAL

ispLSI/pLSI

GLB

ISP

ISP_In System Programmable Lattice FPGA Xilinx ICR_In Circuit Reconfigure Altera

2.5 FPGACPLD1 AlteraXilinx ~ Lattice

20%

2

3 CPLD5 V3.3 V FPGA5 V3.3 V2.5 V 1.8 V1.5 V

4FPGA/CPLD CPLD 1 21000 ~ 50000 3 4 5ISP 6

FPGA 1 2 5000 ~ 3 SOC 4ASIC 5 6 ROM 5FPGA/CPLD PLCCPQFQTQFPRQFP VQFPMQFPPGABGA 28 ~ 1517

1Altera 2FLEX 10K 3FLEX 10KEAB 4ISP 5CPLDFPGA

1. PLD--Programmable Logic Devices

70PROMPLA 70AMDPAL Programmable Array Logic 80LatticePALGAL Generic Array Logic)( 80Xilinx FPGA Field Programmable Gates Array AlteraEPLDErasable Programmable Logic Device 90Lattice(ISP__In System Programming) ispLSI

70PROMPLA 70AMDPAL Programmable Array Logic 80LatticePALGAL Generic Array Logic)( 80Xilinx FPGA Field Programmable Gates Array AlteraEPLDErasable Programmable Logic Device 90Lattice(ISP__In System Programming) ispLSI

PLD1000300MHz 0.1umVDSMVery Deep Sub Micrometer

ISPPLD

1995 PLDIC 40% PLD35% PLD40%

3. PLD a. ns 2ns

b. ISP ISPPLD

b. ISP ISPIn_System Programmability/Programming

PLD ISP PLD

ISP PLD ISP

~ms

CPLDFPGA

1 CPLD FPGA2 CPLD FPGA3 CPLD FPGA

CPLDFPGA

1 CPLD FPGA2 CPLD FPGA3 CPLD FPGA

CPLDFPGA

1 CPLD FPGA2 CPLD FPGA3 CPLD FPGA

3RAMRAM EABRAMRAM

1LUT LUT(Look Up Table)4 LUT

2 DTJKSR (Clock)(Clear)(Preset) I/O LUTLUTLE

1I/O/ 2 3 4 1) slice LC 2) 4 LUT 3) CLBD 4) CLBGRM_General Routing Matrix 5) LUT RAMLUT 16 x 1 RAM LUT 16 x 2 32 x 1 RAM 16 x 1 RAM RAM

/ 1 50k ~ 15k 2

1CLB GRMGeneral Routing Matrix 2CLB CLB LUT 3 CLB GRM

GRM GRM 24 GRM GRM