Growth Networks Inc - An OverviewARM / (Load/Store) (Ex: C=A+B for four classes)

Add
Pop the top-2 values of the stack (A, B) and push the result value into the stack
Pop C
Load A
Add B
Add AC (A) with B and store the result into AC
Store C
(register-memory)


ADC
BLX
BX
CDP
LDM
MCR
MLA
MRS
MUL
SBC
STM
SUB
TEQ
“#” ;
1: R3 1 R3 ;
2: 32-bit R7 8-bit AND R8
Microprocessor Ch3-*
;
R1 R2 R0
Microprocessor Ch3-*
LDR R0, [R1] ; R0 ← [R1]
STR R0, [R1] ; [R1] ← R0
;
;
1: R2 R1 R0 ;
2: R1 R0;
3: R0 R1
Microprocessor Ch3-*
LDR R0, [R1, #4] ;R0 ← [R1+4]
2
Microprocessor Ch3-*
LDR R0, [R1, #4] ! ;R0 ← [R1+4]R1 ← R1+4
;
”!”
Microprocessor Ch3-*
BL NEXT ; NEXT
…..
;R2 ← [R0+4]
;R3 ← [R0+8]
;R4 ← [R0+12]
16 ;
IA / (Load/Store) R0 R1 ~ R4
Microprocessor Ch3-*
:
:
:
Microprocessor Ch3-*
ALU ;
ARM ;
Thumb ;
Z
C
4C: (CMN): ()C=1C=0 (CMP): ()C=0C=1 /C /C
V
Q
Microprocessor Ch3-*
(1/2)
PSR 8 ( IFT M[4:0])
I F
T :
T = 0ARM ;
T = 1Thumb
M[4:0]: M0M1M2M3 M4
Microprocessor Ch3-*
(2/2)
0b10010
IRQ
0b10011

0b10111

0b11011

0b11111

Microprocessor Ch3-*
Microprocessor Ch3-*
(1/2)
:
ARM 3:
( Load Store )
IRQ FIQ
:
;
Microprocessor Ch3-*
(2/2)
ARM
(6)
(5)
(2)

IRQ () (4)
(nIRQ) CPSR I 0 IRQ
FIQ () (3)
(nFIQ) CPSR F 0 FIQ
Microprocessor Ch3-*
ARM 32MB 4 :
B: Branch ()
BLX: Branch and Exchange Instruction Set ()
BX: Branch with Link and Exchange Instruction Set ()
Microprocessor Ch3-*
– B
B
B LABEL1 ; LABEL1
CMP R1, #0 ; Z BEQ LABEL1 LABEL1
BCS LABEL2 ; C LABEL2
Microprocessor Ch3-*
– BL
BL
PC B+ – 32MB
LR PC
.
BX <Rm> PC ;
<Rm> <Rm>[0] <Rm>[0] 1 THUMB <Rm>[0] 0 ARM ; <Rm>[31:1] PC
4GB
.
.
LABEL 1: ; LABEL1
BLX
BLX
BLX ARM ARM THUMB PC R14
BLX BX BL 4GB
CODE 32 ; ARM
…
…
SUB1 : ; SUB1
– BLX (2/2)
LR THUMB BL B
PC B : + – 32MB
CODE 32 // ARM
.
.
: CPSR
ANDORNOTXOR
Microprocessor Ch3-*
EOR
0001
SUB
0010
SBC
0110
RSC
0111
TST
1000
TEQ
1001
CMP
1010
CMV
1011
ORR
1100
MOV
1101
BIC
1110
Operand1 AND NOT operand 2 (Bit clear)1 AND NOT2 ()
MVN
1111
Microprocessor Ch3-*
MOV
MOV
MOV S CPSR S CPSR

MOV PC, R14 ; R14 PC
MOV R1, R0, LSL #3 ; R0 3 R1
Microprocessor Ch3-*
MVN
MVN
MVN MOV S CPSR S CPSR

MVN R0, #0 ; 0 R0 R0= – 1
Microprocessor Ch3-*
CMP
CMP


CMP R1, R0 ; R1 R0 CPSR
CMP R1, #100 ; R1 100 CPSR
Microprocessor Ch3-*
CMN
CMN
12

CMN R1, R0 ; R1 R0 CPSR
CMN R1, #100 ; R1 100 CPSR
Microprocessor Ch3-*
TST
TST
12
TST R1, #%1 ; R1 (%)
TST R1, #oxffe ; R1 oxffe AND CPSR
Microprocessor Ch3-*
TEQ
TEQ
12

TEQ R1, R2 ; R1 R2 XOR CPSR
Microprocessor Ch3-*
ADD
ADD
ADD
ADD R0, R2, R3, LSL#1 ; R0 = R2 + (R3 << 1)
Microprocessor Ch3-*
ADC
ADC
ADC CPSR C 32
12
ADCS R1, R5, R9 ;
ADCS R2, R6, R10 ;
ADC R3, R7, R11 ;
Microprocessor Ch3-*
SUB
SUB
SUB 12
SUB R0, R2, R3, LSL#1 ; R0 = R2 – (R3 << 1)
Microprocessor Ch3-*
SBC
SBC
SBC 12 CPSR C 32
12

SUBS R0, R1, R2 ; R0 = R1 – R2 – !C CPSR
Microprocessor Ch3-*
RSB
RSB
RSB 21
12
RSB R0, R2, R3, LSL#1 ; R0 = (R3 << 1) – R2
Microprocessor Ch3-*
RSC
RSC
RSC 21 CPSR C 32
12
:
RSC R0, R1, R2 ; R0 = R2 – R1 – !C CPSR
Microprocessor Ch3-*
AND
AND
12
Microprocessor Ch3-*
ORR
ORR
12
ORR R0, R0, #3 ; R 0 001
Microprocessor Ch3-*
12
Microprocessor Ch3-*
BIC
BIC
BIC 11
12
BIC R0, R0, #%1011 ; R0 013
Microprocessor Ch3-*
MUL: 32
MLA: 32
12 32
MUL R0, R1, R2 ; R0 = R1 × R2
MULS R0, R1, R2 ; R0 = R1 × R2 CPSR
Microprocessor Ch3-*
MUA
MUA
1232
:
MUA R0, R1, R2, R3 ; R0 = R1 × R2 + R3
MUAS R0, R1, R2, R3 ; R0 = R1 × R2 + R3 CPSR
MUL R1, R2, R3 ; R1 = R2 × R3
MLAEQS R1, R2, R3, R4 ; R1 = R2 × R3 + R4 CPSR
Microprocessor Ch3-*
SMULL
SMULL
1232
:
; R1 = (R2 × R3) 32
SMLAL 1232 RdLo RdLo 32 RdHi RdHi CPSR
1232
:
SMLAL R0, R1, R2, R3 ; R0 = (R2 × R3) 32 +R0
; R1 = (R2 × R3) 32 +R1
Microprocessor Ch3-*
UMULL
UMULL
1232
:
; R1 = (R2 × R3) 32
UMLAL 1232 RdLo RdLo 32 RdHi RdHi CPSR
1232
:
UMLAL R0, R1, R2, R3 ; R0 = (R2 × R3) 32 +R0
; R1 = (R2 × R3) 32 +R1
Microprocessor Ch3-*
MRS :

Microprocessor Ch3-*
MSR <>324:
[31:24]: f ;
[23:16]: s ;
[15:8] x ;
[0:7] c ;
MSR
MSR CPSR_c, R0 ; R0 CPSR CPSR
Microprocessor Ch3-*
MSR CPSR_flg, #0xA0000000 ; CPSR[31:28]0xA
(NC; ZV)
Microprocessor Ch3-*
MSR CPSR_flg, #0x50000000 ; CPSR[31:28]0x5
(ZV; NC)
MSR SPSR_flg, #0xC0000000 ; SPSR[31:28]0xC
(NZ; CV)
Microprocessor Ch3-*
/
LDR R0, [R1, R2] ; R1+R2 R0
LDR R0, [R1, #8] ; R1+8 R0
LDR R0, [R1, R2] ! ; R1+R2 R0 R1+R2 R1
LDR R0, [R1, #8] ! ; R1+8 R0 R1+8 R1
LDR R0, [R1], R2 ; R1 R0 R1+R2 R1
LDR R0, [R1, R2, LSL #2] ! ; R1+R2×4 R0 R1+R2×4 R1
LDR R0, [R1], R2, LSL #2 ; R1 R0 R1+R2×4 R1
Microprocessor Ch3-*
STR
STR :

STR R0, [R1, #8] ; R0 R1 R1+8 R1