목 차 - IRS글로벌 · 2017-12-06 · 목 차 3 목 차 Ⅰ. IoT(사물인터넷) 관련산업과 스마트홈 시장동향 ...
목 차
description
Transcript of 목 차
![Page 1: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/1.jpg)
SungKyunKwan Univ.
1VADA Lab.
목 차� 1. HDL 소개 및 설계방법
� 2. 간단한 VHDL Modeling
� 2. 디지털 변복조 방식
� 3. DQPSK CODING TECHNIQUES
� 부록 : ALTERA 설치 및 사용법
![Page 2: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/2.jpg)
SungKyunKwan Univ.
2VADA Lab.
HDL 소개 및 설계방법◈ Why need such HDLs ?
a
M anualdesign
Englishspecification
Register-transferdesign
HDLdescription
Concept
Synthesistools
High- levelsynthesisS c hem atic c apture
and sim ulation
![Page 3: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/3.jpg)
SungKyunKwan Univ.
3VADA Lab.
HDL 소개 및 설계방법 The lack of a formalized description makes the
task of simulation and verification difficult
The lack of documentation during the design process make maintaining and re-targeting the design difficult.
Formalized input can be used for documentation, simulation, verification and synthesis.
The design description also serves as a good exchange medium between different user, as well as between user and design tools.
![Page 4: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/4.jpg)
SungKyunKwan Univ.
4VADA Lab.
HDL 소개 및 설계방법◈ Programming Language Features for HDLs
Data Types• format (e.g., number of bit)
• types (e.g., Boolean, integer, floating point)
• data representation (e.g., signed/unsigned)
Operators and Assignment Statements• arithmetic , Boolean , logic , bit manipulation ,
array access
![Page 5: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/5.jpg)
SungKyunKwan Univ.
5VADA Lab.
HDL 소개 및 설계방법Control Constructs
• if-then-else , case , loop
Execution Ordering• sequential , concurrent
◈ Hardware-Specific HDL Features
Interface Declarations• Port(size, mode)
size (e.g., num-bit), hardware-specific feature (e.g., Whether the port is buffered or tristate), mode (e.g., input, output, input-output)
![Page 6: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/6.jpg)
SungKyunKwan Univ.
6VADA Lab.
HDL 소개 및 설계방법Structural Declarations
• The specification of registers, counter, other H/W structures that are to be used like variables in the
HDL description.
RT and Logic Operators• Bit -level logical operator
bit shifting, bit rotation, bit-stream extraction ….
• RT-level operator increment and decrement operator for variables.
![Page 7: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/7.jpg)
SungKyunKwan Univ.
7VADA Lab.
HDL 소개 및 설계방법Asynchrony
• In addition to synchronous behavior, RT-level hardware typically exhibits asynchronous behavior in the form of set, reset and interrupts.
Hierarchy• As designs get more complex, we naturally resort to
hierarchy as a means of describing, managing and capturing the complex behavior
• Procedural, structural, behavioral and design hierarchy
![Page 8: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/8.jpg)
SungKyunKwan Univ.
8VADA Lab.
HDL 소개 및 설계방법 Interprocess Communication
For purely synchronous designs, this communication can be embedded within the process’behavioral description, since each process operates in a lock-step manner. In such case, the user can explicitly describe the communication using standard HDL constructs to force reads and write
s on correct clock cycle.• Parameter passing
• Message passing
process P1(a,b) in port a; out port b; { ..... }
process P1(x,y) in port x; out port y; { ..... }
Process P1(a,b) in channel a; out channel b; { receive(a,buf) ... send(b,m sg) }
Process P1(a,b) in channel a; out channel b; { receive(a,buf) ... send(b,m sg) }
a b yx
b
a
Parameter passing Message passing
![Page 9: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/9.jpg)
SungKyunKwan Univ.
9VADA Lab.
HDL 소개 및 설계방법Constraints
• Constraints on the design behavior guide the synthesis of the design towards feasible realization in term of performance, cost, testability, reliability, and other physical restrictions.
User allocation and Bindings
◈ HDL Format To support design description and modeling, we need a variety of HDL formats that suit different application and users.
![Page 10: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/10.jpg)
SungKyunKwan Univ.
10VADA Lab.
HDL 소개 및 설계방법 Textual HDLs
• ISPS, Sliage, VHDL, HardwareC, MIMOLA…
Graphical HDLs
Tabular HDLs• Tabular descriptions provide a concise notation for
state-based design description, particularly for FSDMs
Waveform-Based HDLs
![Page 11: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/11.jpg)
SungKyunKwan Univ.
11VADA Lab.
HDL 소개 및 설계방법• Timing diagrams can graphically represent change on signals,
can show sequencing of events, and can also effectively show timing relationships between event.
◈ Matching Language to Target Architecture
Entity Full_Adder is port(X,Y : in bit; CIN : in bit;
SUM : out bit;COUT: out bit);
end Full_Adder;
X Y C IN
SU MC O U T
![Page 12: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/12.jpg)
SungKyunKwan Univ.
12VADA Lab.
HDL 소개 및 설계방법X YX
CIN
SUM
S1S2
S3
COUT
U?
AND2
123
U?
AND2
12
3
U?
XOR2
123
U?
XOR2
123
U?
OR2
12
3
Architecture behave of Full_Adder is
signal S1,S2,S3:bit
begin
S1 <= X xor Y;
SUM <= S1 xor CIN after 3 ns;
S2 <= X and Y;
S3 <= S1 and CIN;
COUT <= S2 or S3 after 5 ns;
end;
![Page 13: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/13.jpg)
SungKyunKwan Univ.
13VADA Lab.
HDL 소개 및 설계방법◈ Modeling Guidelines for HDLs
In order to achieve effcient hardware synthesis, we need to match the model of the language to that of the underlying target architecture.
Combinational Designs• Hardware design is composed of an interconnection of logic gat
es. (Boolean VHDL operators)
Functional Designs
![Page 14: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/14.jpg)
SungKyunKwan Univ.
14VADA Lab.
HDL 소개 및 설계방법• Function designs are characterized by a mixture of synchronous a
nd asynchronous behavior, in which asynchronous event may override synchronous operation.
☞ Illustrate a functional design using an up/down counter with asynchronous set and reset
Register-Transfer Designs• RT designs correspond to the FSMD model.
• RT designs have an implicit notion of states and state transitions
Behavioral Designs• Design behavior is typically expressed in a sequential language st
yle using sequential assignment statement
![Page 15: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/15.jpg)
SungKyunKwan Univ.
15VADA Lab.
◈ 효율적인 모델링 기법대규모 설계를 위해서는 동작적 모델링 .구현을 위해서는 합성 가능한 구문 이용Process 문의 sensitivity list 를 검사 .연산 순서를 조정한 모델링
HDL 소개 및 설계방법
+ + MUX MUX
+MUX
a adcb dbc
out out
![Page 16: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/16.jpg)
SungKyunKwan Univ.
16VADA Lab.
HDL 소개 및 설계방법 연산수행을 줄이는 모델링
++ +
+
a adcb dbc
out
+
+
out
out = a+ b+ c + d out = (a+ b)+ (c + d)
같은 연산은 한번에 수행process(a,b,c,d) process(a,b,c,d)
begin begin
y1 <= a+b; y1 <= a+b;
y2 <= a+b+d; y2 <= y1+d;
y3 <= a+c; y3 <= a+c;
end process; end process;
![Page 17: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/17.jpg)
SungKyunKwan Univ.
17VADA Lab.
HDL 소개 및 설계방법보다 효율적인 문장 선택
☞ 빠른 속도를 필요로 하는 회로에는 case 문보다 if 문이 효율적이다 .
Simulator 에 따라 다른 library 와 package 사용☞ Library 나 각 package 들의 이름 및 형식은 사용
하는 simulator 에 따라 다를 수 있다 .
반도체 회사에서 제공하는 library 를 이용한 합성
관련이 많은 부분을 그룹지어 코딩 및 합성
![Page 18: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/18.jpg)
SungKyunKwan Univ.
18VADA Lab.
• Library ieee;use ieee.std_logic_1164.all;
entity f_adder is port(x,y,c_in : in std_logic; s_out,c_out : out std_logic);end f_adder;
architecture behave of f_adder isbegin
process(x,y,c_in)
variable tmp : std_logic_vector(1 downto 0);
Full_adder 동작적 모델링간단한 VHDL Modeling
![Page 19: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/19.jpg)
SungKyunKwan Univ.
19VADA Lab.
간단한 VHDL Modeling begin
l := “00”;
if x=‘1’ then l := l+1; end if ;
if y=‘1’ then l := l+1; end if ;
if c_in=‘1’ then l := l+1; end if ;
if (l=0) or (l=2) then s_out <= ‘0’
else s_out <= ‘1’;end if;
if (l=0) or (l=1) then c_out <= ‘0’
else c_out <= ‘1’;end if;
end process;
end behave;
![Page 20: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/20.jpg)
SungKyunKwan Univ.
20VADA Lab.
간단한 VHDL ModelingFull_adder 구조적 모델링
HA1 :h_adder
HA2 :h_adder
org :or2
x
y
c _ in
s_out
c _out
f_adder
st1
st3
st2
![Page 21: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/21.jpg)
SungKyunKwan Univ.
21VADA Lab.
• 반가산기 모델링 (Half adder)
Library ieee;use ieee.std_logic_1164.all;
entity h_adder is port(a,b : in std_logic; ☞ s,c : out std_logic);end h_adder;
architecture behave of h_adder isbegin process(a,b) begin
간단한 VHDL Modeling
if (a=b) then s <= ‘0’; else s <= ‘1’;end if;
if (a=‘1’) and (b=‘1’) then c <=‘1’; else c <= ‘1’;end if;
end process;
end behave;
![Page 22: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/22.jpg)
SungKyunKwan Univ.
22VADA Lab.
간단한 VHDL Modeling• OR gate 모델링
Library ieee;use ieee.std_logic_1164.all;
entity or2 is port(a,b : in std_logic; ☞ o : out std_logic);end or2;
architecture behave of or2 isbegin process(a,b) begin
if (a=‘0’) and (b=‘0’) o <=‘0’; else o <= ‘1’;end if;
end process;
end behave;
![Page 23: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/23.jpg)
SungKyunKwan Univ.
23VADA Lab.
간단한 VHDL Modeling• 전가산기 모델링 (Full adder)
Library ieee;use ieee.std_logic_1164.all;
entity f_adder is port(x,y,c_in : in std_logic; ☞
s_out,c_out : out std_logic);end f_adder;
architecture structural of or2 is signal st1,st2,st3 : std_logic;
component or2
port(a,b : in std_logic; o : out std_logic);
end component;
component h_adder
port(a,b : in std_logic;
s,c : out std_logic);
end component;
begin
![Page 24: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/24.jpg)
SungKyunKwan Univ.
24VADA Lab.
간단한 VHDL Modeling HA1 : h_adder
port map(x,y,st1,st2);
HA2 : h_adder
port map(st1,c_in,s_out,st3);
ORG : or2
port map(st2,st3,c_out);
end structural;
![Page 25: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/25.jpg)
SungKyunKwan Univ.
25VADA Lab.
간단한 VHDL ModelingMultiplexer 모델링
y
a
b
sela
sel
y
a
b
0
1
M U X 2X1 S YM B O L M U X 2X1 진 리 표
![Page 26: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/26.jpg)
SungKyunKwan Univ.
26VADA Lab.
간단한 VHDL Modeling• Entity
entity Mux2X1 is port(a,b : in std_logic; sel : in std_logic;
y : out std_logic);end Mux2X1;
![Page 27: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/27.jpg)
SungKyunKwan Univ.
27VADA Lab.
간단한 VHDL Modeling• Architecture 1
Architecture behave of Mux2X1 isbegin process(a,b,sel) begin if sel=‘0’ then y <= a; else y <= b; end if; end process;end behave;
![Page 28: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/28.jpg)
SungKyunKwan Univ.
28VADA Lab.
간단한 VHDL Modeling• Architecture 2
Architecture behave of Mux2X1 isbegin process(a,b,sel) begin case sel is when ‘0’ => y <= a; when others => y<=b; end case; end process;end behave;
![Page 29: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/29.jpg)
SungKyunKwan Univ.
29VADA Lab.
간단한 VHDL Modeling• Architecture 3
Architecture behave of Mux2X1 is signal temp : std_logic;begin process(a,b,sel) begin temp <= not(sel); y <= (a and temp) or (b and sel); end process;end behave;
![Page 30: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/30.jpg)
SungKyunKwan Univ.
30VADA Lab.
간단한 VHDL Modeling 동기 10 진 카운터 modeling
• Library ieee;use ieee.std_logic_1164.all;
entity cnt10 is port(ck,rst : in std_logic; q : buffer std_logic_vector(3 downto 0));end cnt10;
architecture behave of cnt10 isbegin
![Page 31: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/31.jpg)
SungKyunKwan Univ.
31VADA Lab.
간단한 VHDL Modeling process(ck,rst)
begin
if ck’event and ck=‘1’ then
if rst = ‘0’ then q <= “0000”;
elsif q = “1001” then q<= “0000”;
else q <= q+ “0001”;
end if;
end if;
end process;
end behave;
![Page 32: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/32.jpg)
SungKyunKwan Univ.
32VADA Lab.
디지털 변복조 방식
¸ Þ½ÃÁö¿ø½ÅÈ£Àü¼Ûº Πȣ±â
º ¯Á¶±â
Åë½Åä³ Î
° ËÆıâ½ÅÈ£Àü¼Ûº ¹ È£±â
반 송 파
m i S i S i(t)
X(t)X추 정
송 신 기
수 신 기
![Page 33: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/33.jpg)
SungKyunKwan Univ.
33VADA Lab.
디지털 변복조 방식◈ 디지털 통과대역 변조
ASK(Amplitude Shift Keying)
FSK(Frequency Shift Keying)
PSK(Phase Shift Keying)
QAM(Quadrature-Amplitude Modulation)
![Page 34: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/34.jpg)
SungKyunKwan Univ.
34VADA Lab.
디지털 변복조 방식 디 지 탈 열 1 110 0
t
기 저 대 역신 호
양 극 성 T 4T3T2T
ASK
PSK
FSK t
t
t
0
![Page 35: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/35.jpg)
SungKyunKwan Univ.
35VADA Lab.
디지털 변복조 방식◈ PSK(Phase Shift Keying)
디지털 신호의 정보내용에 따라 반송파의 위상 변
화시키는 방식 M 진 PSK(M-ary Phase Shift Keying)
▶ 2 원 디지털 신호를 m 개의 bit 로 묶어서 개의 위상 으로 분할시킨 위상변조방식 .
▶ 2 진 , 4 진 , 8 진 PSK 등이 널리 사용 .
PSK 파는 일정한 진폭을 갖는 파형▶ 전송로 등에 의한 레벨 변동의 영향을 적게 받는다
mM 2
![Page 36: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/36.jpg)
SungKyunKwan Univ.
36VADA Lab.
디지털 변복조 방식
tfAats cii 2cos)(
1 0 110 0
T
◈ 2 진 PSK(Binary Phase Shift Keying) 데이터 ( ) 에 따라 개개의 데이터 구간에 2 종의 위
상을 갖는 정현파 중 하나를 전송하는 방식1
![Page 37: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/37.jpg)
SungKyunKwan Univ.
37VADA Lab.
디지털 변복조 방식
Á÷º ´ · ĺ ¯È̄ ±â
x
x
c os(2fct + o)
s in(2fct + o)
S QP S K(t)
Q ( 2)채 널 양 극 파 형
I ( 1)채 널 양 극 파 형
NR Z 양 극 펄 스
+
-
◈ 4 진 PSK(Quadrature Phase Shift Keying)
![Page 38: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/38.jpg)
SungKyunKwan Univ.
38VADA Lab.
디지털 변복조 방식d I(t)
dQ (t)
+ 1
- 1
+ 1
- 1
d0
d1 d7
d6
d5
d4
d3
d2
2Tb 8Tb6Tb4Tb
2Tb 4Tb 6Tb 8Tb
s(t)
2Tb 4Tb 6Tb 8Tb
![Page 39: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/39.jpg)
SungKyunKwan Univ.
39VADA Lab.
디지털 변복조 방식◈ 차동 PSK(Differential Phase Shift Keying)
동기검파용 기준반송파가 필요없다
1 구간 (T 초 ) 전의 PSK 신호를 기준파로 사용하여 동기검파하는 방식 .
전후의 신호구간 사이의 위상차가 정보에 대응하도록 송신측에서 PSK 변조하기 전에 차동부호화 (Differential Encoding) 할 필요가 있다 ..
![Page 40: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/40.jpg)
SungKyunKwan Univ.
40VADA Lab.
디지털 변복조 방식◈ 차동 PSK 송신기
Differentialencoder
x
x
c os(2fct + o)
s in(2fct + o)
S DQ P S K(t)
Q ( 2)채 널 양 극 파 형
I ( 1)채 널 양 극 파 형
NR Z 양 극 펄 스
+
-Á÷º ´ · ĺ ¯
È̄ ±â
![Page 41: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/41.jpg)
SungKyunKwan Univ.
41VADA Lab.
DQPSK CODING TECHNIQUES
Serial-to-Parallel(S_TO_P.vhd)
Parallel-to-SerialDQPSKDecoder
DQPSKEncoder
(enc.vhd)
denc .vhd
![Page 42: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/42.jpg)
SungKyunKwan Univ.
42VADA Lab.
DQPSK CODING TECHNIQUES
![Page 43: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/43.jpg)
SungKyunKwan Univ.
43VADA Lab.
DQPSK ENCODER 구조적 모델링
STP :S_TO_P
(s_to_p.vhd)
EN :enc
(enc.vhd)
st1
st2
denc .vhd
oupd_ in
DQPSK CODING TECHNIQUES
![Page 44: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/44.jpg)
SungKyunKwan Univ.
44VADA Lab.
• 직병렬변환기 모델링Library ieee;use ieee.std_logic_1164.all;
entity s_to_p is port(reset,tx_in : in std_logic; ☞ bclk,sclk : in std_logic; I_ch,q_ch : out std_logic);end s_to_p;
architecture behave of s_to_p is signal tmp : std_logic; begin process(reset,tx_in,bclk)
DQPSK CODING TECHNIQUES
begin
if reset=‘0’ then tmp <= ‘0’;
elsif bclk’even and bclk=‘0’ then
tmp <= tx_in;
end if;
process(reset, TMP, tx_in, sclk)
begin
if reset = '0’ then
i_ch <= '0';
![Page 45: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/45.jpg)
SungKyunKwan Univ.
45VADA Lab.
DQPSK CODING TECHNIQUES q_ch <= '0';
elsif sclk'event and sclk = '0' then
i_ch <= TMP;
q_ch <= tx_in;
end if;
end process;
end behave;
![Page 46: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/46.jpg)
SungKyunKwan Univ.
46VADA Lab.
• 직병렬변환기 Simulation 결과
DQPSK CODING TECHNIQUES
![Page 47: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/47.jpg)
SungKyunKwan Univ.
47VADA Lab.
DQPSK CODING TECHNIQUES• ENCODER 모델링
Library ieee;use IEEE.std_logic_1164.ALL;
entity enc is port (rst, i_in, q_in : in std_logic; sclk : in std_logic;
d_out : out std_logic_vector(1 downto 0));end enc;
architecture behave of enc is signal C_STATE, N_STATE : std_logic_vector(1 downto 0); signal IQ_IN : std_logic_vector(1 downto 0);
![Page 48: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/48.jpg)
SungKyunKwan Univ.
48VADA Lab.
DQPSK CODING TECHNIQUES begin
IQ_IN <= i_in & q_in;
process(rst,sclk,IQ_IN) begin if rst = '0' then C_STATE <= "00"; elsif sclk'event and sclk = '0’ then case C_STATE is
when "00" => case IQ_IN is
when "00" => N_STATE <= "00";when "01" => N_STATE <= "01";when "10" => N_STATE <= "10";when "11" => N_STATE <= "11";when others =>
![Page 49: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/49.jpg)
SungKyunKwan Univ.
49VADA Lab.
DQPSK CODING TECHNIQUES end case;
when "01" => case IQ_IN is when "00" => N_STATE <= "01"; when "01" => N_STATE <= "11";
when "10" => N_STATE <= "00"; when "11" => N_STATE <= "10"; when others => end case;
when "10” => case IQ_IN is when "00" => N_STATE <= "10"; when "01" => N_STATE <= "00";
when "10" => N_STATE <= "11"; when "11" => N_STATE <= "01";
when others =>
![Page 50: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/50.jpg)
SungKyunKwan Univ.
50VADA Lab.
DQPSK CODING TECHNIQUES end case; when "11" =>
case IQ_IN is when "00" => N_STATE <= "11"; when "01" => N_STATE <= "10"; when "10" => N_STATE <= "01"; when "11" => N_STATE <= "00"; when others =>
end case; when others => end case; end if; end process;
![Page 51: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/51.jpg)
SungKyunKwan Univ.
51VADA Lab.
DQPSK CODING TECHNIQUES process(rst,sclk,N_STATE)
begin if rst='0' then N_STATE <= "00"; elsif sclk'event and sclk='1' then C_STATE <= N_STATE; d_out <= N_STATE; end if; end process;end behave;
![Page 52: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/52.jpg)
SungKyunKwan Univ.
52VADA Lab.
• ENCODER Simulation 결과
DQPSK CODING TECHNIQUES
![Page 53: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/53.jpg)
SungKyunKwan Univ.
53VADA Lab.
DQPSK CODING TECHNIQUES• DQPSK ENCODER 모델링
library ieee;use ieee.std_logic_1164.all;
entity denc is port(fck,hck : in std_logic; clr : in std_logic; d_in : in std_logic; oup : out std_logic_vector(1 downto 0)); end denc;
architecture behave of denc is
![Page 54: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/54.jpg)
SungKyunKwan Univ.
54VADA Lab.
DQPSK CODING TECHNIQUESsignal st1,st2 : std_logic; component S_TO_P
port ( reset, tx_in : in std_logic; bclk, sclk : in std_logic; i_ch, q_ch : out std_logic);
end component; component ENC
port (rst, i_in, q_in : in std_logic; sclk : in std_logic; d_out : out std_logic_vector(1 downto 0));
end component;
![Page 55: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/55.jpg)
SungKyunKwan Univ.
55VADA Lab.
DQPSK CODING TECHNIQUESbegin
STP : s_to_p port map(clr,d_in,hck,fck,st1,st2); EN : ENC port map(clr,st1,st2,fck,oup);
end behave;
![Page 56: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/56.jpg)
SungKyunKwan Univ.
56VADA Lab.
• DQPSK ENCODER Simulation 결과
DQPSK CODING TECHNIQUES
![Page 57: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/57.jpg)
SungKyunKwan Univ.
57VADA Lab.
ALTERA 설치 및 사용법◈ 시스템 요구사항
486DX66 or Pentium 계열 이상 . MS Windows NT 3.51 or MS Windows95 환경 . MS Windows 에서 사용 가능한 그래픽 카드와
모니터 . CD-ROM 드라이버 . Parallel port32MB RAM(Device 에 따라 다름 )
![Page 58: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/58.jpg)
SungKyunKwan Univ.
58VADA Lab.
◈ SOFTWARE INSTALL
ALTERA 설치 및 사용법
![Page 59: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/59.jpg)
SungKyunKwan Univ.
59VADA Lab.
ALTERA 설치 및 사용법
![Page 60: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/60.jpg)
SungKyunKwan Univ.
60VADA Lab.
ALTERA 설치 및 사용법◈ 디지털 시스템의 설계방법
회로도에 의한 방법 .
VHDL 에 의한 방법 .
![Page 61: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/61.jpg)
SungKyunKwan Univ.
61VADA Lab.
ALTERA 설치 및 사용법M AX+ P LU U S II start
( .G DF )새 로 운 디 자 인 을 만 든 다
node bus 심 볼 을 입 력 하 고 와 를 이 용 하 여 회 로 도 완 성
pro jec t 회 로 도 저 장 후 이 름 설 정
P ro jec t compile
E RRO R
Timing analys is
S imulation
동 작 정 상
M AX+ P LU U S II E nd
No
No
Yes
Yes
M AX+ P LU U S II start
( .vhd)새 로 운 디 자 인 을 만 든 다
VHDL 회 로 의 동 작 을 문 법 에 맞 게 기 술
F ile pro jec t 저 장 후 이 름 을 설 정
P ro jec t compile
E RRO R
Timing analys is
S imulation
동 작 정 상
M AX+ P LU U S II E nd
No
No
Yes
Yes
![Page 62: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/62.jpg)
SungKyunKwan Univ.
62VADA Lab.
ALTERA 설치 및 사용법Design E ntry
MAX+PLUSIIText Editor
MAX+PLUSIISym bol Editor
MAX+PLUSIIGraphic Editor
MAX+PLUSIIFloorplan Editor
MAX+PLUSIIW aveform Editor
Com piler NetlistExtractor(includesall netlis t readers)
ED IF , VHDL &Verilog Netlis t
W riters
Functional, T im ing ,or L inked SNF
Extractor
DatabaseBuilder
DesignDoctor
Partitioner
LogicSynthesizer
Assem bler
F itter
Pro jec t P roc essing
Pro jec t Verific ation
MAX+PLUSIISim ulator
MAX+PLUSIITim ing Analyzer
MAX+PLUSIIW aveform Editor
Devic e program m ing
MAX+PLUSIIProgram m er
MAX+PLUSIIMessage Processor
&Hierarchy Display
![Page 63: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/63.jpg)
SungKyunKwan Univ.
63VADA Lab.
ALTERA 설치 및 사용법◈ Graphic Design File 의 생성
① 새로운 File 이름을 만든다 .
② Project name 을 정한다 .
③ Logic 함수에 대한 symbol 을 입력한다 .
④ Symbol 을 원하는 위치로 이동한다 .
![Page 64: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/64.jpg)
SungKyunKwan Univ.
64VADA Lab.
ALTERA 설치 및 사용법
⑤ Input pin & output pin 을 입력한다 .
⑥ 해당 pin 에 대한 이름을 입력한다 .
⑦ Node 와 bus 들을 연결한다 .
⑧ File 을 저장한 후 기본적인 error check
![Page 65: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/65.jpg)
SungKyunKwan Univ.
65VADA Lab.
ALTERA 설치 및 사용법
![Page 66: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/66.jpg)
SungKyunKwan Univ.
66VADA Lab.
ALTERA 설치 및 사용법☜ Symbol Libraries 에는 매우 많은
종류의 TTL 과 특히 , 74XXX serise 와 다수의 Mega Function Libraries 가 준비되어 있고 또 자신이 VHDL 이나 AHDL 로 설계한 Function 을 Symbol 로 만들면 Symbol Libraries Box 에 포함되어 Symbol
Files box 에 나타난다 .
![Page 67: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/67.jpg)
SungKyunKwan Univ.
67VADA Lab.
ALTERA 설치 및 사용법
![Page 68: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/68.jpg)
SungKyunKwan Univ.
68VADA Lab.
ALTERA 설치 및 사용법
☜ 지금까지는 입출력 각각의 port 가 실제 ALTERA CPLD 의 몇 번에 할당되는지의 정보는 없다 . 이를 위해 다음과 같이 각각의 입출력 pin 에 대한 pin 번호를 할당하기 위하여 이 메뉴를 이용한다 .
![Page 69: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/69.jpg)
SungKyunKwan Univ.
69VADA Lab.
ALTERA 설치 및 사용법
☜ 본 설계에서는 “ test” 가 Chip 의 name 이고 “ @” 우측에 표시된 것이 실제 CPLD 에 연결된 pin 번호이다 .
![Page 70: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/70.jpg)
SungKyunKwan Univ.
70VADA Lab.
ALTERA 설치 및 사용법◈ 컴파일을 통한 Design 상태 점검
컴파일러는 일련의 Module 과 Utility 로 구성
project 에 대한 Error 검출
Logic synthesize 하여 ALTERA Chip 으로 Fitting.
![Page 71: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/71.jpg)
SungKyunKwan Univ.
71VADA Lab.
ALTERA 설치 및 사용법
![Page 72: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/72.jpg)
SungKyunKwan Univ.
72VADA Lab.
ALTERA 설치 및 사용법◈ Simulation 을 통한 Logic 검증
![Page 73: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/73.jpg)
SungKyunKwan Univ.
73VADA Lab.
ALTERA 설치 및 사용법
![Page 74: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/74.jpg)
SungKyunKwan Univ.
74VADA Lab.
ALTERA 설치 및 사용법
![Page 75: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/75.jpg)
SungKyunKwan Univ.
75VADA Lab.
ALTERA 설치 및 사용법◈ Timing 분석
![Page 76: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/76.jpg)
SungKyunKwan Univ.
76VADA Lab.
ALTERA 설치 및 사용법☜ Delay Matrix
KEY_7 로 부터 Led1 출 력까지 14.8ns 지연이 일 어남 .
![Page 77: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/77.jpg)
SungKyunKwan Univ.
77VADA Lab.
ALTERA 설치 및 사용법◈ VHDL 기술을 위한 Text file 의 생성
![Page 78: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/78.jpg)
SungKyunKwan Univ.
78VADA Lab.
ALTERA 설치 및 사용법
![Page 79: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/79.jpg)
SungKyunKwan Univ.
79VADA Lab.
ALTERA 설치 및 사용법
![Page 80: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/80.jpg)
SungKyunKwan Univ.
80VADA Lab.
ALTERA 설치 및 사용법• library IEEE;
use IEEE.std_logic_1164.ALL;entity S_TO_P is port ( reset, tx_in : in std_logic;
bclk, sclk : in std_logic; i_ch, q_ch : out std_logic);
end S_TO_P;
architecture RTL of S_TO_P is signal TMP : std_logic;begin process (reset, tx_in, bclk) begin if reset = '0’ then TMP <= '0'; elsif bclk'event and bclk = '0' then TMP <= tx_in; end if; end process;
process(reset, TMP, tx_in, sclk)
begin
if reset = '0’ theni_ch <= '0';q_ch <= '0';
elsif sclk'event and sclk = '0’ theni_ch <= TMP;q_ch <= tx_in;
end if;
end process;
end RTL;
![Page 81: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/81.jpg)
SungKyunKwan Univ.
81VADA Lab.
ALTERA 설치 및 사용법
![Page 82: 목 차](https://reader035.fdocument.pub/reader035/viewer/2022062222/568150ee550346895dbf0894/html5/thumbnails/82.jpg)
SungKyunKwan Univ.
82VADA Lab.
참고문헌 VHDL 기초와 응용
– 이대영 , 조원경 , 정연모 , 오재곤 공저– 홍릉과학출판사
디지털시스템 설계 및 응용– 양오 저– 복두출판사
아날로그와 디지탈통신– 진년강 저– 청문각
전자통신– 강창언 저– 복두출판사