12. Memory Organization

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1128 x 8128 x 8128 x 8128 x 8512 x 8

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1Content Addressable Memory

1010

110

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1If K1 = 0A1 Fi1 OR gate = 1

If K2 = 1A1 Fi1 (A1= 1) (Fi1=1) (A1=0) (Fi1=0) OR gate = 1

OR gate = 00 1 1 0 1 11 0 1 0 1 01 1 0

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1Cache Memory System

Direct Mapped : Set Associative : Set Fully Associative :

Where can a block be placed in the upper level? Fully Associative Direct Mapped2-way Set Associative

#Memory blocks = 32#cache blocks = 8

Where can the Memory Block 12be placed ?

Direct MappedCache block no = Memory Block no % #cache blocks

S.A. MappingSet Number= Memory Block Number % #Sets

2-way Set Associative: 0 = 12%4

Alpha AXP 21064 Data Cache Index = 8 bits: 256 blocks = 8192/(32x1) According to the request of CPU, the cache responds whether hit or miss. When hit, CPU continues the operation; when miss, CPU requests MM.DirectMapped

Figure 5.5(2nd Ed)

Indicating whether ornotthe next sequential4 bytes areoccupiedin this entry32-byteblock

If =, then 8 Bytes go into CPU (R) or 8 Bytes go into cache (W)If , then 8 Bytes comefrom the lowermemory (R) or8 Bytes go into write buffer (W)25 = 32 Bytes8 Bytes28 = 256 blocks

2-way Set Associative Two sets ofAddress tagsand data RAMby using2 x 1 MUX

32 Bytes29 = 512 blocks26 = 64 Bytes

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TagIndex Address

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Block number

Word number

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TagIndex Address

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164 bits30 bits

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