Post on 13-Mar-2018
Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Tools and Solutions
for Porting, Analysis, Modeling & Sizing
of Nanometer IC Designs
V5 2012 1
Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
MunEDA Corporate Overview
EDA Software Vendor – Design Tool Suite WiCkeDTM
for Porting, Analysis, Modeling & Sizing of Nanometer IC designs
Founded in 2001 - Headquarters in Munich Germany
Worldwide Sales & Support Offices in USA, Korea, China, Taiwan,
Japan, UK, Ireland, Scandinavia, South America
Worldwide Customer Base of Semiconductor IDMs,
Fabless Design Houses & Foundries
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Improve Design Performance & Yield
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Your Circuit Designs and Design Challenges
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Custom Digital • High-Speed I/O
• Memory Interfaces
• SRAM
• FPGA Core
Custom Analog / RF • Low Power Analog
• RF Transceiver
• Equalizer
• PLL / VCO
• DC-DC Converter
Standard Cell & I/O Lib • Latches, Flip-Flop
• Levelshifter
• Clock Buffers
• Logic
Your Circuit Designs
Discover MunEDA solutions for circuit design
porting, analysis, modeling and optimization
You design in nanometer process technologies such
as 90nm, 65nm, 40nm, 28nm, 20nm, 14nm and below
– facing mismatch, device noise, parasitics and layout-
dependent effects
Your key design tasks are
– design migration between process technologies
– high-sigma variation analysis and circuit verification
– circuit sizing and optimization (pre- and post-layout)
Your designs require a large amount of SPICE
simulation runs especially for sizing and verification
You are working in a customized design environment
using different SPICE simulators.
Your Design Challenges
Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Focus of MunEDA Solutions – Nanometer Process Technologies
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180nm 130nm 90nm 40nm 20nm
Growing demand
Growing demand
Standard Cell
Flash Memory
Full Custom Digital,
FPGA
Linear Low Power
Analog SRAM, DRAM
I/O
RF Application Fields
Advanced statistical analysis and
verification – for high sigma
Impact of process variation and mismatch
grows with advanced technology nodes
technology node
Circuit optimization for performance,
power, area, yield
High performance / high speed / low power
design in advanced technology nodes
Improve Design Performance & Yield
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Motivation to use MunEDA WiCkeD & SPT for Nanometer Designs
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Most nanometer ICs contain critical parts that
are created in a full-custom design style:
MunEDA WiCkeDTM and SPT provides advanced tools for migration,
analysis, modeling and sizing of full-custom IC designs and libraries
Full-custom blocks are critical for
• design time,
• key performance metrics,
• and yield
Full-custom designers spend
a lot of time
• analyzing
• optimizing their designs
Standard Custom IC tool suites provide
• mature tools for design entry, layout, and simulation,
• but contain only basic tools for further analysis and optimization
Improve Design Performance & Yield
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MunEDA WiCkeDTM Circuit Design & Sizing Environment
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design tools fully integrated in standard
IC design flows solve nanometer design challenges
Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Circuit & Schematic
Porting
Circuit Analysis &
Verification
Circuit Modelling
Circuit Sizing &
Optimization
MunEDA WiCkeDTM - Best-in-class Design Tools for Nanometer Designs
WiCkeDTM Tools Designer‘s Targets
Quickly and efficiently port and migrate
schematics & IP between process
technologies
Analyze, check and verify circuits
intensively for different targets like:
- Device & process sensitivities
- Performances meeting specifications
- Variation analysis
- High-Sigma & Yield analysis
- Mismatch detection
- Worst-Case process corners
- Worst-Case environmental corners
- Interactive sizing of your circuits
- And many more
Generate Verilog and VHDL models from
circuits to check circuit behavior at
system level
Use WiCkeDTM automated optimizers to
- Fulfill circuit constraints
- Improve performances to meet specifications
- Find local and global optimum of circuits
- Optimize circuit for highest sigma yield
MunEDA WiCkeDTM - Best-in-class Design Tools for Nanometer Design Porting,
Analysis, Modeling and Optimization – The most complete solution in industry!
• SPT – Schematic Porting Tool
• BAS Basic & Sensitivity
• CED Constraint Editor
• NOD Nominal Diagnosis
• SCG Parameter Screening
• WCO Worst Case Operation
• FEO Feasibility Optimization
• DNO Deterministic Nominal Opt.
• GNO Global Nominal Opt.
• YOP Yield Optimization
• RSM Circuit Model Generation
Nominal
Statistical • CRN Corner Run Analysis
• MCA Monte Carlo Analysis
• WCA Worst Case Analysis
• WCD Worst Case Diagnosis
• MMA Mismatch Analysis
Nominal & Statistical
Improve Design Performance & Yield
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Full-Custom Design Tools – GUI- & Script-based
MunEDA solutions available in
- Full GUI mode for GUI-based design environments
- Script-based for batch-mode design environments
Improve Design Performance & Yield
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System to IC Specification
Sign-off
Schematic Capture
Block Layout DRC/LVS
RCLk Parasitic Extraction
and Re-Simulation
Top-Level Closed-Loop
Integration & Verification
Circuit Simulation
Circuit Design Analysis
Sizing & Verification
MunEDA WiCkeD & SPT - filling gaps in existing custom circuit design flows
Circuit Porting & Migration
Sizing & Optimization of
Extracted View Netlists
MunEDA SPT Schematic Porting Tool
MunEDA
WiCkeD™
Design &
Sizing
Environment
Sensitivity
Analysis
Performance
Tuning
Design
Centering
Documentation
& Sign-off
Design
Verification
Improve Design Performance & Yield
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MunEDA WiCkeD integrated into Major Design & Simulation Environments
Cadence® Virtuoso® Analog Design Environment
Synopsys Galaxy Custom Designer®
Starting WiCkeDTM from …
Mentor Graphics IC Station® Schematics
WiCkeDTM SPICE & FastSPICE
Simulator Support…
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Synopsys
- HSPICE
- CustomSIM (HSIM, XA, NanoSIM)
- Magma-FineSim
Cadence
- Spectre / SpectreRF
- UltraSIM
- APS
Mentor Graphics
- Eldo / EldoRF
- AdiT
- QuestaADMS
Berkeley Design Automation
- AFS AnalogFastSpice
Agilent
- GoldenGate
Empyrean/ICScape
- Aeolus
Improve Design Performance & Yield
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Designer‘s Benefits of MunEDA WiCkeD Key Solutions
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Automate transistor sizing (e.g. W, L) to optimize nanometer
IC design specifications with speed-ups up to 90% and more
Take 5-10x advantage from highly advanced Monte Carlo Analysis
features compared to simulator build-in methods
Reduce simulation effort and increase reliability by factors 10-100x for
high sigma analysis with MunEDA Worst Case Distance methods
Accelerate and automated design schematic migration
between different process technologies by factors 50-100x
Generate arithmetic models of performance vs. circuit parameters
for system level verification
Highly benefit from MunEDA WiCkeD enhanced capabilities to
support your porting, design & sizing process
Improve Design Performance & Yield
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and more… for WiCkeDTM customer references see http://www.muneda.com/Customers
Selection of MunEDA Worldwide Customers
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Improve Design Performance & Yield
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MunEDA Tools Overview
Improve Design Performance & Yield
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Circuit & Schematic
Porting
Quickly and efficiently port and migrate
your schematics & IP between different
process technologies
Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
MunEDA WiCkeD & SPT supports a Full-Custom IP Porting and Re-Sizing Workflow
The generalized design flow follows 3 major steps
1. Schematic Porting or IP Re-use
2. Design Assessment (Analysis & Verification)
3. Sizing & Sign-off (Circuit Optimization: Sizing and Design Centering)
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Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Challenges of IP Porting & IP Migration
Migrating AMS/RF IP is a challenge
– Many blocks (whole SoC) must be migrated in a short time.
– There’s no simple rule for shrinking AMS/RF, I/O and full-custom digital. Every
block needs adjustment of geometries, biasing, … even if specs don’t change.
– The circuit topology may need modification to the new process, Vdd, new specs
– W, L shrinking is desirable, but not as simple as digital
– Some devices (mimcaps, inductors, …) may or may not be available in the target
PDK, or only of a quite different type
Circuit & Schematic
Porting
Specification-driven IP porting
has to
– migrate the schematic to the new PDK
– then adjust topology and geometries
to meet specs
– then recreate the layout
Improve Design Performance & Yield
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MunEDA SPT performs automatic & fast schematic migration
– replaces devices in the schematic with their counterparts
– source PDK target PDK
Benefits
Correct and repeatable replacement of instances guarantees database consistency.
Fast: Migrates 1000s of devices in seconds, hierarchically.
Flexible property mapping, configurable, automated shrinking, can handle MOS, R, C, inductors, varactors, …
Generates conversion report: Shows every mapped instance, selected properties and values
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Circuit & Schematic
Porting
Tools of WiCkeD — Circuit & Schematic Porting - SPT Schematic Porting
Improve Design Performance & Yield
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Tools of WiCkeD — Circuit & Schematic Porting - SPT Schematic Porting
Fully integrated into Cadence® Virtuoso® based unified
custom/analog flow including SKILL context files, wrapper scripts and
configuration scripts
Configurable for many source/target process technologies
Configurations available from MunEDA for major foundry process technologies
(e.g. TSMC, GLOBALFOUNDRIES, X-Fab, STMicroelectronics, Samsung Foundry,
AMS, UMC, TowerJazz and others). Please ask us for further process
technologies being already supported
Includes user reference documentation for installation, configuration and usage
Picture: MunEDA SPT Schematic Porting Menu
Item in Virtuoso® Library Manager
Picture: Example Cell Mapping Table (Porting
from TSMC 65nm to TSMC 40nm)
Copyright by MunEDA GmbH. WiCkeDTM is a trademark of MunEDA GmbH. Cadence® and Virtuoso®, are registered trademarks of Cadence Design Systems Inc. All other are trademarks and registered trademarks of their specific owners. For more information
see www.muneda.com
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Circuit & Schematic
Porting
Improve Design Performance & Yield
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Circuit Analysis &
Verification
• CRN Corner Run Analysis
• MCA Monte Carlo Analysis
• WCA Worst Case Analysis
• WCD Worst Case Diagnosis
• MMA Mismatch Analysis
• CED Constraint Editor
• BAS Basic & Sensitivity
• NOD Nominal Diagnosis
• SCG Parameter Screening
• WCO Worst Case Operation
Analyse, check and verify your
circuits intensively for different
design targets
Improve Design Performance & Yield
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Saves all analysis and sizing results
Step-by-step documented sizing
Good for review and documentation
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Tools of WiCkeD - Analysis & Verification – WiCkeD BAS Design History Circuit
Analysis & Verification
Sensitivity calculation
– for all kinds of analyses (transient, RF, …)
– and simulators (XA, Hspice, Finesim,
Goldengate, AFS, Spectre, …)
Sensitivity to geometries, process,
operating condition, mismatch
Sweeps including constraint violation
markers
WiCkeD - BAS Design History
WiCkeD BAS Sensitivity Analysis
Improve Design Performance & Yield
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Tools of WiCkeD — Analysis & Verification – CED Constraint Editor
Automated constraint generation & structure recognition
Including electrical constraints and geometric matching
Automated parameterization from schematic and/or netlist
Automated process corners and statistics setup
Complex, configurable topologies
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Circuit Analysis &
Verification
Improve Design Performance & Yield
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Tools of WiCkeD – Analysis & Verification — NOD Nominal Diagnosis
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Circuit Analysis &
Verification
Fast what-if analysis based on sensitivities
Performance dependency charts
Interactive performance improvements
Improve Design Performance & Yield
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Tools of WiCkeD – Analysis & Verification – SCG Parameter Screening
Reduce the parameter space to the relevant subset
Eases interactive analysis
Significantly reduces simulation effort
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Circuit Analysis &
Verification
Improve Design Performance & Yield
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Tools of WiCkeD – Analysis & Verfication – WCO Worst-Case Operation
Find worst-case operating condition & corner
Includes structural constraints
Can handle non-linear dependency (=worst-case not in
the corner)
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Circuit Analysis &
Verification
Improve Design Performance & Yield
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Tools of WiCkeD- Analysis & Verification — CRN Corner Run Analysis
Check all corners, show corner overview and summary
Distributed simulation in a network of hosts
25
Circuit Analysis &
Verification
Improve Design Performance & Yield
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Tools of WiCkeD – Analysis & Verification — MCA Monte Carlo & Yield Analysis
Monte Carlo Analysis
Contribution Analysis
High-Sigma & Yield Analysis
Total Yield calculation with accuracy
figures (95% confidence intervals)
Safe speed-up (LHS)
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Circuit Analysis &
Verification
Dynamic calculation of worst-case
operating
conditions to save simulation runs
Truly distributed simulation for larger
circuits
Including structural constraints
Supports many simulators and
simulation types (e.g. pss-sweep)
Improve Design Performance & Yield
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Tools of WiCkeD – Analysis & Verification — MCA Scatter Plot, Histogram & Correlation
Interactively pick samples,
e.g. outliers
Show waveforms for any
operating condition & corner
Save sample data for
external processing
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Circuit Analysis &
Verification
Robust parameter sensitivities
Detect sensitive devices (local variation)
Detect critical process parameters
Significance level calculated
Special speed-up methods to save
runs for large #parameters (>500)
Improve Design Performance & Yield
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Tools of WiCkeD – Analysis & Verification — MCA Monte Carlo Analysis
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Circuit Analysis &
Verification
MunEDA MCA Monte-Carlo Analysis highly advanced
compared to existing Monte Carlo Solutions
Conventional Monte Carlo
Benefits and Advanced Solutions with
MunEDA WiCkeD MCA Monte Carlo
Analysis
Run MCA at all corners +++ (optional) dynamic calculation of worst -
case operating conditions to save simulation
runs
Distribute only complete
batch
+++ Truly distributed simulation for larger
circuits
Only user - defined specs +++ Specs + structural constraints
Only selected simulators and
simulation types
+++ Supports many simulators (e.g. Hsim , XA)
and simulation types (e.g. pss - sweep)
No correlation between
testbenches
+++ Define “Physical Identical Devices” to
calculate correct correlation between
testbenches
Improve Design Performance & Yield
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Tools of WiCkeD – Analysis & Verification — WCA Worst-Case Analysis
Calculates worst-case points
Calculated worst-case
distance in sigmas
Low effort high-sigma yield
analysis, particularly for
SRAM and latches
Robustness measure for
any analog performance
Generates worst-case
netlists for sub-blocks
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Circuit Analysis &
Verification
WCA Worst-Case Analysis is factor 10-100 more efficient
than traditional Monte-Carlo Methods
Improve Design Performance & Yield
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random2
(e.g. M2Vth)
1σ
6σ 3σ
Worst-Case
Point
random1 (e.g. M1Vth)
Tools of WiCkeD — Analysis & Verification – WCA Worst-Case & Yield Analysis
WCA
Worst Case Analysis
Worst-case Point:
The parameter
combination with
worst performance
within an x-sigma
distance
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Circuit Analysis &
Verification
Improve Design Performance & Yield
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Tools of WiCkeD – Analysis & Verification — WCD Worst-Case Diagnosis
WCD Worst-Case Diagnosis is
useful for:
– Manual adjustment of a design with
consideration of process variations, i.e.
a manual design centering.
– Benefits of Worst-Case Analysis results • High-Sigma variation analysis
• Specification driven design
• Parametric Yield Analysis
• Interactive Yield Improvement
• Contributor Diagnosis
• Worst Case Distance Algorithms
• Design Parameter Influence
31
Circuit Analysis &
Verification
Improve Design Performance & Yield
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Tools of WiCkeD – Analysis & Verification — MMA Mismatch Analysis
WiCkeD MMA Mismatch Analysis identifies and analyses mismatch-
relevant transistor pairs on selected circuit performances.
The variance of these local variations will be
analyzed based on dependencies
of device pair geometries.
– Mismatch pair detection
– Analysis of matching constraints
– Local process variations influence
– Information for yield optimization
– Fast deterministic algorithms
– Performances by mismatch effects
32
Circuit Analysis &
Verification
Improve Design Performance & Yield
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Customer Example - Advanced Circuit Analysis & Verification with MunEDA WiCkeD STMicroelectronics – Process variation impact analysis on huge circuits with Synopsys CustomSim XA and WiCkeD
Circuits analysed:
(1) High-Speed Clock Generator 65nm
• 60K MOS transistors, 195K devices incl. parasitics
• Simulation time: 9h (SPICE) 10min (XA)
• Task: Statistical verification of trimming algorithm
(2) Matrix of Sense Amplifiers 90nm NVM memory
• 105K MOS transistors, 210K devices incl. parasitics
• Simulation time: 1h (SPICE) 3-5 min (XA)
• Task: Statistical verification
Solution :
Using CustomSim XA FastSpice with WiCkeD
• Couple WiCkeD MCA with CustomSim XA for fast distributed
Monte Carlo simulation of large analog circuits
• Use WiCkeD MCA Data export to validate statistical simulation
with XA against SPICE.
Results published by
STMicroelectronics at MUGM 2010
WiCkeD Monte-Carlo confirms predefined corner results using CustomSim XA
Very good agreement in reliability of max & min values of distribution
Dramatic Speed-up in simulation and statistical assureness:
– High-Speed Oscillator: 55x
– Matrix of Sense Amplifiers: Simulation Speed-up: 20x
Improve Design Performance & Yield
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Customer Example - Advanced Circuit Analysis & Verification with MunEDA WiCkeD Altera– FPGA CRAM cell analysis for 6.5sigma
Circuit:
– memory cell for FPGA
– 40nm TSMC
– cell is repeated >100M times in Stratix IV
Problem Description: Verify High-Sigma
(6,5) Analysis for Global Statistics and
Mismatch
Solution
– WiCkeD Sensitivity
Analysis to detect relative
influences of design,
process and operating
parameters
– Run WiCkeD Worst Case
Analysis to determine
6.5 worst-case condition
– Create worst-case cell
from WiCkeD for system-
level simulation
Stratix IV GX
40-nm FPGA
Results published by Altera at MUGM 2010
„Since 65nm, Altera has used WiCkeD tools to analyse and optimize design
performance and yield of analog and digital circuits“, Richard Saito, Altera
34
Circuit Analysis &
Verification
Improve Design Performance & Yield
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Circuit Modelling
Response Surface Modeling
& Model Generation
Improve Design Performance & Yield
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Tools of WiCkeD – Modelling — RSM Opamp Verilog Model
parameter real
. . .
analog begin
. . .
ω1=-first_pole*`M_TWO_PI;
ω2=-second_pole*`M_TWO_PI;
V(OUTP,AVSS) <+ -vin*`dB2dec(gain)+
ddt((1/ω1+1/ω2)*V(OUTP,AVSS)-(1/(ω1*ω2))*ddt(V(OUTP,AVSS)));
. . .
end
first_pole = first_pole_calc(T,VDD);
second_pole =
second_pole_calc(T,VDD);
gain = gain_calc(T,VDD);
first_pole = 1.079k from (0:inf);
second_pole = 265M from (0:inf);
gain = 75;
Constant model Variable model after WiCkeD RSM
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Circuit Modelling
Improve Design Performance & Yield
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Tools of WiCkeD – Modeling — RSM Response Surface Modeling
Generates arithmetic models of performances vs.
circuit parameters,
process variation, operating conditions or local
variation
Speeds up repetitive sizing tasks
Calibrates behavioral models to include operating
conditions or process variation
Adaptive
Latin Hypercube
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Circuit Modelling
Improve Design Performance & Yield
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Tools of WiCkeD – Modeling — Smart systems simulation
MunEDA contributes to the project
“SMArt systems Co-design” – SMAC
SMAC addresses a flexible software platform
(i.e., the SMAC platform) for smart
subsystems/components design and
integration
The platform shall include methodologies
and EDA tools enabling multi-disciplinary
and multi-scale modeling and design,
simulation of multi-domain systems,
subsystems and components at all levels of
abstraction, system integration and
exploration for optimization of specific
metrics,
Within SMAC MunEDA addresses the
parameterization of behavioral models of
analog circuits based on spice simulations
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Circuit Modelling
www.fp7-smac.org
The SMAC
project has
received
funding from
FP7
Cooperation
Program under
grant
agreement
n. 288827
Improve Design Performance & Yield
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Customer Example – Circuit Model Generation with MunEDA WiCkeD RSM Atmel - Modeling of Multi-stage Amplifiers with WiCkeD
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Results published by Atmel at MUGM 2009
„WiCkeD RSM provides more flexibility to the designer and saves simulation
time with large circuits and long transient runs “, Wolfgang Schneider, Atmel
Circuit Modelling
Solution
Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com 40
Circuit Sizing &
Optimization
• FEO Feasibility Optimization
• DNO Deterministic Nominal Optimization
• GNO Global Nominal Optimization
• YOP Yield Optimization
confidential confidential
Numerical sizing in the full-custom design flow
Numerical sizing has become a must-have for advanced circuit design
High-speed I/O: transients, balancing over corners
RF: noise, jitter, power trade-offs
Complex OTAs: speed, stability, feedback loops
PMU: temperature, stability
Low power analog: specs vs. power trade-off
Memories: full-custom I/O, paths, sensing, …
Numerical sizing is critical for some products‘ KPI
Ultra low power design, mobile communication, medical, near field communication, memories, FPGA
Numerical sizing consumes a lot of designer‘s time
Experienced designers spending weeks of manual tweak-simulate-tweak
41
Circuit Sizing &
Optimization
Improve Design Performance & Yield
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Numerical Sizing in Advanced Circuit Design
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Parasitic Extraction Layout Simulation
(sweeps, MC, corners, …)
Sizing by formula
Topology design
Numerical Sizing
=adjusting device parameters
(W,L,R, …) based on simulation
results
Done
Traditional analog design method: Simulation is used as a verification tool only, but not as a design tool.
Numerical sizing:
Modify device geometries iteratively
based on simulation results (after
traditional initial design).
Circuit Sizing &
Optimization
Improve Design Performance & Yield
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Tools of WiCkeD — Sizing & Optimization– Feasibility Optimization
Automated constraint generation with
advanced structure recognition.
Feasibility checks with advanced electrical
constraint checks.
Feasibility optimization: Set biasing and
operating points right for all corners and
operating conditions.
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Circuit Sizing &
Optimization
The enabler: Circuit Constraints
& Feasibility Optimization
Improve Design Performance & Yield
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Tools of WiCkeD – Sizing & Optimization— DNO & GNO Nominal Optimization
Fast and efficient. Scales well also for larger circuits.
Multiple parameters, goals, corners & testbenches optimized simultaneously
Pre- and post-layout
Broad simulator support, scriptable.
44
Circuit Sizing &
Optimization
The workers: Deterministic & Global
Nominal Circuit Optimization
Improve Design Performance & Yield
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Tools of WiCkeD – Sizing & Optimization — Design Centering (Yield Optimization)
Improve robustness vs process
variation and mismatch
Multiple performances simultaneously
Based on worst-case distance
and sigma measures
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Circuit Sizing &
Optimization
The unique flagship:
Automated Yield Optimization
Improve Design Performance & Yield
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Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools TOP Microprocessor Company - Using MunEDA tools to optimize AMS/RF IP in 65nm
TOP Microprocessor Company - RF receiver path in advanced node
– Task: reduce power consumption while keeping noise low
– To see the noise vs power trade-off, the complete path has to be considered
– Circuit size: ~2000 MOS, ~8000 parasitics.
Simulation time: 40min. for a single run (dc+pss+pnoise)
– Optimization complexity: 80 specs, 50 design parameters
Three process corners + temperature + Vdd
Block 1 Block 2 Block 3 Block 4
Noise matching between blocks
power
Results:
• Power consumption significantly
reduced.
• Sizing task performed completely
automatically.
• Designer attention time is reduced
from 4 weeks to a few hours.
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Improve Design Performance & Yield
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Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools SKHynix - Digital Full-Custom Design – Path Delay Optimization in 28nm Memory (DRAM)
Circuit Description: – Receiver for DRAM Cells
– 28nm Technology
– 1300 Transistors
Issue: Timing Difference (Delay) of Pin-to-
Pin-Skew caused by local variation is too
high (simulation: 100ps; pre-silicon)
Goal: Optimize path delay to <15ps in
silicon
Solution Approach: 4 main analysis &
optimization steps with MunEDA WiCkeD tools:
Path Delay (P2P Skew) reduced with WiCkeD from >100ps to 31,4 ps
in simulation – corresponding to 14,7 ps in silicon (measured result)
Results published by Hynix Semiconductor at MUGM2009, MTF Korea 2011
47
Improve Design Performance & Yield
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Solution:
WiCkeD Optimization + Validation
Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools Toshiba - Optimization of PLL parameters in 40nm
PLL behavioral model
Task: find optimal parameters for the
behavioral model
Challenge: statistics, multiple variants
PLL design parameters could be found by WiCkeD DNO and YOP,
considering dispersion of parameters with agauss()
WiCkeD can save time to decide PLL parameters.
Results published by Toshiba at MTF Tokio 2012
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Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools STMicroelectronics - Optimization of High-Speed I/O circuits in 28nm
28nm DDRx High-Speed I/O
Task: Reduce jitter and duty cycle
Challenge: Manual tuning
takes 2 weeks
Solution:
Use MunEDA Sensitivity Analysis
and Corner Optimization
Results published by STMicroelectronics at MUGM 2011
Design Time reduced from 2 weeks to only 3 hours
Corner spread reduced by 50%
Easy analysis of circuit sensitivities
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Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools Altera - Post-layout optimization of FPGA lookup tables
Circuit Description:
FPGA LUT 40nm
> 2,400 MOS
> 40,000 RC
> 30,000 nodes
187 degrees of freedom
5 simultaneous runsets
Transient simulation with
HSim
Task: Reduce area by 20%, but
don‘t increase delays
Solution:
Run WiCkeD FEA and DNO
Results published by Altera at MUGM 2010
Result: Area reduced by 22%, delays as good as initially.
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Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Tools of WiCkeD – Analysis, Verification, Optimization – BAS / SCR Batch mode operation
WiCkeD is fully scriptable, no
GUI interaction necessary
– Improved efficiency for repetive
tasks
– Good for libraries and IP
(standard cell, I/O macros, …)
– Can run in batch mode on
command line on
netlists; no design framework
needed during runtime
Script.py /
Script.tcl
Sized
Netlist
Settings.XML
Reports
Runset (netlist, models,
.measure, …)
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Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Solution:
MunEDA Nominal Optimization in
Batch Mode
Customer Example – Sizing & Design Centering with MunEDA WiCkeD Optimization Tools Faraday – Batch-mode optimization of standard cells
Standard cell: Clock buffers
Task: Balance slopes
Challenge: many cell & process variants,
multiple slews and output loads,
frequent model update
Complete automation reduces design time significantly.
Equal or better results than manual design.
Results published by Faraday at MTF Anaheim 2008
52
Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Summary – High-Level Benefits of WiCkeD
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Significant design time reduction
Improved design & porting efficiency and quality
Increased design certainty
Simultaneous sizing for multiple specs, corners, goals
Achieve better circuit performance and robustness
Filling gaps within existing designflows
Documentation for better project management
Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
MunEDA—Products & Applications
Broad choice of tools in one suite, compatible with standard flows
Focus on designer’s efficiency and design quality
Long-term experience with a broad customer base
54
Improve Design Performance & Yield
© Copyright by MunEDA GmbH - All rights reserved - www.muneda.com
Thank You !
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