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Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock Slide 1
Spezielle Anwendungen des VLSI – Entwurfs
Applied VLSI design
Course and contest
Adder structures
Sebastian Kruse
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Types of adders
Slide 2
• Redundant• Carry-Save (CSA)• Redundant-Binary (RBA)
• Not redundant (CPA)• Ripple-Carry (RCA), Manchester-Carry-Chain (MCC)• Carry-Skip (CSK), Carry-Select (CSEL)• Carry-Lookahead (CLA), Conditional-Sum (CSUM)• Asynchronous adder
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Ripple-Carry adder
Slide 3
FA FA FA
s1 s0sn-1
cout cinc1c2cn-1
b0a0b1a1bn-1an-1
• Serialization of full adders• Small area but slow speed• In general the best adder for FPGA
• FPGA uses LUTs instead of AND, OR, XOR, NOT• Optimized logic which speeds up RCA
Delay time
Area
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Carry-Skip adder
Slide 4
CPA CPA
CPA
01
01
Delay time
Area
• Adder with square timing complexity and low area
• Area compared to RCA:
• Idea: parallel calculation
𝑠𝑖− 1:𝑘 𝑠𝑛− 1: 𝑖
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Carry-Lookahead adder
Slide 5
CLA-Block
Delay time
Area
• Fast adder with logarithm complexity but high area
• Idea: carry is calculated in advance
• Types of implementation (for carry generation)• Slansky• Kogge-Stone
…
• Brent-Kung• Han-Carlson
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Brent-Kung
• Idea: use binary tree for carry propagation
• Two tree structures• Carry collection• Carry redistribution
Slide 6
Delay time
Area
carrytree
inversecarrytree
𝑐0𝑐1
𝑐2
𝑐3
𝑐4
𝑐5
𝑐6
𝑐7
(𝑔1 ,𝑝1)(𝑔0 ,𝑝0)
(𝑔3 ,𝑝3)(𝑔2 ,𝑝2)
(𝑔5 ,𝑝5)(𝑔4 ,𝑝4)
(𝑔7 ,𝑝7)(𝑔6 ,𝑝6)
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Comparison on FPGA
Slide 7
• RCA• Area : 103• Max. frequency : 431,779 MHz
• CSK• Area : 125 • Max. frequency : 384,025 MHz
• Brent Kung• Area : 109• Max. frequency : 409,500 MHz
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Comparison on ASIC
Slide 8
• RCA
• Core size : 4634,45 µm²
• Max. frequency : 3180 MHz
• Pdyn : 22,154 mW
• Pleak : 9,875 µW
• CSK
• Core size: 4324,63 µm²• Max. frequency : 2910MHz
• Pdyn : 18,651 mW
• Pleak : 8,346 µW
• Brent Kung• Core size : 4392,61 µm²• Max. frequency : 2980 MHz
• Pdyn : 19,406 mW
• Pleak : 8,716 µW
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Thank you for your attention!
Slide 9
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Half / full adder
Slide 10
FA
a b
cincout
s
HA
a b
cout
s
• Half adder ((2,2)-counter)
• Full adder ((3,2)-counter)
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Comparison of adders
Slide 11
0 10 20Number of bits
0
20
40
60
80
0 10 20Number of bits
0
0.2
0.4
Brent-Kung
CSK
RCA Brent-Kung
RCA
t p(n
sec)
Are
a (m
m2)
Source: mountains.ece.umn.edu (2006)
CSK
Institute of Applied Microelectronics and Computer Engineering
College of Computer Science and Electrical Engineering, University of Rostock
Kogge-Stone
Slide 12