Post on 06-Feb-2016
description
Powering tests
Laura Gonella Physikalisches Institut Uni Bonn
Regulator powering configuration 1
L. Gonella - Powering tests2
Regulator powering configuration 1
L. Gonella - Powering tests3
0.01Ω
0.01Ω
Power up - Voltage
• Vin is the voltage at the power supply• Vin Reg1, Vin Reg2, VDDD, VDDA are measured at the pad
– Wire bond from the pad to a measurement point
L. Gonella - Powering tests4
Power up - Current• Iin is the current measured at the power supply, i.e. total
current flowing to the chip• Ia and Id are the analog and digital currents measured across
the 10mΩ resistor• The current flowing thorugh the regulators at start up is
defined by Vin/Rext, not by the load– This is always the case as long as Iload < Vin/Rext
L. Gonella - Powering tests5
VDDD regulated VDDA regulated
Voltages and currents
Vin (V) Iin (A) Vin Reg1/2(V)
VDDD/A Ia, Id (A)
Power up A 1.8 0.239 1.716 1.473 0.150D 1.728 1.198 0.140
Clock on A 1.8 0.262 1.709 1.470 0.180D 1.722 1.189 0.141
Std cfg A 1.8 0.409 1.640 1.418 0.3751.458(*)
D 1.686 1.189 0.137PrmpVbp*2
A 1.8 0.509 1.588 1.413 0.511
D 1.660 1.189 0.134
6 L. Gonella - Powering tests
• (*) Vref1 = 0.730V, increased to 0.750V after loading the std cfg
Threshold scan
L. Gonella - Powering tests7
Threshold scan – PrmpVbp*2
L. Gonella - Powering tests8
Regulator powering configuration 2
L. Gonella - Powering tests9
Regulator powering configuration 2
L. Gonella - Powering tests10
Vref = 0.740V
Vref = 0.740V
0.01Ω
0.01Ω
Power up - Voltage
• VDDD and the Vin for the regulators are ramped up in steps of 100mV to avoid switching on the protection diodes
L. Gonella - Powering tests11
Power up - Current
L. Gonella - Powering tests12
Threshold scan
L. Gonella - Powering tests13
Threshold scan – PrmpVbp*2
L. Gonella - Powering tests14
Vref mismatch
• The short between the outputs is not exactly a short. There is a resistance of 2.1Ω between the output of the regulators
• This introduces an unbalance between the current distribution on top of what is given by mismatch in the design, Vref values, Rext values, etc..
L. Gonella - Powering tests15
2.1 Ω
0ΩVDDA
Vref mismatch
L. Gonella - Powering tests16
Vref (V)
Vin (V) Iin (A)
VDDA (V)
Reg1 0.740 1.656 0.289 1.455Reg2 0.740 1.676 0.200Reg1 0.750 1.630 0.401 1.451Reg2 0.730 1.681 0.134Reg1 0.760 1.596 0.491 1.433Reg2 0.720 1.665 0.130Reg1 0.770 1.583 0.524 1.414Reg2 0.710 1.656 0.129Reg1 0.780 1.571 0.554 1.394Reg2 0.700 1.653 0.129
Vref (V)
Vin (V) Iin (A)
VDDA (V)
Reg1 0.740 1.656 0.289 1.455Reg2 0.740 1.676 0.200Reg1 0.730 1.671 0.196 1.455Reg2 0.750 1.660 0.282Reg1 0.720 1.655 0.172 1.443Reg2 0.760 1.618 0.391Reg1 0.710 1.647 0.170 1.424Reg2 0.770 1.600 0.429Reg1 0.700 1.642 0.170 1.405Reg2 0.780 1.585 0.456
Summary table
L. Gonella - Powering tests17
Std PrmpVbp*2 Std PrmpVbp*2Vth 4652 4630 4433 4433Vth dispersion 639.1 625.6 569.5 565.3Noise 149.1 143.6 135.9 133.7Noise dispersion 15.63 13.83 10.81 10.3
Std PrmpVbp*24499 4466599.4 588152.2 142.316.26 13.45
VthVth dispersionNoiseNoise dispersion
Std PrmpVbp*24340 4365575.4 568.9148 144.4
13.42 12.15
Backup
L. Gonella - Powering tests18
Direct powering configuration 1
19 L. Gonella - Powering tests
Direct powering configuration 1
20 L. Gonella - Powering tests
1.5V
1.2V
Voltages and currents
V @ supply (V) V @ chip (V) I (mA)Power up A 1.5 1.502 13
D 1.2 1.199 3Clock on A 1.5 1.502 13
D 1.2 1.176 92Std cfg A 1.5 1.458 268
D 1.2 (1.22) 1.172(1.191) 107(109)PrmpVbp*2 A 1.5 1.440 372
D 1.22 1.192 105
21 L. Gonella - Powering tests
• I is measured at the power supply• Resistance of the analog input path = Ra = 0.157Ohm• Resistance of the digital input path = Rd = 0.265Ohm
Threshold scan
22 L. Gonella - Powering tests
Threshold scan – PrmpVbp*2
23 L. Gonella - Powering tests
Direct powering configuration 2
24 L. Gonella - Powering tests
Direct powering configuration 2
• VDDD and VDDA shorted at supply– Same wires as in the previous measurement– Use calculated Ra and Rd to extimate analog and digital current,
Ia and Id
1.5V
25 L. Gonella - Powering tests
Voltages and currents
V @ supply (V)
V @ chip (V)
I (mA) Ia/Id (mA)
Power up A 1.5 1.502 20D 1.502
Clock on A 1.5 1.498 98 13D 1.484 60
Std cfg A 1.5 1.458 481 268D 1.440 226
PrmpVbp*2
A 1.5 1.447 508 338
D 1.455 170
26 L. Gonella - Powering tests
• I is the current measured at the power supply, Ia and Id are calculated using Ra and Rd
Threshold scan
27 L. Gonella - Powering tests
Threshold scan – PrmpVbp*2
28 L. Gonella - Powering tests
Powering configurations
29 L. Gonella - Powering tests
Direct powering configuration 1
Direct powering configuration 2
Regulator powering
configuration 1
Regulator powering configuration 2
Meaurements
• For different powering configuration, measure
For now done on bare chips. Current PCB does not have circuitry for sensor HV.
Wire bond from VDDA pad to measurement point. Same for VDDD.
VDDA2M is not connected on the PCB. It was removed to make space for regulator testing circuitry.
43PrmpVbp = PrmpVbp_L/R
= 86
30 L. Gonella - Powering tests
Setup
• Power is provided via an independent power supply– Either to VDDD and VDDA directly or to the input of the
regulators• USBpix is used only to send/receive signals to/from the chip
– Stcontrol– Standard configuration file
• Top row not powered– DC1 and DC40 disabled
31 L. Gonella - Powering tests