Post on 23-Feb-2016
description
Multi-IO board and FE-I4 emulator
F. Hügging
Review of FE-I4CERN, 04-11-2009
University of Bonn
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Introduction• Work on test systems was initiated one year ago because
maintenance and rebuilding of the TPLL/TPCC system turned out to be difficult.
• Proposed a “Lightweight”/low-cost replacement/addition for the TPLL/TPCC system.– based on “S3 Multi-IOBoard“ used as well for several other
applications in Bonn.– limited FPGA/memory resources: no DSP, no dedicated
programmable delay lines.• Build & commisioned the S3 Multi-IOBoard as test system
for FE-I3 single chips during the last year USBPix. • Decided to use this test system as a basis for the system
for the FE-I4 chip and (small) module testing.– TPLL/TPC and TurboDAQ will not be developed for supporting FE-
I4.FE-I4 Review Fabian Hügging, University of Bonn
USBPix Hardware
FE-I4 Review Fabian Hügging, University of Bonn 3
USBpix – Some Specs•USB/FPGA Board (S3MultiIOBoard)
–15 Mbyte/sec FPGA PC data transfer speed–2 Mbyte SRAM–Xilinx XC3S1000 FPGA–LVDS and TTL IOs (for ext. trigger, TDC etc.)–8051 USB microcontroller–Drivers for Windows XP and Linux
•Adapter Card –support of FE-I3 single chip cards or modules–LVDS RX/TX–on board ADC for current, voltage and temperature measurement (NTC )
FE-I4 Review Fabian Hügging, University of Bonn 4
Firmware Structure
8051 µC
USB
configuration state machine
strobe & LV1state machine
data receiverstate machine
reset/sync state machine
readdata buffer
& event builder
write data buffer(parser)
data memory
LDDICCK
SYNCRST
LV1
DO1DO2
histogrammingstate machine
scan routines
full chip scan data:2880px 256 steps 8bit
data
clock XCK
USB controller
FPGA
external
STRB
external triggermaster
state machine
FE-I4 Review Fabian Hügging, University of Bonn 5
USBPix – StatusHardware:• ~20 boards already delivered• FPGA firmware ready• Microcontroller firmware enhancements for hardware controlled scans under
development• two readout-modes implemented:
– run mode: full hit information storage in SRAM (tested - works)– calibration mode: histograms for all pixels stored in SRAM for parameter scan (tested
- works)
Software (Qt based WinXP & Linux):• USBPixDll – communicates with HW, handles configuration data and hit
information, provides access to data to GUIs (authors: Malte Backhaus, Hans Krüger)
two GUIs available: • small, simple Test application (USBPixTest) for testing the communication to
HW and testing FE-I3, incl. Th-scans and plotting/fitting data (no external libraries needed), author: Malte Backhaus
• Fully featured application (STControl) using PixLib and ROOT, authors: Jens Weingarten, Jörn Grosse-Knetter
http://icwiki.physik.uni-bonn.de/twiki/bin/view/Systems/UsbPix
FE-I4 Review Fabian Hügging, University of Bonn 6
Firmware Development Status
FPGA
USB Microcontroller
FE-I4 Review Fabian Hügging, University of Bonn 7
STControl USBPixTest
FE-I4 Review Fabian Hügging, University of Bonn 8
Application software
More details by Jens Weingarten
• “software” controlled scan: pixel mask and scan values controlled via USBpixTest.
• 40 sec. for threshold scan of all pixels (256 scan steps, 100 inject pulses each), slightly faster than TurboPLL/PCC.
• scan routine is implemented in “software” or in “hardware” controlled by microcontroller. (basically no change in speed limited by strobe, trigger timing).
• same noise performance as with TurboPLL/PCC setup.
FE-I4 Review Fabian Hügging, University of Bonn 9
System performance
0 40 80 120 160 200 240 280 320 360 400 440 4800
50010001500
noise dispersion, full chip, untuned
Sigma [e-]
Sigma [e-]
# p
ixel
3000360042004800540060006600720078000
50100150
Threshold dispersion, full chip, untuned
Threshold [e-]
threshold [e-]
# p
ixel
Commissioning Status• 19 systems have been ordered
– CERN– DESY– University of Dortmund– University of Göttingen– University of Hamburg– IFAE Barcelona– Iowa State University– KEK– MPI Munich– LBNL– University of New Mexico– University of California Santa Cruz– SLAC– Stony Brook University
• shipping of the hardware finished• software will be distributed from SVN repository at
http://icwiki.physik.uni-bonn.de/twiki/bin/view/Systems/UsbPix• Still some debugging of the code ongoing
FE-I4 Review Fabian Hügging, University of Bonn 10
USBPix for FE-I4: Why?• Can serve as chip and (small) module FE-I4 test system.• Will be used together with dedicated probe card as a
wafer probing system.• Application software development is more or less
decoupled from hardware and can be used for other hardware platforms as well.
• Main parts of the hardware are already in the field• Hardware support for testbeam usage (EUDET) and
irradaition is already integrated.
USBPix FE-I4 serves as chip and module test system at least for the prototype phase of the IBL
11FE-I4 Review Fabian Hügging, University of Bonn
USBPix for FE-I4: What is needed?
• New adapter boards needed. – Bonn will do this.– Easy and fast to do.
• New firmware code for FE-I4 needed. – Bonn will do this.– most important and a major part of the work. – already started to program the Verilog code of the FE-I4 to a commercial USB
board which can be used as test bench for firmware development of the USBPix.
• Hardware upgrade of USBPix board can be done. – more SRAM for accommodate bigger chip size could be helpful.– relatively easy.– but for a first step for FE-I4 testing the current hardware should be sufficient
only with a firmware update. • Application software development relies on the further development of
PixLib/STControl software.– certainly one major part of the job see J. Weingarten talk.
12FE-I4 Review Fabian Hügging, University of Bonn
Limitations of the USBPix
• Limited data transfer rate (USB2.0). – higher parallelization of module/chip testing as may be
needed for production is unlikely.• Maximum timing accuray of the output of the
FPGA is 1ns.– No dedicated programmable delay lines.– This limits the precision of timewalk and other time
dependent measurements. • Limitations in higher level data analysis function
inside the FPGA.– Not clear whether fitting of histograms etc. is possible
inside the FPGA.
13FE-I4 Review Fabian Hügging, University of Bonn
Firmware development for FE-I4• One crucial point for adapting the
USBPix system in time for FE-I4 is the firmware development.
• Need a FE-I4 emulator to allow realistic firmware development before FE-I4 arrives.
• Uses a spin-off of the stave emulator test bench (developed for SLHC upgrade purposes)– “Module units“ are perfect
candidates for the FE-I4 emulator.
FE-I4 Review Fabian Hügging, University of Bonn 14
add-on boardadd-on boardadd-on board
FPGA cardFPGA cardFPGA card
FPGA board
Virtex 4
End of stave emulator unit(FPGA board + interface board + DCS card)
Up to 8 module emulator units(FPGA card + add-on board)
...
DCS
USB
GBTinterface
card
FPGA Board for FE-I4 Emulator• commercial FPGA board (Trenz
TEO300B) with:– Spartan XC3S1600E.– 64 Mbyte DDR RAM.– 32 Mbit Flash.– USB interface.
• Approx. size of a 2x2 FE-I4 chip module.
• Uses dedicated adapter board for interconnection to several systems:
– As module unit for stave emulator test bench.
– As single FE-I4 chip to connect to the USBPix system.
• Status of module unit as FE-I4 emulator:
– Some part of the FE-I4 data output protocol already implemented in the FPGA (including 8/10 bit encoding)
– Implementatiopn of the FE-I4 code to the FPGA started.
– Interconnection board design started.
40.5 mm
47.5 mm
(Trenz TEO300B)
Module emulator unit
FE-I4 Review Fabian Hügging, University of Bonn 15
Fabian Hügging, University of Bonn 16
Further Aspects• Up to now firmware development concentrates on operating
the FE-I4 chip:– Write/read register. – Digital & analog scanning, etc.
• Scan Chain support as needed for structural testing can be implemented as well into the USBPix FPGA: – requires a new branch of the FPGA firmware. – must be supported from the application software.
• Hardware upgrade possibilities:– More on-board memory might be needed since the pixel number is
now 10 times higher as for FE-I3 (26.880 vs. 2880).– A more powerful FPGA could help with higher level analysis
functions.– Can either upgrade the existing S3Multi-IOBoard or use an already
existing development (Virtex 4 Board) which uses the same USB interface and offers many more features.
FE-I4 Review
Virtex 4 board – some technical specs.
32 MB DDR2 memory
Connector for USB interface
high speed add-on board connectors 32 LVDS pairs
+26 CMOS I/O
Virtex 4LX40 FPGA
RJ-45 connector to TLU (trigger logic unit)
FE-I4 Review Fabian Hügging, University of Bonn 17
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Summary• USBPix successfully commissioned for
testing FE-I3 single chips.• The modular design of USBPix in terms of
hardware, firmware and software makes it easy to develop it further as a test system for FE-I4.– Basically no hardware change is needed.– Work has already started to implement FE-I4
support to the firmware using a FE-I4 emulator.– Further functionality like wafer testing and scan
chain support can be implemented. FE-I4 Review Fabian Hügging, University of Bonn