L21:Lower Power Layout Design

1998. 6.7

성균관대학교 조 준 동 교수http://vlsicad.skku.ac.kr

• Constant scaled wire increases coupling capacitance by S and wire resistance

by S• Supply Voltage by 1/S, Theshold Voltage by 1/S, Current Drive by 1/S• Gate Capaitance by 1/S, Gate Delay by 1/S• Global Interconnection Delay, RC load+para by S• Interconnect Delay: 50-70% of Clock Cycle• Area: 1/S2

• Power dissipation by 1/S - 1/S2

• ( P = nCVdd2f, where nC is the sum of capacitance times #transitions)

• SIA (Semiconductor Industry Association): On 2007, physical limitation: 0.1 m

20 billion transistors, 10 sqare centimeters, 12 or 16 inch wafer

Device Scaling of Factor of S

Delay Variations at Low-Voltage

• At high supply voltage, the delay increases with temperature (mobility is decreasing with temperature) while at very low supply voltages the delay decreases with temperature (VT is decreasing with temperature).

• At low supply voltages, the delay ratio between large and minimum transistor widths W increases in several factors.

• Delay balancing of clock trees based on wire snaking in order to avoid clock-skew. In this case, at low supply voltages, slightly VT variations can significantly modify the delay balancing.

Quarter Micron Challenge

• Computers/peripherals (SOC): 1996 ($50 Billion) 1999 ($70 Billion)• Wiring dominates delay: wire R comparable to gate driver R; wire/wire coupling

C > C to ground• Push beyond 0.07 micron• Quest for area(past), speed-speed (now), power-power-power(future)• Accelerated increases of clock frequencies• Signal integrity-based tools• Design styles (chip + packages)• System-level design(system partitioning)• Synthesis with multiple constraints (power,area,timing)• Partitioning/MCM• Increasing speed limits complicate clock and power distribution• Design bounded by wires, vias, via resistance, coupling• Reverse scaling: adding area/spacing as needed: widening, thickening of wires,

metal shielding & noise avoidance - adding metal

CLOCK POWER CONSUMPTION

•Clock power consumption is as large as the logic power; Clock Signal carrying the heaviest load and switching at high frequency, clock distribution is a major source of power dissipation.• In a microprocessor, 18% of the total power is consumed by clocking• Clock distribution is designed as a hierarchical clock tree, according to the decomposition principle.

Power Consumption per block in typical microprocessor

Crosstalk

Solution for Clock Skew• Dynamic Effects on Skew

Capacitance Coupling• Supply Voltage Deviation (Clock

driver and receiver voltage difference)

• Capacitance deviation by circuit operation

• Global and local temperature• Layout Issues: clocks routed first• Must aware of all sources of delay• Increased spacing• Wider wires• Insert buffers• Specialized clock need net

matching• Two approaches: Single Driver, H-

tree driver

• Gated Clocks: The local clocks that are conditionally enabled so that the registers are only clocked during the write cycles. The clock is partitioned in different blocks and each block is clocked with its own clock.

• Gating the clocks to infrequently used blocks does not provide and acceptable level of power savings

• Divide the basic clock frequency to provide the lowest clock frequency needed to different parts of the circuit

• Clock Distribution: large clock buffer waste power. Use smaller clock buffers with a well-balanced clock tree.

PowerPC Clocking Scheme

CLOCK DRIVERS IN THE DEC ALPHA 21164

DRIVER for PADS or LARGE CAPACITANCES

Off-chip power (drivers and pads) are increasing and is very difficult to reduce such a power, as the pads or drivers sizes cannot be decreased with the new technologies.

Layout-Driven Resynthesis for Lower Power

Low Power Process

• Dynamic Power Dissipation

Vdd

V in Vo

C ovp

C ovn

C djp

C djn

DrainW

D

C jbC jsw

)(2 ,

)(

)(

)(2

0

1

1

2

2

DWPDWA

PCACC

WCC

CC

LWCC

VVI

fVCP

DD

DjswDjdj

GDov

m

jjgatein

n

ioxgate

tgsds

ddLd

Crosstalk• In deep-submicron layouts, some of the netlengths for connection between modules

can be so long that they have a resistance which is comparable to the resistance of the driver.

• Each net in the mixed analog/digital circuits is identified depending upon its crosstalk sensitivity– 1. Noisy = high impedance signal that can disturb other signals, e.g., clock signal

s.– 2. High-Sensitivity = high impedance analog nets; the most noise sensitive nets

such as the input nets to operational amplifiers.– 3. Mid-Sensitivity = low/medium impedance analog nets.– 4. Low-Sensitivity = digital nets that directly affect the analog part in some cells

such as control signals.– 5. Non-Sensitivity = The most noise insensitive nets such as pure digital nets,

• The crosstalk between two interconnection wires also depends on the frequencies (i.e., signal activities) of the signals traveling on the wires. Recently, deep-submicron designs require crosstalk-free channel routing.

Power Measure in Layout

• The average dynamic power consumed by a CMOS gate is given below, where C_l is the load capacity at the output of the node, V_dd is the supply voltage, T_cycle is the global clock period, N is the number of transitions of the gate output per clock cycle, C_g is the load capacity due to input capacitance of fanout gates, and C_w is the load capacity due to the interconnection tree formed between the driver and its fanout gates.

• Pav = (0.5 Vdd2) / (Tcycle Cl N) = (0.5 Vdd

2) / (Tcycle (Cg + Cw )N)

• Logic synthesis for low power attempts to minimize SUM i Cgi Ni

• Physical design for low power tries to minimize SUMi Cwi Ni

• . Here Cwi consists of Cxi + CsI, where Cxi is the capacitance of net i due to its crosstalk, and CsI is the substrate capacitance of net i. For low power layout applications, power dissipation due to crosstalk is minimized by ensuring that wires carrying high activity signals are placed sufficiently far from the other wires. Similarly, power dissipation due to substrate capacitance is proportional to the wirelength and its signal activity.

이중 전압을 이용한 레이아웃 • 조합회로의 전력 소모량을 줄이는

이중 전압 레이아웃 기법 제안

• 이중 전압 셀을 사용할 때 , 한 cell row 에 같은 전압의 cell 이 배치되면서 증가하는 wiring 과 track 의 수를 줄임

• 최소 트랜지스터 개수를 사용하는 Level Converter 회로의 구현

• 디바이스의 성능을 유지하면서 이중 전압을 사용하는 Clustered Voltage Scaling [Usami, ’95] 을 적용

• 제안된 Mix-And-Match Power Supply 레이 아웃 구조는 기존의 Row by Row Power Supply [Usami, ’97] 레이 아웃 구조를 개선하여 전력과 면적을 줄임

Clustered Voltage Scaling• 저전력 netlist 를 생성

F/F

F/F

F/F

LC 2

G 1

G 2

G 3G 4

G 5

G 6

G 7G 8

LC 1

G 11 G 9G 10

S lack(S i) = R i - A i

S 1> 0

S 3> 0S 4> 0

S 5> 0

S 6> 0

S 9> 0S 7< 0

S 10< 0

S 11< 0

S 8< 0

: VDDL

: VDDH

: Level C onverter

S 2< 0

VDDH

VDDL

VDDH

VDDHVDDL

standard cell

s tandard cell

module

VS SVDDH cell

VS S

VDDL

VDDL cell

standard cell

VDDH cell

VDDL cell

Row by Row Power Supply 구조

Mix-And-Match Power Supply 구조

VDDH

VDDLVDDHVDDL

standard cell

s tandard cell

module

standard cellVDDH

cellVDDL

cell

VDDH cell

VDDL cell

VDDL cellVDDH cellVS S

VDDL

VDDH

VS S

VDDL

VDDH

VDDH

module

VDDH

VDDL

module

VDDH

VDDL

module

구 조 비 교Conventional RRPS MAMPS

Circuit

Level Converter 구조• Transistor 의 갯수 : 6 개 4 개 • 전력과 면적면에서 효과적

기 존 제 안

VS S / VDDL

Vth= 1.5V

VS S / VDDH

Vth= 2.0V

VDDHVDDH

INVDDL

VDDH

O U T

Mix-And-Match Power Supply Design Flow

Physical placem ent

Assign supply voltage to each cell

Routing

Synthesis tim ing, power and area

S ingle voltage netlist

Netlist with m ultiple supply voltage

Multiple voltage scaling

(O P U S )

(Aquarius XO )

(P owerM ill)

Area (% )

C onventionalc ircuit

R R P S M AM P S

15%10%

100

power (%)

C onventionalc ircuit

RR P S M AM P S

47%

2%

100

실 험 결 과

전체 Power 전체 Area

Low Power Design Tools

• Transistor Level Tools (5-10% of silicon)– SPICE, PowerMill(Epic), ADM(Avanti/Anagram), Lsim Power Analyst(mentor)

• Logic Level Tools (10-15%)– Design Power and PowerGate (Synopsys), WattWatcher/Gate (Sente), PowerSim (S

ystem Sciences), POET (Viewlogic), and QuickPower (Mentor)

• Architectural (RTL) Level Tools (20-25%)– WattWatcher/Architect (Sente): 20-25% accuracy

• Behavioral (spreadsheet) Level Tools (50-100%)– Active area of academic research

Commercial synthesis systems

Research synthesis systems A - Architectural synthesis.

L - Logic synthesis.

Low-Power CAD sites• Alternative System Concepts, Inc, : 7X power reduction throigh optimization, con

tact http://www.ee.princeton.edu and Jake Karrfalt at jake@ascinc.com or (603) 437-2234. Reduction of glitch and clock power; modeling and optimization of interconnect power; power optimization for data-dominated designs with limited control flow.

• Mentor Graphics QuickPower: Hierarchical of determining overall benet of exchanging the blocks for lower power. powering down or disabling blocks when not in use by gated-clock

• choose candidates for power-down Calculate the effect of the power-down logic http://www.mentorg.com

• Synopsys's Power Compiler http://www.synopsys.com/products/power/power_ds

• Sente's WattWatcher/Architect (first commerical tool operating at the architecture level(20-25 %accuracy). http://www.powereda.com

• Behavioral Tool: Hyper-LP (Optimization), Explore (Estimation) by J. Rabaey

Design Power(Synopsys)

• DesignPower(TM) provides a single, integrated environment for power analysis in multiple phases of the design process:

– Early, quick feedback at the HDL or gate level through probabilistic analysis.

– Improved accuracy through simulation-based analysis for gate level and library exploration.

• DesignPower estimates switching, internal cell and leakage power. It accepts user-defined probabilities, simulation toggle data or a combination of both as input. DesignPower propagates switching information through sequential devices, including flip-flops and latches.

• It supports sequential, hierarchical, gated-clock, and multiple-clock designs. For simulation toggle data, it links directly to Verilog and VHDL simulators, including Synopsys' VSS.

References[1] Gary K. Yeap, "Practical Low Power Digital VLSI Design",

Kluwer Academic Publishers.[2] Jan M. Rabaey, Massoud Pedram, "Low Power Design Methodologies",

Kluwer Academic Publishers.[3] Abdellatif Bellaouar, Mohamed I. Elmasry, "Low-Power Digital VLSI Design

Circuits And Systems", Kluwer Academic Publishers.[4] Anantha P. Chandrakasan, Robert W. Brodersen, "Low Power Digital CMOS Design", Kluwer Academic Publishers.[5] Dr. Ralph Cavin, Dr. Wentai Liu, "1996 Emerging Technologies : Designing Low Power Digital Systems"[6] Muhammad S. Elrabaa, Issam S. Abu-Khater, Mohamed I. Elmasry, "Advanced Low-Power Digital Circuit Techniques", Kluwer Academic Publishers.

References

• [BFKea94] R. Bechade, R. Flaker, B. Kaumann, and et. al. A 32b 66 mhz 1.8W Microprocessor". In IEEE Int. Solid-State Circuit Conference, pages 208-209, 1994.

• [BM95] Bohr and T. Mark. Interconnect Scaling - The real limiter to high performance ULSI". In proceedings of 1995 IEEE international electron devices meeting, pages 241-242, 1995.

• [BSM94] L. Benini, P. Siegel, and G. De Micheli. Saving Power by Synthesizing Gated Clocks for Sequential Circuits". IEEE Design and Test of Computers, 11(4):32-41, 1994.

• [GH95] S. Ganguly and S. Hojat. Clock Distribution Design and Verification for PowerPC Microprocessor". In International Conference on Computer-Aided Design, page Issues in Clock Designs, 1995.

• [MGR96] R. Mehra, L. M. Guerra, and J. Rabaey. Low Power Architecture Synthesis and the Impact of Exploiting Locality". In Journal of VLSI Signal Processing,, 1996.