Futur of Nano CMOS Technology - 東京工業大学 of Nano CMOS Technology ... Still, Si CMOS...

Hiroshi Iwai

Frontier Research CenterTokyo Institute of Technology

Futur of Nano CMOS TechnologyFutur of Nano CMOS Technology

January 3, 2014, At IBM SRDC (Semiconductor Research and Development Center). Bangalore

Back ground for nano-electronics

1900 “Electronics” started.

Device: Vacuum tubeDevice feature size: 10 cm

1970 “Micro-Electronics” started.

Device: Si MOS integrated circuitsDevice feature size: 10 µm

Major Appl.: Amplifier (Radio, TV, Wireless etc.)

Major Appl.: Digital (Computer, PC, etc.)

Technology Revolution

2000 “Nano-Electronics” started.

Device: Still, Si CMOS integrated circuitsDevice feature size: 100 nmMajor Appl.: Digital (µ-processor, cell phone, etc.)

Technology Revolution??

Maybe, just evolution or innovation!

But very important so many innovations!

Now, 2013 “Nano-Electronics” continued.

Device: Still, Si CMOS integrated circuitsDevice feature size: near 10 nmMajor Appl.: Still Digital (µ-processor, cell phone, etc.)

But, so many important emerging applications for smart society.

Still evolution and innovation..

Future, “Nano-Electronics” still continued?

Device: Still, Si CMOS integrated circuits?

Device feature size: ? nm, what is the limit?

Application: New application?

Any Technology Revolution?

Questions for future

What is special or new for Nano-Electronics?

In 1990’s, people expected completely new mechanism or operational principle due the nano size, like quantum mechanical effects.

However, no fancy new operational principle was found.

At least for logic application, there is no success story for “Beyond CMOS devices” to replace Si-CMOS.

Of course, I do not deny the importance of Beyond CMOStechnology development. It is becoming very importantas CMOS approach its limit.

1. Back ground for nano-CMOS

First Computer Eniac: made of huge number of vacuum tubes 1946Big size, huge power, short life time filament

Today's pocket PCmade of semiconductor

has much higher performance with

extremely low power consumption

dreamed of replacing vacuum tube with solid‐state device

1960: First MOSFET by D. Kahng and M. Atalla

Top View

Al Gate

Source

Si/SiO2 Interface is extraordinarily good

1970,71: 1st generation of LSIs

DRAM Intel 1103 MPU Intel 4004

Most Recent SD Card

128GB (Bite) = 128G X 8bit= 1T(Tera)bit

1T = 1012 = １Trillion

Brain Cell：10～100 BillionWorld Population：7 Billion

Stars in Galaxy：100 Billion

In 2012

2.4cm X 3.2cm X 0.21cm

Volume：1. 6cm³ Weight：2g

Voltage：2.7 - 3.6V

Old Vacuum Tube：5cm X 5cm X 10cm, 100g, 50W

128 GB = 1Tbit

What are volume, weight, power consumption for 1Tbit

Old Vacuum Tube：5cm X 5cm X 10cm

1Tbit = 10,000 X 10,000 X 10,000 bitVolume = (5cm X 10,000) X (5cm X 10,000)

X (10cm X 10,000)= 0.5km X 0.5km X 1km

1,000 m

Burji KhalifaDubai, UAE(Year 2010)

Indian TowerMumbai, India(Year 2016)

Pingan IntenationalFinance Center

Shanghai, China(Year 2016)

Old Vacuum Tube：50W

1Tbit = 1012bitPower = 0.05kWX1012=50 TW

Nuclear Power Generator1MkW=1BW We need 50,000 Nuclear Power Plant for

just one 128 GB memory

In Japan we have only 54 Nuclear Power Generator

Last summer Tokyo Electric Power Company (TEPCO) can

supply only 55BW.

We need 1000 TEPCO just one 128 GB memory

Imagine how many memories are used in the world! 15

So progress of integrated circuits is extremely

important for power saving

Brain: Integrated Circuits

Hands, Legs：Power device

Stomach：PV device

Ear, Eye：Sensor

Mouth：RF/Opto device

Near future smart-society has to treat huge data.

Demand to high-performance and low power CMOS become much more stronger.

Semiconductor Device Market will grow 5 times in 12 years, even

though, it is very matured market!!

Gartner: By K. Kim, CSTIC 2012

300B USD

1,500B USD

2. Current status of Si-CMOS device technologies

Downsizing

Thus, important forDecreasing cost, power

Increasing performance21

Decreasing sizeDecreasing capacitance

(1970) 10 μm 8 μm 6 μm 4 μm 3 μm 2 μm 1.2 μm

0.8 μm 0.5 μm 0.35 μm 0.25 μm 180 nm 130 nm

90 nm 65 nm 45 nm 32 nm (28 nm ) 22 nm(2012)

Feature Size / Technology Node

From 1970 to 2013 (Last year)

18 generationsLine width: 1/450

Area: 1/200,000

43 years 1 generation2.5 years

Line width: 1/1.43 = 0.70

Area: 1/2 = 0.5

What is the problem problem for downsizing?

Question

The problem for downsizing

Ioff increase: Transistor cannot be turned‐off.

Ioff (Off‐leakage current) between S and D

1. Punch‐through between S and D

2. Direct‐tunneling between S and D

3. Subthreshold current between S and D

S and D distance small

Ion & Ioff increase

Gate oxide

Gate metal

Source Drain

1V0V0V

Substrate 0V DepletionRegion (DL)by Drain Bias

tox and Vdd have to be decreased for better channel potential control IOFF Suppression

0V < Vdep＜1V

0V < Vdep＜1VChannel

Large IOFF

Region governed By drain bias

Region governed by gate bias

tOX, Vdd thinning

DL touch with SRegion (DL)

Large IOFF

No tox. Vddthinning

Problem for downsizing

(Electron current)

There are solutions to suppress the depletion layer

1.Decrease supply voltage Very difficult

2.Decrease tox to enhance the channel potential controllability by gate bias

as explained later

3. Gate/channel configuration change to enhance the channel potential controllability by gate bias

Fin‐FET, ET‐SOI, etc.

Decrease tox

Increase the Electric field between Gate &Channel

Increase the channel potential controllability by gate bias.

Suppress the depletion layer

Keep channel potential 0V

LLgate gate and tand toxox(EOT) scaling trend(EOT) scaling trendA. Toriumi (Tokyo Univ), IEDM 2006, Short Course

Configuration change for channel and gate structures for better control of channel potential.

Fin‐FET, ET‐SOI, etc.

0V ＜V＜1V

Extremely Thin (or Fully-Depleted) SOI

Planar ET (or FD) SOI31

Extremely thin Si

Drain bias induced depletion

- Make Si layer thin- Control channel potential also from the bottom

0V ＜V＜1V

Surrounding gate structure (Multiple gates)

Planar Multi gate32

Si fin or nanowire

Drain bias induced depletion

- Make Si layer thin- Control channel potential also by multiple gates

not only from top & bottom but maybe also from side

Fin Tri-gate(Variation)

Ω-gate All-around

GNanowire structures in a wide meaning

Tri-gate

Our work at TIT: Our work at TIT: ΩΩ--gate Si Nanowiregate Si NanowireS. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.010-12

Gate Voltage (V)

pFET nFET

Vd=-50mV

Vd=-1V

Vd=50mV

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.010-12

Gate Voltage (V)

pFET nFET

Vd=-50mV

Vd=-1V

Vd=50mV

0 0.5 1 1.5 2ION (mA/µm)

Lg=65nm

0 0.5 1 1.5 2ION (mA/µm)

Lg=65nm

Poly-Si

SiNSiN

・Conventional CMOS process

・High drive current

(1.32 mA/µm @ IOFF=117 nA/µm)

・DIBL of 62mV/V and SS of 70mV/dec for nFET 34

2. Direct‐tunneling between S and D

Wave function of electron penetrates the channel potential barriers by quantum mechanical physics, when the channel length is around 3 nm.

Tunnelingdistance

Source DrainChannel

Direct‐tunnelcurrent

There is no solutions!

Downsizing limit is @ Lg = 3 nm.

Vth (Threshold Voltage)

SubthreshouldLeakage Current

Subtheshold leakage current of MOSFET

Subthresholdregion

Vg (V)1

0.5 V 1.0 V

Id (A/µm)

0.15 V

Subthreshold leakage current

Electron EnergyBoltzmann statics

Exp (qV/kT)

Lg 1/2

Vd, Vg 1/2Vth 1/2

Ioff 103 in this exampleHowever

Because of log-linear dependence

Vth (Threshold Voltage)

SubthreshouldLeakage Current

Subtheshold leakage current of MOSFET

Subthreshold CurrentIs OK at Single Tr. level

But not OKFor Billions of Trs.

Subthresholdregion

Solution: however very difficult

Keep Vth as high as possible‐ Do not decrease supply voltage, Vd

‐ Suppress variability in VthHowever, punchthough enhanced

Thus, subthreshold current will limit the downsizing, especially for mobile devices

42Subthreshold Leakage (A/µm)

Source: 2007 ITRS Winter Public Conf.

The limit is deferent depending on application

How far can we go for production?

10µm 8µm 6µm 4µm 3µm 2µm 1.2µm 0.8µm 0.5µm

0.35µm 0.25µm 180nm 130nm 90nm 65nm 45nm 32nm

(28nm) 22nm 14nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm?

Past 0.7 times per 2.5 years

Now Future

・At least 4,5 generations to 8 ~ 5 nm

Intermediatenode

Direct-tunnelSubthresholdpunchthrough

Limit depending on applications

Fundamentallimit

However, careful about the name of technology!

22 nm Technology by Intel

Lg (Gate length) = 30 nm (HP), 34 nm (MP), 34 nm or larger (SP)

IEDM 2012, VLSI 2013

10 nm Technology by Leti (FD-SOI)

Lg (Gate length) = 15 nm

ECS 2013

Recently, Gate length (Lg) is much larger than the Technology name

The rate for the shrinkage for the gate length and line pitch will be larger than 0.7 in near future, because of the subthreshold leakage, and also because of the delay in EUV lithography.

As a result, we will have more technology generations until reaching the downsizing limit,and the time to reach the limit will be delayed.

HP MP SP

TOX,E (nm) 0.9 0.9 0.9

LGATE (nm) 30 34 34

IOFF (nA/um) 20-100 5-20 1-5

Tri-gate has been implemented since 22nm node, enabling further scaling

C. Auth et al., pp.131, VLSI2012 (Intel)

TriTri--gate implementation for transistors gate implementation for transistors

Thus, we may go down to “5 nm”technology by choozing whatever gate length we want for the application.

More Moore to More More MooreMore Moore to More More Moore

65nm 45nm 32nm

Technology node

M. Bohr, pp.1, IEDM2011 (Intel)P. Packan, pp.659, IEDM2009 (Intel)C. Auth et al., pp.131, VLSI2012 (Intel)T. B. Hook, pp.115, IEDM2011 (IBM)S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)

Lg 35nm Lg 30nm

(Fin,Tri, Nanowire)

22nm 15nm, 11nm, 8nm, 5nm, 3nm

Alternative (III-V/Ge) Channel FinFET

Emerging Devices

Tri-Gate

Now Future

Si channelSi

Others

(ETSOI)Planar

Si is still main stream for future !! ET: Extremely Thin28nm

HighHigh--k gate dielectricsk gate dielectrics

Continued research and development

SiO2 IL (Interfacial Layer) is used at Si interface to realize good mobility

Technology for direct contact of high-k and Si is necessary

Remote SiO2-IL scavengingHfO2 (IBM)

EOT=0.52 nm

La-silicate

Direct contact with La-silicate (Tokyo.Tech)

T. Ando, et al., p.423, IEDM2009, (IBM) T. Kawanago, et al., T-ED, vol. 59, no. 2, p. 269, 2012 (Tokyo Tech.)

K. Mistry, et al., p.247, IEDM 2007, (Intel)

EOT=0.9nmHfO2/SiO2(IBM)

T.C. Chen, et al., p.8, VLSI 2009, (IBM)

Hf-based oxides

45nmEOT:1nm

32nmEOT:0.95nm

22nmEOT:0.9nm

15nm, 11nm, 8nm, 5nm, 3nm,

K. Kakushima, et al., p.8, IWDTF 2008, (Tokyo Tech.)

EOT=0.37nm EOT=0.40nm EOT=0.48nm

0.48 → 0.37nm Increase of Id at 30%49

Now, Ion/Ioff ratio is typically 106.

However, it degrades significantly with decrease in Vsupply.

Rather than Ioff value, Ion/Ioff ratio is important.

[a] C. Auth et al., pp.131, VLSI2012 (Intel).[b] K. Mistry et al., pp.247, IEDM2007 (Intel).[c] H.-J. Cho et al., pp.350, IEDM2011 (Samsung).[d] S. Saitoh et al., pp.11, VLSI2012 (Toshiba).[e] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM).

[f] T. Yamashita et al., pp.14, VLSI2011 (IBM).[g] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).

IIONON and Iand IOFFOFF benchmarkbenchmark

[h] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics).[i] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)[j] K. Cheng et al., pp.419, IEDM2012 (IBM)

0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2ION [mA/µm]

Intel [a]Bulk 32nmVDD=0.8V

Intel [a]Tri-Gate 22nmVDD=0.8V

Intel [b]Bulk 45nmVDD=1V

Toshiba [d]Tri-Gate NWVDD=1V

Samsung [c]Bulk 20nmVDD=0.9V

IBM [5]GAA NWVDD=1V

IBM [g]FinFET 25nmVDD=1V

IBM [g]ETSOIVDD=0.9V

IBM [g]ETSOIVDD=1V

STMicro. [h]GAA NWVDD=0.9V

Tokyo Tech. [i]Ω-gate NWVDD=1V

IBM [j]ETSOIVDD=0.9VIeff

0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6ION [mA/µm]

PMOSIntel [a]Bulk 32nmVDD=0.8V

Intel [a]Tri-Gate 22nmVDD=0.8V

Intel [b]Bulk 45nmVDD=1V

IBM [g]ETSOIVDD=1VSamsung [c]

Bulk 20nmVDD=0.9V

IBM [e]GAA NWVDD=1V

IBM [f]FinFET 25nmVDD=1V

IBM [g]ETSOIVDD=0.9V

IBM [j]ETSOIVDD=0.9VIeff

Nanowire/Tri gate MOSFETs have advantage not only suppressing Ioff, but also for increasing Ion over planer MOSFETs

1. Because of higher mobility due to lower vertical electric field

2. Because of higher carrier density at the round corner

0 .E + 0 0

1 .E + 1 9

2 .E + 1 9

3 .E + 1 9

4 .E + 1 9

5 .E + 1 9

6 .E + 1 9

0 2 4 6 8Distance from SiNW Surface (nm)

6543210

角の部分

平らな部分

電子濃度(x1019cm-3)Electron Density

Edge portion

Flat portion

SiNW Band structure calculation

Cross section of Si NW

[001] [011] [111]D=1.96nm D=1.94nm D=1.93nm

First principal calculation,

Si nanowire FET with 1D Transport[001] [011] [111]0.86 0.94 0.89

OrientationDiameter (nm)

[001] [011] [111]3.00 3.94 1.93

OrientationDiameter (nm)

ZG G GZ ZWave Number

Small mass with [011]

Large number of quantum channels

with [001]

10 nm diameter Si(100)NW（ 2341 atoms）

20 nm diameter Si(100)NW （ 8941 atoms ）

Atomic models of a Si quantum dot and Si nanowires

6.6 nm diameter SiQD（ 8651 atoms）

( , , ) ( , , )n m nm

x y z C x m x y zxψ ψ

∂≈ + ∆

∂ ∑

1( ) ( ) ( ) ( )

m n m i n ii

d x y zψ ψ ψ ψ=

≈ ∆ ∆ ∆∑∫ r r r r r

Real-Space Finite-DifferenceSparse Matrix

FFT free (FFT is inevitable in the conventional plane-wave code)

Kohn-Sham eq. (finite-difference)

3D grid is divided by several regionsfor parallel computation.

Higher-order finite difference

Integration

MPI_ISEND, MPI_IRECV

MPI_ALLREDUCE

RSDFT – suitable for parallel first-principles calculation -

MPI ( Message Passing Interface ) library

)()()(ˆ)]([21 2 rrrr nnn

PPnlocs vv φεφρ =⎟

⎠⎞

⎜⎝⎛ ++∇−

CPU8CPU7CPU6

CPU5CPU4CPU3

CPU2CPU1

Higher-order finite difference pseudopotential methodJ. R. Chelikowsky et al., Phys. Rev. B, (1994)

|Vnew-Vold|^2

50403020100iteration

onvergence behavior for Si10701H1996

e.g.) The system over 10,000 atoms → Si10701H1996(7.6 nm diameter Si dot)

Massively Parallel Computing

Computational Time (with 1024 nodes of PACS-CS)

6781 sec. × 60 iteration step = 113 hour

Based on the finite-difference pseudopotential method (J. R. Chelikowsky et al., PRB1994)

Highly tuned for massively parallel computers

Computations are done on a massively-parallel cluster PACS-CS at University of Tsukuba.

(Theoretical Peak Performance = 5.6GFLOPS/node)

with our recently developed code “RSDFT”

Iwata et al, J. Comp. Phys., to be published.Real-Space Density-Functional Theory code

(RSDFT)

Grid points = 3,402,059Bands = 22,432

-12 -10 -8 -6 -4 -2 0 2(eV)

-10 -8 -6 -4 -2 0 2 4 6(eV)

Structure and DOS of Si(100)NWs (D=1nm, 4nm, and 8nm)

D = 4 nmSi341H84（425 atoms)KS band gap = 0.81eV

D=4nm D=8nmD=1nm

D=8 nmSi1361H164 (1525 atoms)

KS band gap=0.61eV

D=1 nmSi21H20（41 atoms)

KS band gap=2.60eV

KS band gap of bulk (LDA) = 0.53eV

Band structure of 8-nm-diameter Si nanowire near the CBM

0.300.250.200.150.100.050.00

S band gap = 0.608 eV (@Γ)

82 meV (96 meV)

Each band is4-dgenerate. 23 meV (24 meV)

)()()(22 2

rr Φ−=Φ⎥⎦

⎤⎢⎣

∂∂

−⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

+∂∂

− CBMlt zmyxm

εεhh

Effective mass equation

The band structure can be understood thatelectrons near the CBM in the bulk Si are

Confined within a cylindrical geometry.

Si12822H1544（14,366 atoms）･10nm diameter、3.3nm height、(100)･Grid spacing：0.45Å (~14Ry)･# of grid points：4,718,592･# of bands：29,024

･Memory：1,022GB～2,044GB

Si12822H1544

Top View Side View

Si nano wire with surface roughness

SiNW Band compact model

Landauer Formalism for Ballistic FET

From xmax to xmin

[ ][ ]∑

⎭⎬⎫

⎩⎨⎧

−+−+

⎟⎟⎠

⎞⎜⎜⎝

BD TkE

TkEgqTkGI

/)(exp1/)(exp1ln

xO xmax xmin

Energy

µSµD

0 0.1 0.2 0.3 0.4 0.5

Drain Bias (V)

Current (uA)

IV Characteristics of Ballistic SiNW FET

T=1KT=300K

Vg-Vt=1.0 V

0.05 V

Small temperature dependency35µA/wire for 4 quantum channels

Model of Carrier Scattering

ChannelOpticalPhonon

Initial ElasticZone

Optical PhononEmission Zone

ε~kBT

Source

TransmissionProbability : Ti

Elastic Backscatt.Elastic Backscatt.

＋（Optical Phonon Emission）

Linear Potential Approx. ： Electric Field E

TransmissionProbability

to Drain

To Drain

0Drain fromInjection )0()0()0()(

=⎟⎟⎠

⎞−=

FGFT ε

Résumé of the Compact Model

bfStG C

−−−

µµα

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

ttrttr

0 1 1 ( ( ))( ) ( ) ( )1 exp 1 exp 1 exp

f b i i ii i S i S i D

q dkQ Q g T k dkk k kk T k T k T

επ ε µ ε µ ε µ

−∞ −∞

⎤⎡ ⎧ ⎫⎥⎢ ⎪ ⎪

⎪ ⎪ ⎥⎢+ = − −⎨ ⎬ ⎥⎢ ⎧ ⎫ ⎧ ⎫ ⎧ ⎫− − −⎪ ⎪+ + + ⎥⎢ ⎨ ⎬ ⎨ ⎬ ⎨ ⎬⎪ ⎪⎢ ⎥⎩ ⎭ ⎩ ⎭ ⎩ ⎭⎣ ⎩ ⎭ ⎦

∑ ∫ ∫

⎟⎠⎞

⎜⎝⎛ +

επDDS qV=− µµ

Unknowns are ID, (µS-µ0), (µD-µ0), (Qf+Qb)

[ ]( , ) ( , )i s D ii

qI g f f T dε µ ε µ επ

= −∑ ∫h

00 0 0 0 0

qExB D D qE mD Bε

=+⎛ ⎞+ + + ⎜ ⎟

⎝ ⎠

PlanarGate

GAA(Electrostatics requirement)

(Carrier distributionin Subbands)

I-VD Characteritics (RT)

Electric current ２０～25 µANo satruration at Large VD

0 0.1 0.2 0.3 0.4 0.5 0.6

Drain Bias [V]

Current [uA]

VG-Vt=0.1V,Bal.

VG-Vt=0.1V,Qbal

VG-Vt=0.4V,Bal.

VG-Vt=0.4V,Qbal.

VG-Vt=0.7V,Bal.

VG-Vt=0.7V,Qbal.

VG-Vt=1.0V,Bal.

VG-Vt=1.0V,Qbal.

Size and Corner Effects on Electron Mobility of Rectangular Silicon Nanowire MOSFETs

Introduction

(L. Sekaric et al., Appl. Phys. Lett., 2009)

(J. Chen et al., IEDM, 2008)

To analysis deviation from facet-driven operation,We investigate size and corner effects in the rectangular Si NW MOSFETs

Experimental results showed a drastic mobility increase in width <

Expectation in facet-driven operation

Simulation methods

Using the parabolic EMA, we self-consistently solved 2D Schrödinger and Poisson equations in equilibrium

Using the Kubo-Greenwood formula (low-field limit), we calculated phonon-scattering-limited mobility (R. Kotlyar et al., APL, 2004 / S. Jin et al., JAP,2007)

Subband structure, Eµ, and wave function, Ψµ,

[ ]∫∞

−=µ

µµµµ

µ ρτµE

dEEfEfEEvETkn

q )(1)()()()( 2

∑′

′′=µ

µµµηηµ

ρδρ

πτ i

B FEugTkΞ

E ,,2Si

ac )()(

∑′

′′′ ⎟⎠⎞

⎜⎝⎛ +

−±−

µµµηηµ

ωωρ

ωρπ

)(1)(1

FEggKD

∫∫ ′′ = dxdyyxΨyxΨF22

, ),(),( µµµµForm factor

Intrasubbandscattering rate

Intersubbandscattering rate

Materials

[100]/(100) Si NW

[110]/(100) Si NW

[110]/(110) Si NW

Wafer orientationWire direction

Rectangular Si NW MOSFETs with various orientations

To take into account arbitrary direction, effective mass tensor needs to be re-expressed in each coordinate system (M. Bescond et al., Nanotechnol.,

⎟⎟⎟

⎜⎜⎜

⎛=−

/1000/1000/1

Example effective mass tensor:Red valley of [100]/(100) Si NW

y zx[010]

Constant energy surface

tox = 1 nmnon-doped channelno interface statesNinv = 0.8 x 1013 /cm2

GateSiO2

Result 1: Cross-sectional electron density

Electron density (/cm

w = 14 nm 6 nm 3 nm

･ Corner and side electron distributions hardly depend on size when w > 6 nm

(100)(1

[100]/(100) Si NW

[110]/(100) Si NW

[110]/(110) Si NW

0 2 4 6 8 10 12 14 16

2 /V･s

Width (nm)

Result 2: Size-dependent mobility[100]/(100)

[110]/(100)

[110]/(110)

･ Mobility does not drastically change in width larger than 10 nm(we could not explain the drastic mobility increase in the experimental results)

h = 10 nm

Now, we discuss the corner effect based on specially resolved mobility analysis

･When w < 6 nm, mobility is drastically changed by the increase in form factor and change of electron structure

Spatially resolved mobility analysis

),(),(

local yxn

nyxΨyx

∑= µ

µµµ µµ

･ Mobility for each subband, µµ, is spatially independent

･ Local mobility shows spatially different contribution of each subband

∑=µ

µµ nyxΨyxn2

),(),(

Mobility (cm

2/V･s)

w = 14 nm 6 nm 5 nm 4 nm 3 nm

･We can distinguish orientation and corner effects based on the spatially resolved mobility analysis･ Corner mobility is always lower than the (100)-surface mobility.

Result 3: Cross-sectional spatially resolved mobility

(100)[10

[100]/(100) Si NW

[110]/(100) Si NW

[110]/(110) Si NW

x (nm)y (nm)

Local mobility, µlocal(x,y) (cm2/V⋅ s)

Corner Side

Discussion 1: Corner effectElectron density Local mobility

Corner mobility is lower than side mobility

Velocity & scattering rate

he large ratio of corner electrons belongs to the 2nd Subband, which shows lower velocity and higher scattering rate

Subband occupancy ratio

x 1019

x (nm)y (nm)

Electron density, n(x,y) (/cm3)

Corner

Corner Side

x 1020

Others

1st subband group

2nd subband group

-0.04 -0.02 0 0.02 0.040

E - Efn (eV)

Group velocity, vµ (cm/s) (b)

-0.04 -0.02 0 0.02 0.040

E - Efn (eV)

Scattering rate, 1/τ µ (/s) (c)

1st 2nd

Discussion 2: Origin of different contribution between subbands

The large ratio of corner electrons belongs to the 2nd

Subband group

Corner Side

x 1020

Others

1st subband group

2nd subband group

Subband occupancy ratio

x 1013

x (nm)y (nm)

Probability density (/cm2)

x 1013

x (nm)y (nm)

Probability density (/cm2)

(b) 2nd subband group

(a) 1st subband group

Probability density

Probability density of the 2nd subband group with high energy is localized at

cornerbecause wave function within rapidly varying potential at corner could be

represented by high energy plane wave function basis

Velocity and Form Factor

･ Velocity increases with occupancy of the ground subband with small effective mass･ Scattering rate increases with increasing form factor

Trade-off in width dependence

0 2 4 6 8 10 12 14 16

2 /V･s

Width (nm)

[100]/(100)

[110]/(100)

[110]/(110)

h = 10 nm

0 2 4 6 8 10 12 14 16Width (nm)

[100]/(100)

h = 10 nm

2 /V･s

0 2 4 6 8 10 12 14 16Width (nm)

[100]/(100)

h = 10 nmSca

tterin

We investigated the size-dependent phonon-scattering-limited mobility of rectangular Si NW MOSFETs

The drastic increase in mobility from experimental results could not be explained by size and corner effects (strain could cause the drastic

increase in mobility)

When w < 6 nm, the mobility drastically modulated

According to the specially resolved mobility analysis, the corner mobility was lower than the side mobility

Paper with respect to a part of thisY. Lee, K. Kakushima, K. Natori, and H. Iwai, “Corner effects on phonon-limited mobility in

rectangular silicon nanowire metal-oxide-semiconductor field-effect transistors based on spatially resolved mobility analysis,” J. Appl. Phys., Vol. 109, Issue 11, pp. 113712-1–113712-5, June 2011.

Modeling of Quasi-Ballistic Transport in Nanowire MOFSETs

A part of this work has been conducted with group of Prof. Giorgio Baccarani at University of Bologna

Quasi-ballistic transport

M. Lundstrom (EDL, 1997) modeled the quasi-ballistic transport with the kT layer

E. Gnani et al. (TED, 2008) and K. Natori (JJAP, 2009) modeled the quasi-ballistic transport with only elastic scattering

K. Natori (JJAP, 2009 / TED, 2011) modeled the quasi-ballistic transport both welastic and inelastic scatterings

R: Backscattering coefficientλ0: Mean free pathLkT: kT-layer length

K. Natori (JAP, 1994) modeled the ballistic MOSFET operation

(However, the scattering theory with kT layer has not been clearly postulated)

We develop a comprehensive model of the quasi-ballistic transport based on Natori’s model

As the MOSFET is extremely downscaled, diffusive transport changes to quasi-ballistic transport

Natori’s model for quasi-ballistic transport

Dividing the channel into two zones: elastic zone and relaxation zone

Elastic zone

Relaxation zone

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−−

−=⎟⎟

⎞⎜⎜⎝

⎛−

)0()0(

Scattering matrix

where (from BTE)

ħωε

),(),()(1

),(),()](21[)(

),0(),0()(

εεε

zfzfRR

−+==

ελε

e 1),(),(

⎟⎟⎠

⎞⎜⎜⎝

⎛−+≈+

(endless drain)

Concept of this studyDividing the device into five zones:source zone, barrier zone, elastic zone, relaxation zone, drain zone

ħωε

0 z0 ze zr zd

Source zone

Drain zone

Elastic zone

Relaxation zone

Barrier zone

･ Adopted elastic scattering is intravalley acoustic phonon (AP) scattering･ Si NW MOSFET is adopted to consider 1D transport

･ Adopted inelastic scattering is g3- and f3-type optical phonon (OP) scattering･ OP energies are set to 63 meV

One-flux scattering matrix

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−−

=⎟⎟⎠

⎞⎜⎜⎝

⎛−

RRRRTT

f+(z1)R1

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛=⎟⎟

⎞⎜⎜⎝

⎛−

f–(z2)

f+(z2)f–(z1)

Expression with one-flux scattering matrices∫ −+ −= εεε

πdzfzfqI )],(),([ 00

Flux between z0 and zd

)(1))(()()1(

2121111211

2121212121211121

rrrrdedrre

rrrreeeeeeeerdre

RRTTRRRRRRRRTTRRTTRRTTRRRRR

−−−−−−+−+−

)(1 2121111211

rrrrdedrre

RRTTRRRRRRTTTT

−−−−≡

Flux between 0 and z0

Simultaneously solving them, f+(z0) and f-(z0) are described by Rs, Ts, fS, and fD

Solving BTE for each zone, we can derive Rs and Ts

ħωε

0 z0 ze zr zd

Source zone

Drain zone

Elastic zone

Relaxation zone

Barrier zone

212122

bbbbsbS RR

RRTTRRR

−−−

bsS RR

−≡

TfRRRT

11)( 0)()( 00 zfRfTzf SSS

−+ +=

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−−

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

=⎟⎟⎠

⎞⎜⎜⎝

⎛−−

)0(111

)()( S

2s2s1s2s1s

2b2b1b2b1b

RRRRTT

TTzfzf

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−−

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

=⎟⎟⎠

⎞⎜⎜⎝

⎛−

1111)z(

2e2e1e2e1e

2r2r1r2r1r

d2d2d1d2d1

d2r2e2D

RRRRTT

ħωε

0 z0 ze zr zd

Source zone

Drain zone

Elastic zone

Relaxation zone

Barrier zone

Rb1,2 and Tb1,2 for barrier zone

where AP scattering only

If potential is given, we can calculate R and T

),(),(

1),(),(

1),( εελ

εελ

ε zfz

−=−

),(),(

1),(),(

1),( εελ

εελ

ε zfz

+−−

)()( 21 z

ελεε

)(1)()( 121 εεε bbb RTT −==

Barrier zone is substantially short

)]()([4),(),(21

101 zEzEmS

zzvzac

acac −+=≡

επετεελ h

ħωε

0 z0 ze zr zd

Source zone

Drain zone

Elastic zone

Relaxation zone

Barrier zone

Re1,2 and Te1,2 for elastic zone

where AP scattering only

),(),(

1),(),(

1),( εελ

εελ

ε zfz

−=−

),(),(

1),(),(

1),( εελ

εελ

ε zfz

+−−

)()( 21

ελεε

)(1)()( 121 εεε eee RTT −==

)]()([4),(),(21

101 zEzEmS

zzvzac

acac −+=≡

επετεελ h

Validation of the approximation in elastic zone

Scattering rate under equilibrium (d = 3 nm, nondegenerate)

･ OP scattering can be neglected below the 63 meV

0 0.05 0.1 0.150

15x 10

ε (eV)

tterin

AP only

AP + OP

Rr1,2 and Tr1,2 for relaxation zone (1)

where AP + OP (emission only)

We approximate U(z0) + ε – U(z) >> ħω, to analytically solve BTE

To avoid excessive relaxation in degenerate system

)(),( ωεωε hh −≈−+Dfzf

)(),( ωεωε hh −≈−−Dfzf

ħωε

0 z0 ze zr zd

Source zone

Drain zone

Elastic zone

Relaxation zone

Barrier zone

),(),(

2/)],(),([1),(),(

1),(),(

1),( εελ

ωεωεεελ

εελ

ε zfz

zfzfzfz

opacac

−++ −+−−

+−=−hh

),(),(

2/)],(),([1),(),(

1),(),(

1),( εελ

ωεωεεελ

εελ

ε zfz

zfzfzfz

opacac

−−+

+−− −+−−

+−=hh

)]()([(2])()()][()([2),(),(1

101101101 zEzEmS

zEzEzEzEmS

zzvzopop

opop −+≈

−−+−+=≡

επωεεπετεελ hhh

)]()([4),(),(21

101 zEzEmS

zzvzac

acac −+=≡

επετεελ h

Rr1,2 and Tr1,2 for relaxation zone (2)

⎟⎟⎠

⎞⎜⎜⎝

⎛+−⎟⎟

⎞⎜⎜⎝

⎛−+−⎟⎟

⎞⎜⎜⎝

⎟⎟⎠

⎞⎜⎜⎝

⎛+−−

XXXXXX

),(122exp

),(122exp1

ελεε

⎟⎟⎠

⎞⎜⎜⎝

⎛+−⎟⎟

⎞⎜⎜⎝

⎛−+−⎟⎟

⎞⎜⎜⎝

⎟⎟⎠

⎞⎜⎜⎝

⎛+−−+

XXXXXX

XXXXTT

),(122exp

),(122exp22

ελεε

)](1[ ωε h−−≡ Dac

op fSS

Rs2,d2 and Ts1,d1 for source and drain zones (1)

Where (for source zone)

AP + OP (both in- and out-scattering)

Constant potential

To avoid excessive relaxation in the degenerate system

)(),( ωεωε hh −≈−+Sfzf

)(),( ωεωε hh −≈−−Sfzf

ħωε

0 z0 ze zr zd

Source zone

Drain zone

Elastic zone

Relaxation zone

Barrier zone

)],(1[/),(

2/)],(),([),(),(

2/)],(),([1),(),(

1),(),(

1),( εελ

ωεωεεελ

εελ

ε zfSSz

zfzfzfz

opopopopacac

−′−+−

−−+−−

+−=−hhhh

)],(1[/),(

2/)],(),([),(),(

2/)],(),([1),(),(

1),(),(

1),( εελ

ωεωεεελ

εελ

ε zfSSz

zfzfzfz

opopopopacac

−−+

+−−

−′−+−

−−+−−

+−=hhhh

)](1)[(),()](1)[(),( εωεεωεεε SSopSSop ffzSffzS −−=−−′hh

Detailed balance conditionTo apply appropriate in-scattering rate

])([4)(1

acsacac EzE

mSz −+

≡≈επελελ h

])(][)([2)(1

opsopop ωεεπελελ hh −−+−+

≡≈EzEEzE

Modified BTE

We can calculate R and T from length of source and drain

Rs2,d2 and Ts1,d1 for source and drain zones (2)

)(1),(

ελε

ελελε

zfzfdzzdf

−−⎟⎟⎠

⎞⎜⎜⎝

⎛+=− −+

)(1),(

ελε

ελελε

zfzfdzzdf

−−⎟⎟⎠

⎞⎜⎜⎝

⎛+= +−

− )](1)[()(1

Ssout εελ

ωεελ f

f−−−

)](1)[()()](1[

SSsin εελ

εωεελ f

−−≡

)(2exp

)(2exp1)(2

ελε

−−

−−=

)(1)( 21 εε ss RT −=

Drain zone

)(2exp

)(2exp1)(1

ελε

−−

−−=

)(1)( 12 εε dd RT −=2d

outdout

dac )]([

2)(ελελελ

ε +≡dY

sac )]([

2)(ελελελ

ε +≡sY

Source zone

With the same process

Summary of derived Rs and Ts

Elastic zone

Relaxation zone

Barrier zone

Source zone

)()( 21 z

ελεε

)(1)()( 121 εεε bbb RTT −==

)()( 21

ελεε

)(1)()( 121 εεε eee RTT −==

⎟⎟⎠

⎞⎜⎜⎝

⎛+−⎟⎟

⎞⎜⎜⎝

⎛−+−⎟⎟

⎞⎜⎜⎝

⎟⎟⎠

⎞⎜⎜⎝

⎛+−−

XXXXXX

),(122exp

),(122exp1

ελεε

⎟⎟⎠

⎞⎜⎜⎝

⎛+−⎟⎟

⎞⎜⎜⎝

⎛−+−⎟⎟

⎞⎜⎜⎝

⎟⎟⎠

⎞⎜⎜⎝

⎛+−−+

XXXXXX

XXXXTT

),(122exp

),(122exp22

ελεε

)](1[ ωε h−−≡ Dac

op fSS

)(2exp

)(2exp1)(2

ελε

−−

−−=

)(1)( 21 εε ss RT −=

sac )]([

2)(ελελελ

ε +≡sY

whereDrain zone ( )

)(2exp

)(2exp1)(1

ελε

−−

−−=

)(1)( 12 εε dd RT −=

dac )]([

2)(ελελελ

ε +≡dY

)](1)[()(1

Ssout εελ

ωεελ f

f−−−

)]()([4),(1

0 zUzUmS

ac −+≡

επελ h

)](1)[()(1

Ddout εελ

ωεελ f

f−−−

])([4)(1

acdac EzE

mS−+

≡επελ h

])(][)([2)(1

opdop ωεεπελ hh −−+−+

≡EzEEzE

])(][)([2)(1

opsop ωεεπελ hh −−+−+

≡EzEEzE

])([4)(1

acsac EzE

mS−+

≡επελ h

-0.4-0.35-0.3

-0.25-0.2

-0.15-0.1

-0.050

0 10 20 30 40 50

Validation by a numerical simulation

Importing self-consistent potential, Rs and Ts are semi-analytically calculated in our model

Position (nm)

)d=3nm (1D-like transport)Ls=10nmLg=30nmLd=10nmVg–Vt=0.3VVd=0.3V

We compare the results from our model and the numerical simulation based on the deterministic solution of 1D MSBTE

Example of self-consistently calculated potential profile

Numerical simulation based on the deterministic solution of 1D MSBTE

Longitudinal BTE: fµ

Charge calculation: n

Poisson eq.: U

Convergence check

Transverse Schrödinger eq.: Eµ, Rµ

Deterministic solution of 1D MSBTE is more efficient than1D MSMC in the low

dimensionality of the nanowire

Results are the same as those from 1D MSMC

Cylindrical coordinate system

Validation 1: Backscattering coefficient

AP only

This model

･ This model is in good agreement with the numerical simulation especially below 63 meV

Numerical simulation

0 0.05 0.1 0.15 0.2ε (eV)

Saturation regionVg – Vt = 0.3 V

Vd = 0.3 V

0 0.05 0.1 0.15 0.2ε (eV)

Subthreshold regionVg – Vt = 0.0 V

Vd = 0.3 V

0 0.05 0.1 0.15 0.2ε (eV)

Saturation region and long drainLd = 100 nm

Vg – Vt = 0.3 VVd = 0.3 V

･ Modeling for drain zone is available even in substantially long drain

Validation 2: Carrier distribution function at z0

･ Distribution function at the top of the barrier taken into account

･ Modeling of source zone is available even in substantially long source

0 0.1 0.20

00.10.2ε (eV)

tion Solid lines: This model

Symbols: Numerical simulation

f+(z0,ε)f–(z0,ε)

Dotted line: fS(ε)

00.10.2ε (eV)

0 0.1 0.2

f+(z0,ε)f–(z0,ε)

Solid lines: This modelSymbols: Numerical simulation

Dotted line: fS(ε)

Long sourceLs = 100 nmVg – Vt = 0.0 VVd = 0.3 V

Saturation regionLs = 10 nmVg – Vt = 0.3 VVd = 0.3 V

Validation 3: I-V characteristics

･ This model is in quantitatively good agreement with the numerical simulation

012345678

0 0.1 0.2 0.3 0.4 0.5

V g– V t

Vg – Vt = 0.0 V

Drain voltage (V)

nt (µ

Numerical simulation

This model

Linear potential

Lg LdLs

Source

Channel

z0 zr zd

Discussion 1: Potential profile to investigate quasi-ballistic transport

･ R(ε) can be analytically derived

･ Us and Ud are self-consistently calculated with donor impurity density

･ To calculate drain current, we need numerical integration over energy

0 50 100 150Gate length (nm)

listic

d = 3 nmLs = 10 nmLd = 1 nmVd = 0.3 VU(z0) = Efs

0 50 100 150Drain length (nm)

listic

d = 3 nmLs = 10 nmLg = 1 nmVd = 0.3 VU(z0) = Efs

Discussion 2: Ballisticity

Ballisticity vs. Lg Ballisticity vs. Ld

･When Ld > 50 nm, 20 % is backscattered from drain zone

･ Considering realistic 1D drain, we can not obtain ‘ballisticity = 1’

･When Lg = 10 nm, 20 % is backscattered

0 50 100 150Source length (nm)

nt (µ

d = 3 nmLg = 10 nmLd = 10 nmVd = 0.3 VU(z0) = Efs

This modelAP only

0 50 100 150Source length (nm)

nt (µ

d = 3 nmLg = 10 nmLd = 10 nmVd = 0.3 VU(z0) = Efs

This modelAP only

Discussion 3: Source length dependence

･When Ls < 10 nm, elastic source approximation is available

･ In a shorter 1D source, the resistivity seems to be smaller

0 20 40 60Gate length (nm)

d = 3 nmLs = 10 nmLd = 10 nmVd = 0.3 VU(z0) = Efs

This modelNatori’s model

AP only

nt (µ

Discussion 4: Comparison with other models (1)

･ In Lg > 50 nm, Natori’s model is in good agreement with this model

･ In Lg < 10 nm, elastic approximation is in good agreement with this model

Drain current vs. gate length

Discussion 5: Comparison with other models (2)

･ Elastic approximation could not describe backscattering in long drain

･ In Lg > 100 nm, Natori’s model is in good agreement with this model

0 50 100 150Drain length (nm)

nt (µ

d = 3 nmLs = 10 nmLg = 10 nmVd = 0.3 VU(z0) = Efs

This modelNatori’s modelAP only

Drain current vs. drain length

Advantages of this model

ħωε

0 z0 ze zr zd

Source zone

Drain zone

Elastic zone

Relaxation zone

Barrier zone

･ Describing distribution function of the carrier injected from realistic source

･ Describing transmission coefficient for the carriers injected from drain

･ Taking into account finite length of drain and source as well aschannel

- Device is divided into five zones

･We have successfully modeled the quasi-ballistic transport in nanowire MOSF

- Backscattering coefficient, distribution function, and drain current were derived with one-flux scattering matrix and BTEs

･ Results from this model were in good agreement with those from anumerical simulation

･ 1D drain length was important to adjust backscattering coefficient

･ 1D source length was also important to represent distribution of the carriers injected from realistic source

Conclusions

- We successfully modeled the gate capacitance to distinguish different contributions of the quantum effects- The decrease in xavg caused the positive effect on the total capacitance

- We showed the effects of the size-dependent properties on performance- Desirable diameter could be around 5 nm

- We can suppress effective mass fluctuation by adopting square cross section

- We successfully developed the quasi-ballistic transport model of NW MOSFETs- Ls and Ld were also important to estimate the drain current

- Size and corner effects without strain could not cause the drastic mobility increase from experimental results- In width < 6 nm, mobility drastically modulated

By modeling gate capacitance and quasi-ballistic transport,we could interpret device physics

By numerical simulation, we investigatedwhat parameter control performance in ultra-scaled NW MOSFETs

SiNW FET Fabrication

Sacrificial Oxidation

SiN sidewall support formation

Ni SALISIDE Process (Ni 9nm / TiN 10nm)

S/D & Fin Patterning

Gate Oxidation & Poly-Si DepositionGate Lithography & RIE EtchingGate Sidewall Formation

Oixde etch back

Standard recipe for gate stack formationBackend

(a) SEM image of Si NW FET (Lg = 200nm) (b) high magnification observation of gate and its sidewall.

Fabricated SiNW FET

Poly-Si

SiN support

Lg=65nm, Tox=3nm

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

-1.0 -0.5 0.0 0.5 1.00

10 20 30 40 50 60 70

nt (µ

Drain Voltage (V)

Vg-Vth=1.0 V

Vg-Vth= -1.0 V

Gate Voltage (V)

pFET nFET

Vd=-50mV

Vd=-1V

Vd=50mV

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

-1.0 -0.5 0.0 0.5 1.00

10 20 30 40 50 60 70

nt (µ

Drain Voltage (V)

Vg-Vth=1.0 V

Vg-Vth= -1.0 V

Gate Voltage (V)

pFET nFET

Vd=-50mV

Vd=-1V

Vd=50mV

On/Off>106、60uA/wire

Recent results to be presented by ESSDERC 2010 next week in Sevile

Wire cross-section: 20 nm X 10 nm

010203040506070

1 10 100 1000Gate Length (nm)

nMOSpMOS

(10)(12)

(12x19)

(13x20)

(9x14)(10)

(3)(3)

VDD: 1.0~1.5 V

括弧内は寸法を示す

010203040506070

nMOSpMOS

010203040506070

nMOSpMOS

(10)(12)

(12x19)

(13x20)

(9x14)(10)

(3)(3)

VDD: 1.0~1.5 V

010203040506070

nMOSpMOS

(10)(12)

(12x19)

(13x20)

(9x14)(10)

(3)(3)

VDD: 1.0~1.5 V

010203040506070

nMOSpMOS

010203040506070

nMOSpMOS

(10)(12)

(12x19)

(13x20)

(9x14)(10)

(3)(3)

VDD: 1.0~1.5 V

010203040506070

nMOSpMOS

(10)(12)

(12x19)

(13x20)

(9x14)(10)

(3)(3)

VDD: 1.0~1.5 V

010203040506070

nMOSpMOS

010203040506070

nMOSpMOS

(10)(12)

(12x19)

(13x20)

(9x14)(10)

(3)(3)

VDD: 1.0~1.5 V

本研究で得られたオン電流

(10x20)102µA

Our Work

Bench Mark

Bench MarkBench MarkThis work Ref[11] Ref[12] Ref[13] Ref[14] Ref[15] Ref[4]

NW Cross-section (nm) Rect. Rect. Rect. Cir. Cir. Elliptical Elliptical NW Size (nm) 10x20 10x20 14 10 10 12 13x20

Lg (nm) 65 25 100 30 8 65 35EOT or Tox (nm) 3 1.8 1.8 2 4 3 1.5

Vdd (V) 1.0 1.1 1.2 1.0 1.2 1.2 1.0Ion(uA) per wire 60.1 102 30.3 26.4 37.4 48.4 43.8

Ion(uA/um) by dia. 3117 5010 2170 2640 3740 4030 2592Ion(uA/um) by cir. 1609 2054 430 841 1191 1283 825

SS (mV/dec.) 70 79 68 71 75 ~75 85DIBL (mV/V) 62 56 15 13 22 40-82 65

Ion/Ioff ~1E6 >1E6 >1E5 ~1E6 >1E7 >1E7 ~2E5

Ref[11] by Stmicro Lg=25nm,Tox=1.8nmThis work Lg=65nm,Tox=3nm

Y. Jiang, VLSI 2008, p.34H.-S. Wong, VLSI 2009, p.92

S. Bangsaruntip, IEDM 2009, p.297C. Dupre, IEDM 2008, p. 749S.D.Suk, IEDM 2005, p.735G.Bidel, VLSI 2009, p.240

SiナノワイヤFET

Planer FETS. Kamiyama, IEDM 2009, p. 431

P. Packan, IEDM 2009, p.659

1.2～1.3V

1.0～1.1V

Lg=500～65nm

IIONON/I/IOFF OFF Bench markBench mark

This work

H2 annealingChapter 4

10 nm10 nm

H2 annealing750oC, 2min

1012 1013100El

2 /Vs]

Ninv [cm-2]

1012 1013100El

2 /Vs]

Ninv [cm-2]

1012 1013

2 /Vs]

Ninv [cm-2]

1009080706050

1012 1013

2 /Vs]

Ninv [cm-2]

1009080706050

w/o H2 anneal

w H2 anneal

w/o H2 anneal

w H2 anneal

Change the cross sectionA little improvement of surface roughness

Increase of coulomb scattering

µsrµsr

µcbµcb

Frequency, f [MHz]

I cp[x

20.50 1 1.5

Interface trap density (Dit)Chapter 4

The p+ region actsas a ‘substrate’ contact.

Gated diode

Dit [eV-1cm-2]6.39 x 1011

w H2annealBOX

Trapezoidal pulse+Vbase

ICP=q2fWLDit∆ψs

NWsBOX

Trapezoidal pulse+Vbase

ICP=q2fWLDit∆ψs

w/o H2anneal

Dit [eV-1cm-2]2.24 x 1011

Increase of interface trap density

3. Problems

We have to decrease Si layer thickness to better control of channel potential by gate bias.

Significant decrease in conduction or Ion.

ShortShort--channel effectchannel effectT. Skotnicki, IEDM 2009 Short Course (STMicroelectronics)

DrainDrain--induced barrier loweringinduced barrier loweringT. Skotnicki, IEDM 2010 Short Course (STMicroelectronics)

SubSub--threshold Slopethreshold SlopeT. Skotnicki, IEDM 2010 Short Course (STMicroelectronics)

110 mV/dec

85 mV/dec

75 mV/dec

65 mV/dec

95 mV/dec

3. Problems

Mobility degradation.

S. Bangsaruntip et al., pp.297, IEDM2009 (IBM), K. Tachi et al., pp.313, IEDM2009 (CEA-LETI)

Decreasing the diameter of NW

Problems in MultiProblems in Multi--gategate

Improvedshort-channel control

Severe mobility degradation

Significant µ degradationat diameter < 10 nm

Need to decrease diameter for SCH

K. Uchida et al., pp.47, IEDM2002 (Toshiba)

Problems in SOIProblems in SOI

Mobility is also decreased with decreasing the Si thickness of SOI transistor similar to the NW transistor. 124

When wire diameter becomes less than 10 nm, sudden drop of IdProblem for nanowire

IdDiameter

2. Electron density decrease

If diameter cannot be scaled, SCE cannot be suppressed.

Then, again aggressive EOT scaling of high-k is necessary. 125

< 10 nm1. Mobility degradation

Extremely small distance between the electron and all around Si surface.

Strong scattering of electrons by interaction with all around Si surface.

Decrease of DOS in extremely narrow wire.

3. Problems

Carrier density degradation.

Number of quantum channels

Energy band of Bulk Si

By Prof. Shiraishi of Tsukuba univ.

Energy band of 3 x 3 Si wire

4 channels can be used

128By Profs. Oshiyama and Iwata, U. of Tokyo

Diameter dependence1 nm 2 nm 3 nm 4 nm 6 nm

By Profs. Oshiyama and Iwata, U. of Tokyo

Wire cross section dependence.

What cross section gives best solution forSCE suppression and drive current?.

J. B. Chang et al., pp.12, VLSI2012 (IBM)

VVthth variabilityvariability

nFETs pFETs

Significant increase in Vth variability with decreasing Fin width

K. Kim, pp.1, IEDM2010 (Samsung)1.21.1

202020152010Year

Body Thickness [nm

Multi-Gate

Planar

ITRS2011

Fin width

Trend 1

Trend 2

Trend 3 ?

EOT Scaling TrendsEOT Scaling Trends

Smaller wire/fin width is necessary for SCE suppression

But mobility and ION severely degrade with wire/fin width reduction

Therefore even in multi-gate structures, EOT scaling should be accelerated to provide SCE immunity 131

High-k beyond 0.5 nm

Limit in tLimit in toxox thinningthinning

R.Chau, et al., (Intel) IWGI 2003

Gate oxide should be thicker than mono atomic layer

0.8 nm gate oxide thickness MOSFETs operate0.8 nm Distance of 3 Si atoms 2 mono layers

Limit in tLimit in toxox thinningthinningR.Chau, et al., (Intel) IWGI 2003

1 0.010.1

Gate Length [µm]

Active Power

Passive PowerGate

Leakage

Gate Leakage Power Density becomes significantly large with Lg reduction, and thus, with tox thinning!!

W.F.Clark, (IBM) VLSI 2007 Short Course

To use high-k dielectrics

Thin SiO2

Thick high-k dielectrics

Almost the same electric characteristics

However, very difficult and big challenge!

K: Dielectric Constant

5 times thicker

Small leakageCurrent

K=4K=20

SolutionSolution

SiO2 High-k

Equivalent Oxide Thickness (EOT)Equivalent Oxide Thickness (EOT)

Silicon Substrate

Poly-Si

C Poly

High-kCOX

Equivalent Oxide Thickness (EOT): gate dielectrics itself, Cox

Capacitance Equivalent Thickness (CET): entire gate stack,

Metal gate can eliminate the poly-Si depletion.

Inversion CET = Tinv ≈ EOT + 0.4nm with metal gate electrode

Cmetal

Poly-Si(1020cm-3)

K. Natori, et al., (Tsukuba Univ) SSDM 2005, p.286

CMetal(EOT: 0.1 nm)

Depletion

Cmetal is finite because of quantum effect. In other words electron is not a point charge

located at the interface but distributed charge.

(EOT: 0.3 nm)

Combination of high-k and metal gate is important

R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)

Gas or liquidat 1000 K

Radio activeHe

Li BeB C N O F Ne

① Na Mg Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ① K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ① ① ① ① Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe ③ ① ① ① ① ① ① ① Cs Ba

HfTa W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn

Fr Ra Rf Ha Sg Ns Hs Mt

La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er TmYｂ Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr

Candidates

Na Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ①

Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr

Unstable at Si interfaceSi + MOX M + SiO2①

Si + MOX MSiX + SiO2

Si + MOX M + MSiXOY

Choice of High-k elements for oxide

HfO2 based dielectrics are selected as the

first generation materials, because of

their merit in1) band-offset,

2) dielectric constant3) thermal stability

La2O3 based dielectrics are

thought to be the next generation materials, which may not need a

thicker interfacial layer

0 10 20 30 40 50Dielectric Constant

XPS measurement by Prof. T. Hattori, INFOS 2003

Conduction band offset vs. Dielectric Constant

Band offset

Leakage Current by Tunneling

SiO2-ILHfSix (k~4)

VOHfO2

Si substrate SiO2-IL(k~4)

IOLa2O3silicate

La-rich Si-rich

Si substrate

High PO2Low PO2 High PO2Low PO2

HfO2 case La2O3 case

Direct contact can be achieved with La2O3 by forming silicate at interfaceControl of oxygen partial pressure is the key for processing.

Our approach

K. Kakushima, et al., VLSI2010, p.69

Direct high-k/Si by silicate reaction

SiO2-ILHfSix (k~4)

VOHfO2

Si substrate SiO2-IL(k~4)

IOLa2O3silicate

La-rich Si-rich

Si substrate

High PO2Low PO2 High PO2Low PO2

SiO2 IL formation

Si substrate

silicate formation

Si substrate

HfO2 case La2O3 case

Direct contact can be achieved with La2O3 by forming silicate at interfaceControl of oxygen partial pressusre is the key for processing.

Our approach

K. Kakushima, et al., VLSI2010, p.69

Direct high-k/Si by silicate reaction

1837184018431846Binding energy (eV)

Si sub.

Hf SilicateSiO2

500 oC

Si sub.

Hf SilicateSiO2

500 oC

SiOx-IL

SiOx-IL growth at HfO2/Si Interface

HfO2 + Si + O2→ HfO2 + Si + 2O*→HfO2+SiO2

Phase separator

SiOx-IL is formed after annealingOxygen control is required for optimizing the reaction

Oxygen supplied from W gate electrode

XPS Si1s spectrum

D.J.Lichtenwalner, Tans. ECS 11, 319

TEM image500 oC 30min

H. Shimizu, JJAP, 44, pp. 6131

La-Silicate Reaction at La2O3/Si

La-silicate

500 oC, 30 min

k=8~14

as depo.

300 oC

La-silicate

Si sub.

500 oC

as depo.

300 oC

La-silicate

Si sub.

500 oC

La2O3 + Si + nO2→ La2SiO5, La2Si2O7,

La9.33Si6O26, La10(SiO4)6O3, etc.La2O3 can achieve direct contact of high-k/Si

XPS Si1s spectra TEM image

Direct contact high-k/Si is possible

Flash Lamp

ALDRTAEntrance

Sputterfor MG

EB Deposition for HK5m

Cluster tool for HKMG Stack

Cluster Chambers for HKMG Gate Stack

Flash Lamp Anneal

EB Deposition: HK Sputter: MG

ALD: HK

Entrance

Shutter movement

Si Si SiSi

Metal Metal Metal Metal

Thin Thick

high-k

0.0E+00

5.0E-04

1.0E-03

1.5E-03

2.0E-03

2.5E-03

3.0E-03

3.5E-03

0 0.2 0.4 0.6 0.8 1

Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V

0 0.2 0.4 0.6 0.8 1

Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V

0 0.2 0.4 0.6 0.8 1

Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2VI d

Vth=-0.04VVth=-0.05VVth=-0.06V

Substrate

Moving Mask

SourceElectron Beam

Deposited thin film

L=0.5~100µm (8 kinds)W=10, 20, 50, 100µm(4 kinds)

30 different Trs

1cm×1cm

S Dn+ Sn+SiO2

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

0 0.5 1 1.5 2 2.5 3

EOT ( nm )

2 )Al2O3HfAlO(N)HfO2HfSiO(N)HfTaOLa2O3Nd2O3Pr2O3PrSiOPrTiOSiON/SiNSm2O3SrTiO3Ta2O5TiO2ZrO2(N)ZrSiOZrAlO(N)

Gate Leakage vs EOT, (Vg=|1|V)

-1 -0.5 0 0.5 1Gate Voltage [V]

10kHz 100kHz 1MHz

20 x 20µm2 1.5

-1.5 -1 -0.5 0 0.5Gate Voltage [V]

20 x 20µm2

10kHz 100kHz 1MHz

-1.5 -1 -0.5 0 0.5Gate Voltage [V]

20 x 20µm2

10kHz 100kHz 1MHz

FGA500oC 30min FGA700oC 30min FGA800oC 30min

A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC)

However, high-temperature anneal is necessary for the good interfacial property

substrate

①La gas feed

②Ar purge ③H2O feed

④Ar purge

Laligand H

substrate substrate substrate

1 cycle

La(iPrCp)3 La(FAMD)3

Precursor (ligand)

ALD is indispensable from the manufacturing viewpoint- precise control of film thickness and good uniformity

K. Ozawa, et al., (Tokyo Tech. and AIST) Ext. Abstr. the 16th Workshop on Gate Stack Technology and Physics., 2011, p.107.

ALD of La2O3

① silicate-reaction-formedfresh interface

Si sub.

La2O3 La-silicateSi Si

Fresh interface with silicate reaction

J. S. Jur, et al., Appl. Phys. Lett., Vol. 87, No. 10, (2007) p. 102908

② stress relaxation at interface by glass type structure of La

silicate.

La atomLa-O-Si bonding

Si sub.

SiO4tetrahedron network

FGA800oC is necessary to reduce the interfacial stress

S. D. Kosowsky, et al., Appl. Phys. Lett., Vol. 70, No. 23, (1997) pp. 3119

Physical mechanisms for small DitPhysical mechanisms for small Dit

600 700 800 900 1000As depo

～～

Annealing temperature (oC)

Annealed for 2 sLa2O3(3.5 nm)

W(60 nm)

TiN/W(12 nm)

TiN/W(6 nm)

TiN(45nm)/W(6nm)

-1 -0.5 0 0.5

Vg (V)

Experiment

Cvc fittingTheory

EOT=0.55nm

TaN/(45nm)/W(3nm)900oC, 30min

EOT=0.55nm

0.5 0.55 0.6 0.65 0.7

EOT（nm)

TaN(45nm)/W(3nm)

900oC, 30min

Qfix=1×1011 cm-2

Fixed Charge density: 1×1011 cm-2

0 0.2 0.4 0.6 0.8 1.0

Drain Voltage (V)

Vg= 0.4V

Vg= 0.6V

Vg= 0.8V

Vg= 1.0V

Vg= 0.2V

Vg= 0 V

L/W = 5/20µm

T = 300K

Nsub = 3×1016cm-3

0 0.5 1 1.5 2 2.5

EOT = 0.40nm

L/W = 5/20µm

T = 300K

Nsub = 3×1016cm-3

Eeff [MV/cm]

2 /Vse

EOT=0.40nm

Our Work at TIT: HighOur Work at TIT: High--k k

Our result at TIT

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

0.3 0.4 0.5 0.6 0.7 0.8

ITRS requirement

EOT (nm)

Benchmark of LaBenchmark of La--silicate dielectricssilicate dielectrics

T. Ando, et al., (IBM) IEDM 2009, p.423

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1EOT (nm)

2 /Vse

at 1 MV/cm

Open square : Hf-based oxides

Solid circle: Our data

Our data: La-silicate gate oxide

La-silicate gate oxide

L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng, vol. 88, no. 7, pp. 1317–1322, 2011.

Gate Leakage current Effective Mobility

Si-sub.

SiO2-IL

High-kSmall interfacial state

density at high-k/Si

Oxygen diffusion control for prevention of EOT increase

and oxygen vacancy formation in high-k

Thinning or removal of SiO2-IL for small EOT

Flat metal/high-k interface for better

mobility

Workfunction engineering for Vth control

Interface dipole control for Vth tuning

Suppression of oxygen vacancy

formation

Control of interface reaction and Si diffusion to high-k

Oxygen concentration control for prevention of EOT

increase and oxygen vacancy formation in high-k

Suppression of metal diffusion

Endurance for high temperature process

Remove contaminationintroduced by CVD

Reliability: PBTI, NBTI, TDDB

Suppression of gate leakage current

Suppression of FLP

Issues in high-k/metal gate stack

Si benchmark (nMOSFET)Si benchmark (nMOSFET)

EOT Mobility Vth SS DIBLGate stack Ref.

0.45nmTiN/Cap/HfO2 115cm2/Vs

(at 1x1013cm-2)IMEC

MEE20110.3V

(Lg=10um)

(at 1x1013cm-2)IBM

VLSI2011~0.4V

(Lg=24nm) 90mV/dec 147mV/V

0.59nmMetal/HfO2 130cm2/Vs

(at 1MV/cm)0.45V

(Lg=1um) 75mV/decSematechVLSI2009

0.65nmMetal/Hf-basedSamsungVLSI2011

0.3~0.4V(Lg=~30nm) 90mV/dec 100mV/V

0.95nmMetal/Hf-basedIntel

IEDM2009~0.3V

(Lg=30nm) 100mV/dec ~200mV/V

0.62nmW/La-silicateTokyo Tech.T-ED2012

-0.08V(Lg=10um) ~70mV/dec

155cm2/Vs (at 1MV/cm)

(at 1MV/cm)IBM

VLSI2009

Conclusions 1

Downsizing of MOSFETs is still important for high-speed low-power operation of logic LSIs.

Ioff will limit the downsizing.

Punchthrough component of Ioff will be suppressed by thinning tox and adopting new configuration such as FinFET or nanowire FET.

Direct tunneling will limit the downsizing @Lg = 3 nm.

Even before that, subthreshould leakage would limit the downsizing @ Lg > 3nm, depending on the application.

Conclusions 2

In the application, Ion/Ioff ratio is important.

The ratio is typically 106 for the present devices, however, it degrades significantly with decreasing the supply voltage.

Si nanowire FET has advantage not only on Ioff over planer FET, but also on Ion, because of better mobility and higher channel carrier density.

In order to suppress Ioff with decrease in Lg, the diameter of nanowire, width of fin, or thickness of Si film of SOI need to be shirked.

.However, with decreasing the above diameter, width or thickness less than several nano-meter, very significant decrease in Ion occurs, because of the degradation on mobility and carrier concentration.

Conclusions 3

If the diameter, width or thickness cannot be decreased, we need to decrease the EOT of high-k aggressively in order to suppress Ioff.

High-k EOT reduction trend is very slow – 0.05 nm for each generation --, for the moment.

The limit of EOT scaling is expected to be around 0.4 nm or so, considering the additional capacitances of channel and metal gate.

By changing the high-k material from HfO2 to La-silicate, we can obtain the good operation of MOSFET with EOT = 0.4 nm,

.Metal silicide Shottoky S/D will become important in order to suppress the S/D encroachment to the channel by dopant diffusion.

Conclusions 3

Downsizing of MOFET is becoming more and more important for low power high performance application in the future smart society, and will be accomplished in another 10 to 15 years, although the rate of the downsizing will become slow.

Thus, many challenging technology development will be necessary for another 10 to 15 years.

Thank you very much for your attention.

Futur of Nano CMOS Technology - 東京工業大学 of Nano CMOS Technology ... Still, Si CMOS...

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