Encryption / Decryption VHDL Core Final Presentation Part A

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Technion - Israel institute of technology department of Electrical Engineering . הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל. Encryption / Decryption VHDL Core Final Presentation Part A. Instructor : Mony Orbach Semester :Winter-Spring 2013 - PowerPoint PPT Presentation

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Encryption / Decryption VHDL CoreFinal Presentation

Part A

Instructor : Mony OrbachSemester : Winter-Spring 2013Performed By: Watad Duna , Watad EsamDuration : Year

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

Project’s Goals

• Implementing RSA Encryption Decryption Core.

• Enhancing encryption and decryption processing time.

• Achieving standard safety level

Project(Part a) Goals

• Golden Matlab model.• VHDL RSA Encryption\Decryption Core.• Encryption\Decryption Core Simulation.

RSA Theory - Reminder• Key Generation Algorithm– Generate two large random primes, p and q– Compute n = pq and (phi) φ = (p-1)(q-1) – Choose an integer e, 1<e<phi, such that gcd(e,phi) = 1– Compute the secret exponent d, 1 < d < phi, such that

(e x d) ≡ 1 (mod phi)– The public key is (n, e) and the private key (d, p, q)

RSA Theory - Reminder(Cont.) • Encryption Sender A does the following:

1. Obtains the recipient B's public key (n, e)2. Represents message as a positive integer m, 1< m< n3. Computes c = me mod n4. Sends the c to B

RSA Theory - Reminder(Cont.) • Decryption Recipient B does the following:

1. Uses his private key (n, d) to compute m = cd mod n

2. Extracts the message from the representative m

Golden Model

• Java.math.BigInteger– M = java.math.BigInteger(m);– E = java.math.BigInteger(e);– N = java.math.BigInteger(n);– C = m.modPow(e,n);

System Launching Operations

• RSA algorithm needs parameters (p,q) as input• This inputs will determine another parameter– N,Phi,e,d

• The following code finds all these parameters

System Launching Operations-cont.function res = FindPrimeBiggerThan( input )myres= input;a = java.math.BigInteger('1');primeWereFounded = 0;

while ( primeWereFounded ==0)myres = myres.add(a)primeWereFounded = myres.isProbablePrime(1012456875);

endres = myres;

end

function res = IsRealyPrime( input )a = java.math.BigInteger('2');

%b = java.math.BigInteger('260');zero = java.math.BigInteger('0');one = java.math.BigInteger('1');b = a.pow(260);res = 1;myinput = input;

while(a.compareTo(b)==(-1))if(myinput.mod(a).compareTo(zero) == 0)res = 0;break;

enda = a.add(one);

endres = res;

end

function res = FindE( input,p,q )one = java.math.BigInteger('1');mp = p.subtract(one);mq = q.subtract(one);

phi = mp.multiply(mq);

tmp = java.math.BigInteger('2');startFrom = tmp.pow(255);

while(startFrom.gcd(phi)!=1)startFrom = startFrom.add(one);

endres = startFrom;

end

function res = FindDForE( e , phi )one = java.math.BigInteger('1');tmp = java.math.BigInteger('2');d = tmp.pow(256);

while(d.multiply(e).mod(phi).compareTo(one))d= d.add(one)endres = dend

System Launching Operations- ResultsP = 13407807929942597099574024998205846127479365820592393377723561443721764030073546976801874298166903427690031858186486050853753882811946569946433649006084171

Q= 13407807929942597099574024998205846127479365820592393377723561443721764030073546976801874298168510365734290848462028012946095045414468772940216441841386573

N = PxQ

phi = 179769313486231590772930519078902473361797697894230657273430081157732675805500963132708477322429081537772856017757052452219066775828510814325211150767994823723247172937861228229027691397192757191152180662345359209725607627810522086248050040267465404662290479408319732043037440995227714070917226519336939765240

E = 57896044618658097711785492504343953926634992332820282019728792003956564819971

D =

Enc./Dec Unit Design

regMux

Mux reg

X %nM

controle

reg

The Enc./Dec. Unit – The Algorithm – To calculate c = m^e%n

• Represent e by it’s binary base ( e= e1e2e3e4… ek)• c = m%n• For i=2 to i=k

– If ei=0 then , C (C x C) % n– If ei=1 then , C ( ((C x C) %n) x m%n ) %n

• Return C.– Example e=149 ( e = 10010101)

• i=2 , m^2%n= c (m^1%n x m^1%n ) % n • i=3 , m^4%n= c (m^2%n x m^2%n ) % n • i=4 , m^9%n= c (( (m^4%n x m^4%n ) % n ) x m^1%n) %n• i=5 , m^18%n= c (m^9%n x m^9%n ) % n • i=6 , m^37%n= c (( (m^18%n x m^18%n ) % n ) x m^1%n) %n• i=7 , m^74%n= c (m^37%n x m^37%n ) % n • i=8 , m^149%n= c (( (m^74%n x m^74%n ) % n ) x m^1%n) %n

The Enc./Dec- Mult

Adder

1024

En

trie

s

2048 bits

a

b

Controller

Multiply Unit - Controller• For each bit in b – Say the index of the bit is i :

• If b(i)=0 then the i-output will be 1024 bits vector with value 0• Else the i-output will be 1024 bits vector

– Bits i-0 with value 0– Bits i-i+1024 will a bits– Bit 2048 – i+1024 with value 0

– Simple example :• 1010 x 0101 = 00001010+00000000+00101000+00000000 =

01101010 = 50 = 5 x 10

The Enc./Dec-Mod-Inputs

. In1 : A binary number (2048 bits).

. In2=N : A binary number (1024 bits) . . Select ( technical problem)

- Outputs . Ready : Indicate that the computing was finished.

. Result : The final result In1%In2.

MUX

Mod Unit Design

Subtractor

NMUX

Comp_R

Comp.0

Conc.Unit

Comp.1

Reg

‘1’

In1

In2=N

Result

Ready

Mod Unit- Conc.Unit The unit concatenates zeros . -Input . A binary number (1024 bits) N -Outputs . 1025 binary numbers (2048 bits).

Example :

1

2

1024

0

2

2...

2

N

N

N

N

(1024)(1024 ) ( )

2 [00...0] [ ] [00..00]i

bitsi bits i bits

N N

Mod Unit- NMux The output is the data which has been selected by the select vector. The index

of the last bit of value ‘1’ is the index of the data that would be sent to the output.

-Input .select: vector of 1025 bits. .Data :1025 binary number (2048 bits).-Output . A binary number (2048 bits).

10240 2Data

N

(1025 )select bits

Comp

comp

outputNMuxab

c

( )1

if a bc

Summary

• Acquired a lot of knowledge about Encryption especially RSA Algorithm

• Achieved standard safety level• Top-Down design and encapsulation are very

useful • We adopt abstraction as a style of coping with

the big challenge of the large numbers

Planning Ahead

• Completing simulation successfully.• Synthesis On FPGA.• Timing & Performance enhancements