Post on 19-Nov-2021
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CMOSCMOS INTEGRATED CIRCUIT DESIGN TECHNIQUESINTEGRATED CIRCUIT DESIGN TECHNIQUES
University of University of IoanninaIoannina
BuiltBuilt‐‐In Self TestIn Self Test(BIST)(BIST)
BuiltBuilt‐‐In Self TestIn Self Test(BIST)(BIST)
Dept. of Computer Science and EngineeringDept. of Computer Science and Engineering
Y. Tsiatouhas
OverviewOverview
1.1. Embedded test pattern generationEmbedded test pattern generation
CMOS Integrated Circuit Design TechniquesCMOS Integrated Circuit Design Techniques
2.2. Output response analysisOutput response analysis
3.3. Linear feedback shift registers (LFSRs)Linear feedback shift registers (LFSRs)
4.4. Circular BISTCircular BIST
5.5. BuiltBuilt‐‐in logic blocks observer (BILBO)in logic blocks observer (BILBO)
6.6. The STAMPS architectureThe STAMPS architecture
Built-In Self Test 2
7.7. LFSRLFSR reseeding and bitreseeding and bit‐‐fixingfixing
8.8. Design for DiagnosisDesign for DiagnosisVLSI Systems
and Computer Architecture Lab
2
A General BuiltA General Built‐‐In Self Test (BIST) SchemeIn Self Test (BIST) Scheme
Primary Inputs Primary
OutputsCircuit UnderCircuit Under
TestTest( )( )
MUX
MUX
Chip
ControlControlLogicLogic
(CUT)(CUT)
PatternPatternGeneratorGenerator
SignatureSignatureAnalyzerAnalyzer
BIST Circuitry +ROM
Scan Chains
Built-In Self Test 3
In Built‐In Self Test schemes the test vectors are generated inside the chip and they areapplied to the CUT under the control of the BIST controller. The CUT responses arecompacted by the signature analyzer and the final value (signature), after test completion,is compared with the expected signature. In case of discrepancy the CUT is characterizedas defective. A proper signal (Pass/Fail) is activated to indicate a possible fault detection.
Pass/FailTest_Enable
PseudorandomPseudorandom Pattern GenerationPattern Generation
Linear Feedback Shift Registers ‐ LFSRs
An a LFSR acts as a pseudorandom pattern generator
Step/Cycle Q[2...0]
0 111
1
2
3
110
010
101D Q D QD Q
Q(0) Q(1) Q(2)Flip‐Flop Flip‐Flop Flip‐Flop
Built-In Self Test 4
4
5
6
7
100
001
011
111 repetition!
QCK QCKQCK
CLK
3
An LFSR is fully described by its characteristic polynomial. An LFSR with characteristic polynomial of Ν‐degree is capable to generate a maximallength cycle 2Ν–1 if its polynomial is a primitive polynomial. An Ν‐degree polynomial is primitive if it cannot be factored and it is divisible only byitself and 1 and it divides evenly the xk+1 polynomial only when for the integer k
TheThe Linear Feedback Shift RegisterLinear Feedback Shift Register
itself and 1, and it divides evenly the x +1 polynomial only when for the integer kstands that k=2N–1 but not when k<2N–1.
Step Q[2] Q[1] Q[0]
0 1 1 1
1 1 1 0
2 1 0 1
3 0 1 0D Q D QD Q
Q(0) Q(1) Q(2)
Flip‐Flop Flip‐Flop Flip‐Flopx x2 x31
Built-In Self Test 5
4 1 0 0
5 0 0 1
6 0 1 1
7 1 1 1P(x) = 1.x3+0.x2+1.x+1 = x3+x+1
QCK QCKQCK
CLK
LFSR PropertiesLFSR Properties
The maximal length cycle of an LFSR with a primitive characteristicpolynomial is 2Ν–1.polynomial is 2 1. In a maximal length cycle “1” appears N+1 times while “0” appears N times. The sequence obtained at any stage j of the LFSR is one clock cycle delayedwith respect to the sequence at stage j–1.
Since the generated patterns by an LFSR have a predetermined distribution
Built-In Self Test 6
of grouping bits and the sequences from different stages are self‐correlated (pseudorandom patterns), some faults may be undetectable when this
sequence of patterns is applied. These faults are called: random pattern resistant (RPR) faults.
4
LFSRLFSR in a Typical Test Configurationin a Typical Test ConfigurationP(x)=x4+x2+x+1
LFSR
D Q
QCK
D Q
QCK
D Q
QCK
CLK
Q(0) Q(1) Q(2)
Flip‐Flop Flip‐Flop Flip‐Flop
D Q
QCK
Q(3)
Flip‐Flop1 x x2 x3 x4
Built-In Self Test 7
Scan
Chain 1
Scan
Chain 2
Scan
Chain 3
Scan
Chain 4
Signature AnalysisSignature Analysis
The most common signature analysis technique is the sequential compaction of the CUT responses and the comparison of the final result (signature) with
the expected one. The latter is derived by simulations on the CUT. Usually, an LFSR is exploited for the response compaction. At the end of this
operation the LFSR’s contents is the signature of the circuit.
A faulty circuit is expected to provide a different signature than this of a fault free circuit.
Since response compaction may result in information loss, it is possible a faulty circuit to provide a signature identical to the expected one [the fault
Built-In Self Test 8
faulty circuit to provide a signature identical to the expected one [the fault escapes detection (test escape) and the CUT is characterized as fault free].
This type of information loss is called aliasing.
The probability of aliasing using an LFSR of Ν stages is: Pa=2‐N
5
Output Response CompactionOutput Response Compaction
L F S RCUT
a) Bellmac architecture
XOR
CUT
b) Use of Multiple Input Shift Register ‐MISR
Built-In Self Test 9
FlipFlop
FlipFlop
FlipFlop
FlipFlop
M I S R
XOR
Random Pattern Resistant FaultsRandom Pattern Resistant Faults
RPR
rage
100%ΔFC
Random Pattern Resistant (RPR) Fault Alleviation Techniques
# of Test Patterns
Fault Cover
100 200 300 800700600500400
Built-In Self Test 10
• Weighted pseudorandom pattern generation• Aliasing reduction (e.g. multiple LFSR or MISR, collect multiple signatures)• LFSR reseeding• Multiple polynomial LFSR (reconfigurable LFSRs)• Use of extra deterministic tests stored in a ROM (bit‐fixing or bit‐flipping)
6
S0 S1 S2
ReconfigurableReconfigurable LFSR (I)LFSR (I)
D Q
QCK
D Q
QCK
D Q
QCK
CLK
Q(0) Q(1) Q(2)
Flip‐Flop Flip‐Flop Flip‐Flop
D Q
QCK
Q(3)
Flip‐Flop
S0 S1 S2
Multiple Polynomial LFSR(R fi bl LFSR)
1 x x2 x3 x4
Built-In Self Test 11
(Reconfigurable LFSR)
Standard Configuration
Si Zi Mode
0
10Q(i)
InactiveActive
Si Si
Q(i)
Zi
ReconfigurableReconfigurable LFSR (II)LFSR (II)
S2 S1 S0
Multiple Polynomial LFSR(R fi bl LFSR)
D Q
QCK
D Q
QCK
D Q
QCK
CLK
Q(3) Q(2) Q(1)Flip‐Flop Flip‐Flop Flip‐Flop
D Q
QCK
Q(0)
Flip‐Flop 1xx2x3
x4
Built-In Self Test 12
(Reconfigurable LFSR)
Modular Configuration
Si Zi Mode
0
10Q0
InactiveActive
Si Si
Q(0)
Zi
7
S0 S1 S2
Equivalent LFSR DesignsEquivalent LFSR Designs
0
D Q
QCK
D Q
QCK
D Q
QCK
CLK
Q(0) Q(1) Q(2)
Flip‐Flop Flip‐Flop Flip‐Flop
D Q
QCK
Q(3)
Flip‐Flop1 x x2 x3 x4
S2 S1 S0
P(x)=x4+x3+x+1
0
Built-In Self Test 13
D Q
QCK
D Q
QCK
D Q
QCK
CLK
Q(3) Q(2) Q(1)Flip‐Flop Flip‐Flop Flip‐Flop
D Q
QCK
Q(0)
Flip‐Flop
S2 S1 S0
1xx2x3
x4
0
WeightedWeighted LFSRLFSR
D Q D QD Q D QFlip‐Flop Flip‐Flop Flip‐Flop Flip‐Flop
Built-In Self Test 14
Scan
Chain 1
Scan
Chain 2
Scan
Chain 4
Scan
Chain 3
8
Inputs Outputs
BasicBasic BIST ArchitecturesBIST Architectures (Ι)(Ι)
ControlControl
CUTCUTMUX
MUXLL
FFSSRR
MMIISSRR
XOR
Built-In Self Test 15
LogicLogic ROM
Chip
Pass/Fail
XOR
Test_Enable
+
BasicBasic BIST ArchitecturesBIST Architectures (ΙΙ)(ΙΙ)
Chip
can
Out
Inputs Outputs
LLRR
Input Boundary Sc
tput B
oundary ScanScan Chains
CUTCUT
LL
Built-In Self Test 16
ControlControlLogicLogic
FFSSRR
RROOMM
Pass/Fail
LLFFSSRR
XOR
+
9
PartitioningPartitioning –– AutonomousAutonomous BISTBIST
L F S R
SubSub‐‐CircuitCircuitC1C1
SubSub‐‐CircuitCircuitC2C2
MUX0
1
MUX0
1
Built-In Self Test 17
MUX MUX0 01 1
M I S R
CUTCUT
CombinationalCombinationalLogicLogic
CombinationalCombinationalLogicLogic
STSR _1 STSR_2
Self‐TestShift Register
CircularCircular BISTBIST
CL_1CL_1 CL_2CL_2
CombinationalCombinationalLogicLogicCL_3CL_3
STSR _3
SR 1 SR 2SI SO
Built-In Self Test 18
CombinationalCombinationalLogicLogicCL_4CL_4
CombinationalCombinationalLogic Logic CL_5CL_5
STSR_4
SR_1
STSR_5
SR_2All STSRs operate
either as LFSRs or MISRs
Characteristic polynomial1+xm
m = # STSR Flip‐Flops
10
CircularCircular BISTBIST FlipFlip‐‐FlopFlop
0D QU
X
from logic to logic
STSR FFDj Qj
Z
N/T Z Mode
0 Dj Normal
STSR Flip‐Flop
from logic to logic
SR FFDj Qj
CLK
1
N/T
D Q
CLK
M
to scan FFfrom scan FF
Sj Sj+1
1 SjDj Test (LFSR‐MISR)
B Z M dB
SR Flip‐Flop
Built-In Self Test 19
CLK
D Q
CLK
to scan FFfrom scan FF
Sj Sj+1
B0
B1
ZB0 Z Mode
0
0
Dj
SjDj
Normal
Test (LFSR‐MISR)
B1
0
11
1
0
1
0
Sj
Reset
Scan
Register A
. . .LFSR
. . .
BuiltBuilt‐‐In Logic Blocks Observer In Logic Blocks Observer ‐‐ BILBOBILBO
. . .g
. . .Combinational A
. . .Register B
. . .Combinational B
Register C
. . .
. . .Combinational A
. . .BILBO
. . .Combinational B
MISR
C1
C2
C1
0
1
C2
0
0
Mode
Scan
LFSR+
MISR
SOSI
Built-In Self Test 20
. . .Register C
. . .MISR
1 1 Normal
11
BILBOBILBO Register StructureRegister Structure
. . .C1
D1 D2 Dn
BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop
D Q
Q
C2
0
1
D Q
Q
D Q
Q. . .Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
MUX
MUX
. . .SI
SO
Built-In Self Test 21
. . .
Q1 QnQ2
BILBO RegisterBILBO Register
CLK
BILBOBILBO –– Normal ModeNormal Mode
. . .C1
D1 D2 Dn“1”
BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop
D Q
Q
C2
“1”
“0” “0”0
1
D Q
Q“0”
D Q
Q. . .Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
MUX
MUX
. . .SI
SO
Built-In Self Test 22
. . .
Q1 QnQ2C1 = “1”
C2 = “1”
12
. . .C1
D1 D2 Dn“0”
“0” “0”“0”BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop
BILBOBILBO –– Scan Operation ModeScan Operation Mode
D Q
Q
C2
“0”
0
1
D Q
Q
D Q
Q. . .Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
MUX
MUX
. . .SI
SO
Built-In Self Test 23
. . .
Q1 QnQ2C1 = “0”
C2 = “0”
. . .C1
D1 D2 Dn“1”
BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop
BILBOBILBO –– LFSRLFSR Operation ModeOperation ModeConstant Values
D Q
Q
C2
“0”
0
1
D Q
Q
D Q
Q. . .Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
MUX
MUX
. . .SI
SO
Built-In Self Test 24
. . .
Q1 QnQ2C1 = “1”
C2 = “0”
13
. . .C1
D1 D2 Dn“1”
BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop BILBO FlipBILBO Flip‐‐FlopFlop
BILBOBILBO –– MISRMISR Operation ModeOperation Mode
D Q
Q
C2
“0”
0
1
D Q
Q
D Q
Q. . .Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
Flip
Flip‐‐Flop
Flop
MUX
MUX
. . .SI
SO
Built-In Self Test 25
. . .
Q1 QnQ2C1 = “1”
C2 = “0”
The STUMPS ArchitectureThe STUMPS Architecture
Chip
Linear Phase Shifter
L F S RXOR Cloud
Self‐Test Using MISR and a Parallel Shift Register Sequence Generator
CUTCUT. . .
.
.
.
.
.
.
tput Boundary Scan
Input B
oundary Sca
PrimaryInputs
PrimaryOutputs
scan
chain
scan
chain
scan
chain
scan
chain
Built-In Self Test 26
M I S R
Out anm scan chains
Linear Phase Compactor
XOR Tree
14
Linear Phase ShifterLinear Phase Shifter
S0 S1 S2
LFSR
D Q
QCK
D Q
QCK
D Q
QCK
CLK
Q(0) Q(1) Q(2)
Flip‐Flop Flip‐Flop Flip‐Flop
D Q
QCK
Q(3)
Flip‐Flop
S0 S1 S2
Built-In Self Test 27
Linear PhaseShifter
To scan chains
Linear Phase CompactorLinear Phase CompactorFrom scan chains
Linear Phase
Compactor
MISR
Built-In Self Test 28
D Q
QCK
D Q
QCK
D Q
QCK
CLK
Flip‐Flop Flip‐Flop Flip‐Flop
D Q
QCK
Flip‐Flop
15
LFSRLFSR ReseedingReseeding
Chip
L F S R
r ‐ bits
r – bit seed
CUTCUT
Linear Phase Shifter
Tester
. . .
r – bit seed
r – bit seed
k seeds
scan
chain
scan
chain
scan
chain
scan
chain
Built-In Self Test 29
M I S R
. . .
s s s s
# test vectors
Fault coverage % 100%
1st seed
2nd seed
3rd seed
kth seed
LFSRLFSR and Bitand Bit‐‐FixingFixing
Chip
L F S R
BitBit Fi iFi iO
Embedding Deterministic Patterns
CUTCUT
. . .
. . . BitBit‐‐Fixing Fixing LogicLogic
Fix‐to‐1 signals
Fix‐to‐0 signals
OR
AND
an chain
an chain
an chain
Built-In Self Test 30
M I S R
. . .Fix to 0 signals
sca
sca
sca
m scan chains
16
LFSRLFSR and Bitand Bit‐‐FlippingFlipping
Chip
L F S R
BitBit Fli iFli i
Embedding Deterministic Patterns
CUTCUT. . .
. . .BitBit‐‐Flipping Flipping
LogicLogic
Bit‐flipping whenthe value is “1”
XOR
an chain
an chain
an chain
Built-In Self Test 31
M I S R
. . .
sca
sca
sca
m scan chains
Design for DiagnosisDesign for Diagnosis
As Diagnosiswe define those operations that are performed in order to locate defects in an integrated circuit. This information is used to improve the manufacturing process or the quality of the design and consequently tothe manufacturing process or the quality of the design and consequently to
increase the yield.
Design for testability techniques may increase the difficulty to diagnose faults. A main problem comes from the scan chain output compaction
schemes.
Hardware assisted, software assisted (the inject and evaluate paradigm) and l f l b d h l d f f l dsignal‐profiling based techniques are exploited for fault diagnosis.
In all diagnosis techniques, special diagnosis vectors (or the existing test vectors) are used for defect location.
32Built-In Self Test
17
Chip LFSR & Linear Phase Shifter
nn
Compressed Pattern DiagnosisCompressed Pattern Diagnosis
CUTCUT
. . .
scan
chain
scan
chain
scan
chain
scan
chain
DecoderDecoder
Mask Pattern
Mask Pattern
Response Compaction & MISR
. . .AND
DecoderDecoder
Y. Huang et al, ITC, 2005
33Built-In Self Test
ReferencesReferences
• “Principles of Testing Electronics Systems”, S. Mourad and Y. Zorian, John Wiley& Sons, 2000.
• “Essentials of Electronic Testing: for Digital Memory and Mixed‐Signal VLSI• Essentials of Electronic Testing: for Digital, Memory and Mixed‐Signal VLSICircuits”, M. Bushnell and V. Agrawal, Kluwer Academic Publishers, 2000.
• “Digital Systems Testing and Testable Design”, M. Abramovici, M. Breuer and A.Friedman, Computer Science Press, 1990.
• “Bit‐Fixing in Pseudorandom Sequences for Scan BIST”, N. Touba and J.McCluskey, IEEE Tran. on CAD of Integrated Circuits and Systems, vol. 20, no.4,pp. 546‐555, 2001.
• “System‐on‐Chip Test Architectures”, L‐T Wang, C. Stroud and N. Touba,
Built-In Self Test 34
Morgan‐Kaufmann, 2008.